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From ad50e0e2d310277f06a9c512fe6e31da183ead6e Mon Sep 17 00:00:00 2001
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From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
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Date: Wed, 24 Feb 2021 11:30:34 -0500
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Subject: [PATCH 1/4] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
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RH-Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Message-id: <20210224113037.15599-2-dgilbert@redhat.com>
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Patchwork-id: 101203
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O-Subject: [RHEL-8.4.0 qemu-kvm PATCH 1/4] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
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Bugzilla: 1790620
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Sergio Lopez Pascual <slp@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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From: Cathy Zhang <cathy.zhang@intel.com>
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AVX512_VP2INTERSECT compute vector pair intersection to a pair
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of mask registers, which is introduced with intel Tiger Lake,
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defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].
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Refer to the following release spec:
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https://software.intel.com/sites/default/files/managed/c5/15/\
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architecture-instruction-set-extensions-programming-reference.pdf
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Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
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Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 353f98c9ad52ff4b8cfe553c90be04f747a14c98)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index ff39fc9905..67dab94aa5 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1078,7 +1078,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.feat_names = {
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NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
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NULL, NULL, NULL, NULL,
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- NULL, NULL, "md-clear", NULL,
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+ "avx512-vp2intersect", NULL, "md-clear", NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL /* pconfig */, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index f3da25cb8a..8e2e52ed31 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -770,6 +770,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
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/* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
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+/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
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+#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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--
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2.27.0
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