|
 |
0727d3 |
From 3ba6092159b6e3b25505af2a49c0f6ac99043db9 Mon Sep 17 00:00:00 2001
|
|
|
0727d3 |
From: Jing Liu <jing2.liu@intel.com>
|
|
|
0727d3 |
Date: Wed, 16 Feb 2022 22:04:28 -0800
|
|
|
0727d3 |
Subject: [PATCH 06/24] x86: Add AMX XTILECFG and XTILEDATA components
|
|
|
0727d3 |
|
|
|
0727d3 |
RH-Author: Paul Lai <plai@redhat.com>
|
|
|
0727d3 |
RH-MergeRequest: 176: Enable KVM AMX support
|
|
|
0727d3 |
RH-Commit: [6/13] 95229f87b4494631d57232f374a174f7bc95843a
|
|
|
0727d3 |
RH-Bugzilla: 1916415
|
|
|
0727d3 |
RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
|
|
|
0727d3 |
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
|
|
|
0727d3 |
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
0727d3 |
|
|
|
0727d3 |
The AMX TILECFG register and the TMMx tile data registers are
|
|
|
0727d3 |
saved/restored via XSAVE, respectively in state component 17
|
|
|
0727d3 |
(64 bytes) and state component 18 (8192 bytes).
|
|
|
0727d3 |
|
|
|
0727d3 |
Add AMX feature bits to x86_ext_save_areas array to set
|
|
|
0727d3 |
up AMX components. Add structs that define the layout of
|
|
|
0727d3 |
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
|
|
|
0727d3 |
structs sizes.
|
|
|
0727d3 |
|
|
|
0727d3 |
Signed-off-by: Jing Liu <jing2.liu@intel.com>
|
|
|
0727d3 |
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
|
|
|
0727d3 |
Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
|
|
|
0727d3 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
0727d3 |
(cherry picked from commit 1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8)
|
|
|
0727d3 |
Signed-off-by: Paul Lai <plai@redhat.com>
|
|
|
0727d3 |
---
|
|
|
0727d3 |
target/i386/cpu.c | 8 ++++++++
|
|
|
0727d3 |
target/i386/cpu.h | 18 +++++++++++++++++-
|
|
|
0727d3 |
2 files changed, 25 insertions(+), 1 deletion(-)
|
|
|
0727d3 |
|
|
|
0727d3 |
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
|
0727d3 |
index f44fad3a2a..0453c27c9d 100644
|
|
|
0727d3 |
--- a/target/i386/cpu.c
|
|
|
0727d3 |
+++ b/target/i386/cpu.c
|
|
|
0727d3 |
@@ -1401,6 +1401,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
|
|
|
0727d3 |
[XSTATE_PKRU_BIT] =
|
|
|
0727d3 |
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
|
|
|
0727d3 |
.size = sizeof(XSavePKRU) },
|
|
|
0727d3 |
+ [XSTATE_XTILE_CFG_BIT] = {
|
|
|
0727d3 |
+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
|
|
|
0727d3 |
+ .size = sizeof(XSaveXTILECFG),
|
|
|
0727d3 |
+ },
|
|
|
0727d3 |
+ [XSTATE_XTILE_DATA_BIT] = {
|
|
|
0727d3 |
+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
|
|
|
0727d3 |
+ .size = sizeof(XSaveXTILEDATA)
|
|
|
0727d3 |
+ },
|
|
|
0727d3 |
};
|
|
|
0727d3 |
|
|
|
0727d3 |
static uint32_t xsave_area_size(uint64_t mask)
|
|
|
0727d3 |
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
|
0727d3 |
index 5d9702a991..e1dd8b9555 100644
|
|
|
0727d3 |
--- a/target/i386/cpu.h
|
|
|
0727d3 |
+++ b/target/i386/cpu.h
|
|
|
0727d3 |
@@ -537,6 +537,8 @@ typedef enum X86Seg {
|
|
|
0727d3 |
#define XSTATE_ZMM_Hi256_BIT 6
|
|
|
0727d3 |
#define XSTATE_Hi16_ZMM_BIT 7
|
|
|
0727d3 |
#define XSTATE_PKRU_BIT 9
|
|
|
0727d3 |
+#define XSTATE_XTILE_CFG_BIT 17
|
|
|
0727d3 |
+#define XSTATE_XTILE_DATA_BIT 18
|
|
|
0727d3 |
|
|
|
0727d3 |
#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
|
|
|
0727d3 |
#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
|
|
|
0727d3 |
@@ -845,6 +847,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
|
|
|
0727d3 |
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
|
|
|
0727d3 |
/* AVX512_FP16 instruction */
|
|
|
0727d3 |
#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
|
|
|
0727d3 |
+/* AMX tile (two-dimensional register) */
|
|
|
0727d3 |
+#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
|
|
|
0727d3 |
/* Speculation Control */
|
|
|
0727d3 |
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
|
|
|
0727d3 |
/* Single Thread Indirect Branch Predictors */
|
|
|
0727d3 |
@@ -1348,6 +1352,16 @@ typedef struct XSavePKRU {
|
|
|
0727d3 |
uint32_t padding;
|
|
|
0727d3 |
} XSavePKRU;
|
|
|
0727d3 |
|
|
|
0727d3 |
+/* Ext. save area 17: AMX XTILECFG state */
|
|
|
0727d3 |
+typedef struct XSaveXTILECFG {
|
|
|
0727d3 |
+ uint8_t xtilecfg[64];
|
|
|
0727d3 |
+} XSaveXTILECFG;
|
|
|
0727d3 |
+
|
|
|
0727d3 |
+/* Ext. save area 18: AMX XTILEDATA state */
|
|
|
0727d3 |
+typedef struct XSaveXTILEDATA {
|
|
|
0727d3 |
+ uint8_t xtiledata[8][1024];
|
|
|
0727d3 |
+} XSaveXTILEDATA;
|
|
|
0727d3 |
+
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
|
|
|
0727d3 |
@@ -1355,6 +1369,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
|
|
|
0727d3 |
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
|
|
|
0727d3 |
+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
|
|
|
0727d3 |
+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
|
|
|
0727d3 |
|
|
|
0727d3 |
typedef struct ExtSaveArea {
|
|
|
0727d3 |
uint32_t feature, bits;
|
|
|
0727d3 |
@@ -1362,7 +1378,7 @@ typedef struct ExtSaveArea {
|
|
|
0727d3 |
uint32_t ecx;
|
|
|
0727d3 |
} ExtSaveArea;
|
|
|
0727d3 |
|
|
|
0727d3 |
-#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
|
|
|
0727d3 |
+#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
|
|
|
0727d3 |
|
|
|
0727d3 |
extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
|
|
|
0727d3 |
|
|
|
0727d3 |
--
|
|
|
0727d3 |
2.35.3
|
|
|
0727d3 |
|