Blame SOURCES/kvm-target-ppc-add-basic-support-for-PTCR-on-POWER9.patch

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From 3b97963ddb435e25f758032691cb2315570a2093 Mon Sep 17 00:00:00 2001
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From: David Gibson <dgibson@redhat.com>
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Date: Mon, 12 Nov 2018 01:28:32 +0000
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Subject: [PATCH 01/16] target/ppc: add basic support for PTCR on POWER9
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: David Gibson <dgibson@redhat.com>
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Message-id: <20181112012835.21863-2-dgibson@redhat.com>
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Patchwork-id: 82978
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O-Subject: [RHEL-8 qemu-kvm PATCH 1/4] target/ppc: add basic support for PTCR on POWER9
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Bugzilla: 1639069
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Serhii Popovych <spopovyc@redhat.com>
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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From: Cédric Le Goater <clg@kaod.org>
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The Partition Table Control Register (PTCR) is a hypervisor privileged
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SPR. It contains the host real address of the Partition Table and its
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size.
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Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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(cherry picked from commit 4a7518e0fdaa20525730ae0709a4afa0960a6c67)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1639069
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Signed-off-by: David Gibson <dgibson@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 target/ppc/cpu.h            |  2 ++
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 target/ppc/helper.h         |  1 +
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 target/ppc/misc_helper.c    | 12 ++++++++++++
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 target/ppc/mmu-book3s-v3.h  |  6 ++++++
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 target/ppc/mmu_helper.c     | 29 +++++++++++++++++++++++++++++
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 target/ppc/translate.c      |  3 +++
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 target/ppc/translate_init.c | 18 ++++++++++++++++++
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 7 files changed, 71 insertions(+)
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diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
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index 1932c2e..8f3cf44 100644
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--- a/target/ppc/cpu.h
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+++ b/target/ppc/cpu.h
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@@ -1313,6 +1313,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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 #if !defined(CONFIG_USER_ONLY)
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 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
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+void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
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 #endif /* !defined(CONFIG_USER_ONLY) */
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 void ppc_store_msr (CPUPPCState *env, target_ulong value);
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@@ -1604,6 +1605,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
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 #define SPR_BOOKE_GIVOR13     (0x1BC)
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 #define SPR_BOOKE_GIVOR14     (0x1BD)
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 #define SPR_TIR               (0x1BE)
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+#define SPR_PTCR              (0x1D0)
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 #define SPR_BOOKE_SPEFSCR     (0x200)
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 #define SPR_Exxx_BBEAR        (0x201)
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 #define SPR_Exxx_BBTAR        (0x202)
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diff --git a/target/ppc/helper.h b/target/ppc/helper.h
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index 5b73917..19453c6 100644
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--- a/target/ppc/helper.h
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+++ b/target/ppc/helper.h
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@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
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 #if !defined(CONFIG_USER_ONLY)
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 #if defined(TARGET_PPC64)
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 DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
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+DEF_HELPER_2(store_ptcr, void, env, tl)
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 #endif
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 DEF_HELPER_2(store_sdr1, void, env, tl)
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 DEF_HELPER_2(store_pidr, void, env, tl)
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diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
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index 0e42178..8c8cba5 100644
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--- a/target/ppc/misc_helper.c
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+++ b/target/ppc/misc_helper.c
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@@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
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     }
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 }
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+#if defined(TARGET_PPC64)
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+void helper_store_ptcr(CPUPPCState *env, target_ulong val)
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+{
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+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
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+
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+    if (env->spr[SPR_PTCR] != val) {
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+        ppc_store_ptcr(env, val);
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+        tlb_flush(CPU(cpu));
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+    }
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+}
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+#endif /* defined(TARGET_PPC64) */
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+
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 void helper_store_pidr(CPUPPCState *env, target_ulong val)
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 {
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     PowerPCCPU *cpu = ppc_env_get_cpu(env);
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diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
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index 56095da..fdf8098 100644
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--- a/target/ppc/mmu-book3s-v3.h
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+++ b/target/ppc/mmu-book3s-v3.h
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@@ -22,6 +22,12 @@
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 #ifndef CONFIG_USER_ONLY
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+/*
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+ * Partition table definitions
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+ */
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+#define PTCR_PATB               0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
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+#define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
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+
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 /* Partition Table Entry Fields */
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 #define PATBE1_GR 0x8000000000000000
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diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
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index 5568d16..e2197a5 100644
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--- a/target/ppc/mmu_helper.c
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+++ b/target/ppc/mmu_helper.c
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@@ -2028,6 +2028,35 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
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     env->spr[SPR_SDR1] = value;
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 }
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+#if defined(TARGET_PPC64)
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+void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
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+{
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+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
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+    target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
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+    target_ulong patbsize = value & PTCR_PATS;
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+
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+    qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
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+
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+    assert(!cpu->vhyp);
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+    assert(env->mmu_model & POWERPC_MMU_3_00);
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+
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+    if (value & ~ptcr_mask) {
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+        error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
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+                     value & ~ptcr_mask);
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+        value &= ptcr_mask;
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+    }
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+
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+    if (patbsize > 24) {
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+        error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
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+                     " stored in PTCR", patbsize);
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+        return;
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+    }
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+
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+    env->spr[SPR_PTCR] = value;
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+}
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+
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+#endif /* defined(TARGET_PPC64) */
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+
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 /* Segment registers load and store */
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 target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
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 {
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diff --git a/target/ppc/translate.c b/target/ppc/translate.c
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index 3457d29..7da9b67 100644
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--- a/target/ppc/translate.c
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+++ b/target/ppc/translate.c
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@@ -7136,6 +7136,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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         if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
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             cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
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         }
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+        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
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+            cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
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+        }
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         cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
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                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);
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         break;
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diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
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index 17b06c7..926efbc 100644
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--- a/target/ppc/translate_init.c
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+++ b/target/ppc/translate_init.c
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@@ -420,6 +420,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
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     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
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     tcg_temp_free(t0);
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 }
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+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
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+{
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+    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
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+}
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+
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 #endif
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 #endif
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@@ -8167,6 +8172,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
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 #endif
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 }
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+static void gen_spr_power9_mmu(CPUPPCState *env)
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+{
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+#if !defined(CONFIG_USER_ONLY)
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+    /* Partition Table Control */
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+    spr_register_hv(env, SPR_PTCR, "PTCR",
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+                    SPR_NOACCESS, SPR_NOACCESS,
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+                    SPR_NOACCESS, SPR_NOACCESS,
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+                    &spr_read_generic, &spr_write_ptcr,
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+                    0x00000000);
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+#endif
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+}
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+
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 static void init_proc_book3s_common(CPUPPCState *env)
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 {
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     gen_spr_ne_601(env);
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@@ -8761,6 +8778,7 @@ static void init_proc_POWER9(CPUPPCState *env)
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     gen_spr_power8_ic(env);
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     gen_spr_power8_book4(env);
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     gen_spr_power8_rpr(env);
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+    gen_spr_power9_mmu(env);
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     /* POWER9 Specific registers */
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     spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
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-- 
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1.8.3.1
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