|
 |
4841a6 |
From 416de21d11540a927cceb533bf54ce28ffa15ad6 Mon Sep 17 00:00:00 2001
|
|
|
60061b |
From: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
60061b |
Date: Thu, 24 Mar 2022 09:21:41 +0100
|
|
|
4841a6 |
Subject: [PATCH 2/3] target/i386: properly reset TSC on reset
|
|
|
60061b |
|
|
|
60061b |
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
4841a6 |
RH-MergeRequest: 172: target/i386: properly reset TSC on reset
|
|
|
4841a6 |
RH-Commit: [1/1] 7008bc5d02ad0a2d8b78259459d22d8f0986c989
|
|
|
4841a6 |
RH-Bugzilla: 2070417
|
|
|
60061b |
RH-Acked-by: Marcelo Tosatti <None>
|
|
|
60061b |
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
|
|
|
60061b |
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
|
|
60061b |
|
|
|
60061b |
Some versions of Windows hang on reboot if their TSC value is greater
|
|
|
60061b |
than 2^54. The calibration of the Hyper-V reference time overflows
|
|
|
60061b |
and fails; as a result the processors' clock sources are out of sync.
|
|
|
60061b |
|
|
|
60061b |
The issue is that the TSC _should_ be reset to 0 on CPU reset and
|
|
|
60061b |
QEMU tries to do that. However, KVM special cases writing 0 to the
|
|
|
60061b |
TSC and thinks that QEMU is trying to hot-plug a CPU, which is
|
|
|
60061b |
correct the first time through but not later. Thwart this valiant
|
|
|
60061b |
effort and reset the TSC to 1 instead, but only if the CPU has been
|
|
|
60061b |
run once.
|
|
|
60061b |
|
|
|
60061b |
For this to work, env->tsc has to be moved to the part of CPUArchState
|
|
|
60061b |
that is not zeroed at the beginning of x86_cpu_reset.
|
|
|
60061b |
|
|
|
60061b |
Reported-by: Vadim Rozenfeld <vrozenfe@redhat.com>
|
|
|
60061b |
Supersedes: <20220324082346.72180-1-pbonzini@redhat.com>
|
|
|
60061b |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
60061b |
(cherry picked from commit 5286c3662294119dc2dd1e9296757337211451f6)
|
|
|
60061b |
---
|
|
|
60061b |
target/i386/cpu.c | 13 +++++++++++++
|
|
|
60061b |
target/i386/cpu.h | 2 +-
|
|
|
60061b |
2 files changed, 14 insertions(+), 1 deletion(-)
|
|
|
60061b |
|
|
|
60061b |
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
|
60061b |
index 6e25d13339..dd6935b1dd 100644
|
|
|
60061b |
--- a/target/i386/cpu.c
|
|
|
60061b |
+++ b/target/i386/cpu.c
|
|
|
60061b |
@@ -5871,6 +5871,19 @@ static void x86_cpu_reset(DeviceState *dev)
|
|
|
60061b |
env->xstate_bv = 0;
|
|
|
60061b |
|
|
|
60061b |
env->pat = 0x0007040600070406ULL;
|
|
|
60061b |
+
|
|
|
60061b |
+ if (kvm_enabled()) {
|
|
|
60061b |
+ /*
|
|
|
60061b |
+ * KVM handles TSC = 0 specially and thinks we are hot-plugging
|
|
|
60061b |
+ * a new CPU, use 1 instead to force a reset.
|
|
|
60061b |
+ */
|
|
|
60061b |
+ if (env->tsc != 0) {
|
|
|
60061b |
+ env->tsc = 1;
|
|
|
60061b |
+ }
|
|
|
60061b |
+ } else {
|
|
|
60061b |
+ env->tsc = 0;
|
|
|
60061b |
+ }
|
|
|
60061b |
+
|
|
|
60061b |
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
|
|
|
60061b |
if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
|
|
|
60061b |
env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
|
|
|
60061b |
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
|
60061b |
index 04f2b790c9..c6a6c871f1 100644
|
|
|
60061b |
--- a/target/i386/cpu.h
|
|
|
60061b |
+++ b/target/i386/cpu.h
|
|
|
60061b |
@@ -1510,7 +1510,6 @@ typedef struct CPUX86State {
|
|
|
60061b |
target_ulong kernelgsbase;
|
|
|
60061b |
#endif
|
|
|
60061b |
|
|
|
60061b |
- uint64_t tsc;
|
|
|
60061b |
uint64_t tsc_adjust;
|
|
|
60061b |
uint64_t tsc_deadline;
|
|
|
60061b |
uint64_t tsc_aux;
|
|
|
60061b |
@@ -1660,6 +1659,7 @@ typedef struct CPUX86State {
|
|
|
60061b |
int64_t tsc_khz;
|
|
|
60061b |
int64_t user_tsc_khz; /* for sanity check only */
|
|
|
60061b |
uint64_t apic_bus_freq;
|
|
|
60061b |
+ uint64_t tsc;
|
|
|
60061b |
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
|
|
|
60061b |
void *xsave_buf;
|
|
|
60061b |
uint32_t xsave_buf_len;
|
|
|
60061b |
--
|
|
|
4841a6 |
2.35.1
|
|
|
60061b |
|