|
|
34b321 |
From f9a24822687113e34194f05aeb641365b8202e9e Mon Sep 17 00:00:00 2001
|
|
|
34b321 |
From: Amit Shah <amit.shah@redhat.com>
|
|
|
34b321 |
Date: Wed, 25 Nov 2015 05:51:34 +0100
|
|
|
34b321 |
Subject: [PATCH 4/6] target-i386: get/put MSR_TSC_AUX across reset and
|
|
|
34b321 |
migration
|
|
|
34b321 |
|
|
|
34b321 |
Message-id: <daab7f1c955ec81df8aff4ab10fd6ae17e16e99e.1448430513.git.amit.shah@redhat.com>
|
|
|
34b321 |
Patchwork-id: 68467
|
|
|
34b321 |
O-Subject: [RHEL 7.3 qemu-kvm PATCH 1/1] target-i386: get/put MSR_TSC_AUX across reset and migration
|
|
|
34b321 |
Bugzilla: 1265427
|
|
|
34b321 |
RH-Acked-by: Juan Quintela <quintela@redhat.com>
|
|
|
34b321 |
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
34b321 |
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
34b321 |
|
|
|
34b321 |
There's one report of migration breaking due to missing MSR_TSC_AUX
|
|
|
34b321 |
save/restore. Fix this by adding a new subsection that saves the state
|
|
|
34b321 |
of this MSR.
|
|
|
34b321 |
|
|
|
34b321 |
https://bugzilla.redhat.com/show_bug.cgi?id=1261797
|
|
|
34b321 |
|
|
|
34b321 |
Reported-by: Xiaoqing Wei <xwei@redhat.com>
|
|
|
34b321 |
Signed-off-by: Amit Shah <amit.shah@redhat.com>
|
|
|
34b321 |
CC: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
34b321 |
CC: Juan Quintela <quintela@redhat.com>
|
|
|
34b321 |
CC: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
|
|
|
34b321 |
CC: Marcelo Tosatti <mtosatti@redhat.com>
|
|
|
34b321 |
CC: Richard Henderson <rth@twiddle.net>
|
|
|
34b321 |
CC: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
34b321 |
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
34b321 |
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
34b321 |
(cherry picked from commit c9b8f6b6210847b4381c5b2ee172b1c7eb9985d6)
|
|
|
34b321 |
Signed-off-by: Amit Shah <amit.shah@redhat.com>
|
|
|
34b321 |
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
34b321 |
---
|
|
|
34b321 |
target-i386/kvm.c | 14 ++++++++++++++
|
|
|
34b321 |
1 file changed, 14 insertions(+)
|
|
|
34b321 |
|
|
|
34b321 |
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
|
|
|
34b321 |
index c91bfb8..e1b0ca2 100644
|
|
|
34b321 |
--- a/target-i386/kvm.c
|
|
|
34b321 |
+++ b/target-i386/kvm.c
|
|
|
34b321 |
@@ -63,6 +63,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
|
|
|
34b321 |
|
|
|
34b321 |
static bool has_msr_star;
|
|
|
34b321 |
static bool has_msr_hsave_pa;
|
|
|
34b321 |
+static bool has_msr_tsc_aux;
|
|
|
34b321 |
static bool has_msr_tsc_adjust;
|
|
|
34b321 |
static bool has_msr_tsc_deadline;
|
|
|
34b321 |
static bool has_msr_async_pf_en;
|
|
|
34b321 |
@@ -774,6 +775,10 @@ static int kvm_get_supported_msrs(KVMState *s)
|
|
|
34b321 |
has_msr_hsave_pa = true;
|
|
|
34b321 |
continue;
|
|
|
34b321 |
}
|
|
|
34b321 |
+ if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
|
|
|
34b321 |
+ has_msr_tsc_aux = true;
|
|
|
34b321 |
+ continue;
|
|
|
34b321 |
+ }
|
|
|
34b321 |
if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
|
|
|
34b321 |
has_msr_tsc_adjust = true;
|
|
|
34b321 |
continue;
|
|
|
34b321 |
@@ -1159,6 +1164,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
|
|
|
34b321 |
if (has_msr_hsave_pa) {
|
|
|
34b321 |
kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
|
|
|
34b321 |
}
|
|
|
34b321 |
+ if (has_msr_tsc_aux) {
|
|
|
34b321 |
+ kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
|
|
|
34b321 |
+ }
|
|
|
34b321 |
if (has_msr_tsc_adjust) {
|
|
|
34b321 |
kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
|
|
|
34b321 |
}
|
|
|
34b321 |
@@ -1507,6 +1515,9 @@ static int kvm_get_msrs(X86CPU *cpu)
|
|
|
34b321 |
if (has_msr_hsave_pa) {
|
|
|
34b321 |
msrs[n++].index = MSR_VM_HSAVE_PA;
|
|
|
34b321 |
}
|
|
|
34b321 |
+ if (has_msr_tsc_aux) {
|
|
|
34b321 |
+ msrs[n++].index = MSR_TSC_AUX;
|
|
|
34b321 |
+ }
|
|
|
34b321 |
if (has_msr_tsc_adjust) {
|
|
|
34b321 |
msrs[n++].index = MSR_TSC_ADJUST;
|
|
|
34b321 |
}
|
|
|
34b321 |
@@ -1636,6 +1647,9 @@ static int kvm_get_msrs(X86CPU *cpu)
|
|
|
34b321 |
case MSR_IA32_TSC:
|
|
|
34b321 |
env->tsc = msrs[i].data;
|
|
|
34b321 |
break;
|
|
|
34b321 |
+ case MSR_TSC_AUX:
|
|
|
34b321 |
+ env->tsc_aux = msrs[i].data;
|
|
|
34b321 |
+ break;
|
|
|
34b321 |
case MSR_TSC_ADJUST:
|
|
|
34b321 |
env->tsc_adjust = msrs[i].data;
|
|
|
34b321 |
break;
|
|
|
34b321 |
--
|
|
|
34b321 |
1.8.3.1
|
|
|
34b321 |
|