From 6d0877d3a5dff82b854a7eee38ef7558dfa1d4ef Mon Sep 17 00:00:00 2001

From: Eduardo Habkost <ehabkost@redhat.com>

Date: Wed, 13 Dec 2017 15:42:56 -0200

Subject: [PATCH 2/3] target-i386: add support for SPEC_CTRL MSR

RH-Author: Eduardo Habkost <ehabkost@redhat.com>

Message-id: <20171213174257.20475-3-ehabkost@redhat.com>

Patchwork-id: n/a

O-Subject: [CONFIDENTIAL][RHEL-7.4.z qemu-kvm PATCH v2 2/3] target-i386: add

 support for SPEC_CTRL MSR

Bugzilla: CVE-2017-5715

RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>

RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>

RH-Acked-by: Wainer dos Santos Moschetta <wainersm@redhat.com>

---

 target-i386/cpu.h     |  4 ++++

 target-i386/kvm.c     | 15 +++++++++++++++

 target-i386/machine.c | 21 +++++++++++++++++++++

 3 files changed, 40 insertions(+)

diff --git a/target-i386/cpu.h b/target-i386/cpu.h

index 5697dc6..b23242d 100644

--- a/target-i386/cpu.h

+++ b/target-i386/cpu.h

@@ -304,6 +304,7 @@

 #define MSR_IA32_APICBASE_ENABLE        (1<<11)

 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

 #define MSR_TSC_ADJUST                  0x0000003b

+#define MSR_IA32_SPEC_CTRL              0x48

 #define MSR_IA32_TSCDEADLINE            0x6e0

 #define MSR_P6_PERFCTR0                 0xc1

@@ -958,6 +959,7 @@ typedef struct CPUX86State {

     uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];

     uint64_t msr_gp_counters[MAX_GP_COUNTERS];

     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];

+

     uint64_t msr_hv_hypercall;

     uint64_t msr_hv_guest_os_id;

     uint64_t msr_hv_vapic;

@@ -1030,6 +1032,8 @@ typedef struct CPUX86State {

     uint64_t xcr0;

     uint64_t xss;

+    uint64_t spec_ctrl;

+

     TPRAccess tpr_access_type;

 } CPUX86State;

diff --git a/target-i386/kvm.c b/target-i386/kvm.c

index 6a479f4..ff58314 100644

--- a/target-i386/kvm.c

+++ b/target-i386/kvm.c

@@ -77,6 +77,7 @@ static bool has_msr_hv_vapic;

 static bool has_msr_hv_tsc;

 static bool has_msr_mtrr;

 static bool has_msr_xss;

+static bool has_msr_spec_ctrl;

 static bool has_msr_architectural_pmu;

 static uint32_t num_architectural_pmu_counters;

@@ -800,6 +801,10 @@ static int kvm_get_supported_msrs(KVMState *s)

                     has_msr_xss = true;

                     continue;

                 }

+                if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {

+                    has_msr_spec_ctrl = true;

+                    continue;

+                }

             }

         }

@@ -1185,6 +1190,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)

     if (has_msr_xss) {

         kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);

     }

+    if (has_msr_spec_ctrl) {

+        kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl);

+    }

 #ifdef TARGET_X86_64

     if (lm_capable_kernel) {

         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);

@@ -1193,6 +1201,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)

         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);

     }

 #endif

+

     if (level == KVM_PUT_FULL_STATE) {

         /*

          * KVM is yet unable to synchronize TSC values of multiple VCPUs on

@@ -1541,6 +1550,9 @@ static int kvm_get_msrs(X86CPU *cpu)

     if (has_msr_xss) {

         msrs[n++].index = MSR_IA32_XSS;

     }

+    if (has_msr_spec_ctrl) {

+        msrs[n++].index = MSR_IA32_SPEC_CTRL;

+    }

     if (!env->tsc_valid) {

@@ -1783,6 +1795,9 @@ static int kvm_get_msrs(X86CPU *cpu)

                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;

             }

             break;

+        case MSR_IA32_SPEC_CTRL:

+            env->spec_ctrl = msrs[i].data;

+            break;

         }

     }

diff --git a/target-i386/machine.c b/target-i386/machine.c

index ce7fcd3..4092cae 100644

--- a/target-i386/machine.c

+++ b/target-i386/machine.c

@@ -722,6 +722,24 @@ static const VMStateDescription vmstate_xss = {

     }

 };

+static bool spec_ctrl_needed(void *opaque)

+{

+    X86CPU *cpu = opaque;

+    CPUX86State *env = &cpu->env;

+

+    return env->spec_ctrl != 0;

+}

+

+static const VMStateDescription vmstate_spec_ctrl = {

+    .name = "cpu/spec_ctrl",

+    .version_id = 1,

+    .minimum_version_id = 1,

+    .fields = (VMStateField[]){

+        VMSTATE_UINT64(env.spec_ctrl, X86CPU),

+        VMSTATE_END_OF_LIST()

+    }

+};

+

 const VMStateDescription vmstate_x86_cpu = {

     .name = "cpu",

     .version_id = 12,

@@ -871,6 +889,9 @@ const VMStateDescription vmstate_x86_cpu = {

          }, {

             .vmsd = &vmstate_xss,

             .needed = xss_needed,

+        }, {

+            .vmsd = &vmstate_spec_ctrl,

+            .needed = spec_ctrl_needed,

         } , {

             /* empty */

         }

-- 

1.8.3.1