Blame SOURCES/kvm-target-i386-add-feature-flags-for-CPUID-EAX-0xd-ECX-.patch

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From 5fcaf5176d7545518c76f3aa8ea7ce6fb063c62d Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Wed, 6 Jul 2016 20:47:52 +0200
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Subject: [PATCH 1/2] target-i386: add feature flags for CPUID[EAX=0xd, ECX=1]
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <1467838073-23873-2-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 71051
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O-Subject: [RHEL-7.3 qemu-kvm PATCH 1/2] target-i386: add feature flags for CPUID[EAX=0xd, ECX=1]
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Bugzilla: 1327599
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
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These represent xsave-related capabilities of the processor, and KVM may
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or may not support them.
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Add feature bits so that they are considered by "-cpu ...,enforce", and use
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the new feature work instead of calling kvm_arch_get_supported_cpuid.
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Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS.
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Neither KVM nor any commonly available hardware supports it anyway.
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RHEL backport notes:
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* In addition to allowing xsave flags to be configured, this
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  patch is a bug fix because we shouldn't use
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  kvm_arch_supported_cpuid() directly when configuring CPUID for
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  the guest
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* tcg_features didn't exist, handle it inside x86_cpu_realizefn()
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  directly in the !kvm_enabled() check
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* As the unmigratable_flags mechanism is not present yet,
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  remove the "xsaves" flag name so it can't be enabled manually
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  (otherwise we would need to backport upstream commit
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  18cd2c17b5370369a886155c001da0a7f54bbcca too)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 target-i386/cpu.c | 28 +++++++++++++++++++++++++++-
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 target-i386/cpu.h |  6 ++++++
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 2 files changed, 33 insertions(+), 1 deletion(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 06efe17..6650c72 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -150,6 +150,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
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     NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
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 };
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+static const char *cpuid_xsave_feature_name[] = {
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+    "xsaveopt", "xsavec", "xgetbv1", NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+    NULL, NULL, NULL, NULL,
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+};
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+
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 typedef struct FeatureWordInfo {
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     const char **feat_names;
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     uint32_t cpuid_eax;   /* Input EAX for CPUID */
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@@ -193,6 +204,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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         .cpuid_reg = R_EBX,
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     },
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+    [FEAT_XSAVE] = {
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+        .feat_names = cpuid_xsave_feature_name,
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+        .cpuid_eax = 0xd,
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+        .cpuid_needs_ecx = true, .cpuid_ecx = 1,
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+        .cpuid_reg = R_EAX,
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+    },
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 };
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 typedef struct X86RegisterInfo32 {
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@@ -833,6 +850,8 @@ static x86_def_t builtin_x86_defs[] = {
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              CPUID_EXT2_SYSCALL,
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         .features[FEAT_8000_0001_ECX] =
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             CPUID_EXT3_LAHF_LM,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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         .xlevel = 0x8000000A,
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         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
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     },
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@@ -866,6 +885,8 @@ static x86_def_t builtin_x86_defs[] = {
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             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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             CPUID_7_0_EBX_RTM,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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         .xlevel = 0x8000000A,
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         .model_id = "Intel Core Processor (Haswell)",
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     },
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@@ -900,6 +921,8 @@ static x86_def_t builtin_x86_defs[] = {
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             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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             CPUID_7_0_EBX_SMAP,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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         .xlevel = 0x8000000A,
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         .model_id = "Intel Core Processor (Broadwell)",
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     },
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@@ -1017,6 +1040,7 @@ static x86_def_t builtin_x86_defs[] = {
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              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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              CPUID_EXT3_LAHF_LM,
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+        /* no xsaveopt! */
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         .xlevel = 0x8000001A,
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         .model_id = "AMD Opteron 62xx class CPU",
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     },
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@@ -1051,6 +1075,7 @@ static x86_def_t builtin_x86_defs[] = {
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              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
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              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
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              CPUID_EXT3_LAHF_LM,
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+        /* no xsaveopt! */
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         .xlevel = 0x8000001A,
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         .model_id = "AMD Opteron 63xx class CPU",
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     },
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@@ -2196,7 +2221,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
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             *ebx = *ecx;
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         } else if (count == 1) {
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-            *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
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+            *eax = env->features[FEAT_XSAVE];
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         } else if (count < ARRAY_SIZE(ext_save_areas)) {
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             const ExtSaveArea *esa = &ext_save_areas[count];
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             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
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@@ -2540,6 +2565,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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             );
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         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
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         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
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+        env->features[FEAT_XSAVE] = 0;
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     } else {
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         if ((cpu->check_cpuid || cpu->enforce_cpuid)
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             && kvm_check_features_against_host(cpu) && cpu->enforce_cpuid) {
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 61e9b86..da7e060 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -405,6 +405,7 @@ typedef enum FeatureWord {
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     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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     FEAT_SVM,           /* CPUID[8000_000A].EDX */
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+    FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
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     FEATURE_WORDS,
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 } FeatureWord;
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@@ -565,6 +566,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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+#define CPUID_XSAVE_XSAVEOPT   (1U << 0)
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+#define CPUID_XSAVE_XSAVEC     (1U << 1)
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+#define CPUID_XSAVE_XGETBV1    (1U << 2)
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+#define CPUID_XSAVE_XSAVES     (1U << 3)
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+
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 #define CPUID_VENDOR_SZ      12
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 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
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-- 
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1.8.3.1
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