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From 1163b93bcdbef8e11c276722014d39c3619dbd1b Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 22 Nov 2019 11:53:48 +0000
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Subject: [PATCH 15/16] target/i386: add VMX features to named CPU models (RHEL
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only)
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20191122115348.25000-16-pbonzini@redhat.com>
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Patchwork-id: 92614
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O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 15/15] target/i386: add VMX features to named CPU models (RHEL only)
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Bugzilla: 1689270
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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Upstream has switched to versioned CPU models in order to provide the
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noTSX and IBRS variants. In 2.12, VMX features have to be duplicated by
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hand.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 538 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 538 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 36c9252..3effcf3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -2212,6 +2212,46 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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+ MSR_VMX_BASIC_TRUE_CTLS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
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+ .features[FEAT_VMX_EXIT_CTLS] =
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+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
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+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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+ .features[FEAT_VMX_SECONDARY_CTLS] =
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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+ VMX_SECONDARY_EXEC_ENABLE_VPID,
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.xlevel = 0x80000008,
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.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
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},
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@@ -2307,6 +2347,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EDX_SPEC_CTRL,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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+ MSR_VMX_BASIC_TRUE_CTLS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
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+ .features[FEAT_VMX_EXIT_CTLS] =
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+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
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+ MSR_VMX_MISC_STORE_LMA,
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+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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+ .features[FEAT_VMX_SECONDARY_CTLS] =
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
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.xlevel = 0x80000008,
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.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
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},
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@@ -2412,6 +2493,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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+ MSR_VMX_BASIC_TRUE_CTLS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
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+ .features[FEAT_VMX_EXIT_CTLS] =
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+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
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+ MSR_VMX_MISC_STORE_LMA,
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+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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+ .features[FEAT_VMX_SECONDARY_CTLS] =
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
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},
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@@ -2526,6 +2648,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_XSAVE_XSAVEOPT,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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+ MSR_VMX_BASIC_TRUE_CTLS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
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+ .features[FEAT_VMX_EXIT_CTLS] =
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+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2562,6 +2728,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Haswell, no TSX)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2600,6 +2812,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2722,6 +2980,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Haswell, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2760,6 +3064,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
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|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
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|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
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|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
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|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Broadwell, no TSX)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2800,6 +3151,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2925,6 +3323,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Broadwell, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -3062,6 +3507,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XGETBV1,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
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016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
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016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
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016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
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016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
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016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
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016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
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016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
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016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
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016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
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016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
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016a62 |
.xlevel = 0x80000008,
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016a62 |
.model_id = "Intel Core Processor (Skylake, IBRS)",
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016a62 |
},
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016a62 |
@@ -3208,6 +3698,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
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016a62 |
CPUID_XSAVE_XGETBV1,
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016a62 |
.features[FEAT_6_EAX] =
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016a62 |
CPUID_6_EAX_ARAT,
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016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
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016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
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016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
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016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
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016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
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016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
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016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
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016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
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016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
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016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
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|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
|
|
|
016a62 |
},
|
|
|
016a62 |
--
|
|
|
016a62 |
1.8.3.1
|
|
|
016a62 |
|