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From d6acc0368578932ee6a2949054a6f640a5b6fa09 Mon Sep 17 00:00:00 2001
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From: Fam Zheng <famz@redhat.com>
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Date: Thu, 18 May 2017 09:21:26 +0200
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Subject: [PATCH 13/18] serial: update LSR on enabling/disabling FIFOs
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RH-Author: Fam Zheng <famz@redhat.com>
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Message-id: <20170518092131.16571-14-famz@redhat.com>
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Patchwork-id: 75306
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O-Subject: [RHEL-7.4 qemu-kvm PATCH v3 13/18] serial: update LSR on enabling/disabling FIFOs
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Bugzilla: 1451470
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
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When the transmit FIFO is emptied or enabled, the transmitter
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hold register is empty. When it is disabled, it is also emptied and
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in addition the previous contents of the transmitter hold register
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are discarded. In either case, the THRE bit in LSR must be set and
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THRI raised.
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When the receive FIFO is emptied or enabled, the data ready and break
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bits must be cleared in LSR. Likewise when the receive FIFO is disabled.
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Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 023c3a9707d0d9259a1e858cdf7804dd10973fca)
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Signed-off-by: Fam Zheng <famz@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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hw/char/serial.c
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Contextual conflict because upstream uses new timer API timer_del while
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downstream still uses qemu_del_timer.
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---
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hw/char/serial.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/hw/char/serial.c b/hw/char/serial.c
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index c2be4bd..e0d29a8 100644
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--- a/hw/char/serial.c
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+++ b/hw/char/serial.c
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@@ -351,12 +351,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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/* FIFO clear */
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if (val & UART_FCR_RFR) {
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+ s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
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qemu_del_timer(s->fifo_timeout_timer);
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s->timeout_ipending=0;
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fifo8_reset(&s->recv_fifo);
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}
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if (val & UART_FCR_XFR) {
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+ s->lsr |= UART_LSR_THRE;
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+ s->thr_ipending = 1;
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fifo8_reset(&s->xmit_fifo);
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}
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--
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1.8.3.1
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