9ae3a8
From d07bebfe0f9a1e1cf3f25449d9c20d4c21c6e2a0 Mon Sep 17 00:00:00 2001
9ae3a8
Message-Id: <d07bebfe0f9a1e1cf3f25449d9c20d4c21c6e2a0.1387298827.git.minovotn@redhat.com>
9ae3a8
In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
9ae3a8
References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
9ae3a8
From: "Michael S. Tsirkin" <mst@redhat.com>
9ae3a8
Date: Tue, 17 Dec 2013 15:17:37 +0100
9ae3a8
Subject: [PATCH 19/56] q35: make pci window address/size match guest cfg
9ae3a8
9ae3a8
RH-Author: Michael S. Tsirkin <mst@redhat.com>
9ae3a8
Message-id: <1387293161-4085-20-git-send-email-mst@redhat.com>
9ae3a8
Patchwork-id: 56325
9ae3a8
O-Subject: [PATCH qemu-kvm RHEL7.0 v2 19/57] q35: make pci window address/size match guest cfg
9ae3a8
Bugzilla: 1034876
9ae3a8
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
9ae3a8
RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
9ae3a8
RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
9ae3a8
9ae3a8
For Q35, MMCFG address and size are guest configurable.
9ae3a8
Update w32 property to make it behave accordingly.
9ae3a8
9ae3a8
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
9ae3a8
(cherry picked from commit 636228a887c4d5c0dc313bbf936de969b420a91a)
9ae3a8
9ae3a8
Conflicts:
9ae3a8
	hw/pci-host/q35.c
9ae3a8
---
9ae3a8
 hw/pci-host/q35.c | 10 ++++++++++
9ae3a8
 1 file changed, 10 insertions(+)
9ae3a8
9ae3a8
Signed-off-by: Michal Novotny <minovotn@redhat.com>
9ae3a8
---
9ae3a8
 hw/pci-host/q35.c | 10 ++++++++++
9ae3a8
 1 file changed, 10 insertions(+)
9ae3a8
9ae3a8
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
9ae3a8
index be12eee..70ad01f 100644
9ae3a8
--- a/hw/pci-host/q35.c
9ae3a8
+++ b/hw/pci-host/q35.c
9ae3a8
@@ -207,6 +207,16 @@ static void mch_update_pciexbar(MCHPCIState *mch)
9ae3a8
     }
9ae3a8
     addr = pciexbar & addr_mask;
9ae3a8
     pcie_host_mmcfg_update(&s->host, enable, addr, length);
9ae3a8
+    /* Leave enough space for the MCFG BAR */
9ae3a8
+    /*
9ae3a8
+     * TODO: this matches current bios behaviour, but it's not a power of two,
9ae3a8
+     * which means an MTRR can't cover it exactly.
9ae3a8
+     */
9ae3a8
+    if (enable) {
9ae3a8
+        mch->pci_info.w32.begin = addr + length;
9ae3a8
+    } else {
9ae3a8
+        mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
9ae3a8
+    }
9ae3a8
 }
9ae3a8
 
9ae3a8
 /* PAM */
9ae3a8
-- 
9ae3a8
1.7.11.7
9ae3a8