9ae3a8
From c538b7706e6f03a1eae8f11f9f89b9cbee73dbc9 Mon Sep 17 00:00:00 2001
9ae3a8
From: Laszlo Ersek <lersek@redhat.com>
9ae3a8
Date: Sat, 11 Jan 2014 18:00:08 +0100
9ae3a8
Subject: [PATCH 18/22] piix: fix 32bit pci hole
9ae3a8
9ae3a8
RH-Author: Laszlo Ersek <lersek@redhat.com>
9ae3a8
Message-id: <1389463208-6278-19-git-send-email-lersek@redhat.com>
9ae3a8
Patchwork-id: 56630
9ae3a8
O-Subject: [RHEL-7.0 qemu-kvm PATCH 18/18] piix: fix 32bit pci hole
9ae3a8
Bugzilla: 1032346
9ae3a8
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
9ae3a8
RH-Acked-by: Amos Kong <akong@redhat.com>
9ae3a8
RH-Acked-by: Andrew Jones <drjones@redhat.com>
9ae3a8
9ae3a8
From: Gerd Hoffmann <kraxel@redhat.com>
9ae3a8
9ae3a8
Make the 32bit pci hole start at end of ram, so all possible address
9ae3a8
space is covered.
9ae3a8
9ae3a8
We used to try and make addresses aligned so they are easier to cover
9ae3a8
with MTRRs, but since they are cosmetic on KVM, this is probably not
9ae3a8
worth worrying about.
9ae3a8
Of course the firmware can use less than that.  Leaving space unused is
9ae3a8
no problem, mapping pci bars outside the hole causes problems though.
9ae3a8
9ae3a8
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
9ae3a8
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
9ae3a8
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
9ae3a8
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
9ae3a8
(cherry picked from commit ddaaefb4dd427d6d2e41c1cfbe0cd8d8e8d6aad9)
9ae3a8
9ae3a8
Conflicts:
9ae3a8
	hw/i386/pc_piix.c
9ae3a8
	hw/pci-host/piix.c
9ae3a8
	include/hw/i386/pc.h
9ae3a8
9ae3a8
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
9ae3a8
---
9ae3a8
 hw/pci-host/piix.c | 10 +---------
9ae3a8
 1 file changed, 1 insertion(+), 9 deletions(-)
9ae3a8
9ae3a8
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
9ae3a8
---
9ae3a8
 hw/pci-host/piix.c |   10 +---------
9ae3a8
 1 files changed, 1 insertions(+), 9 deletions(-)
9ae3a8
9ae3a8
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
9ae3a8
index 9284c8d..5757b1d 100644
9ae3a8
--- a/hw/pci-host/piix.c
9ae3a8
+++ b/hw/pci-host/piix.c
9ae3a8
@@ -337,15 +337,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
9ae3a8
     f->ram_memory = ram_memory;
9ae3a8
 
9ae3a8
     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
9ae3a8
-    /* Set PCI window size the way seabios has always done it. */
9ae3a8
-    /* Power of 2 so bios can cover it with a single MTRR */
9ae3a8
-    if (ram_size <= 0x80000000) {
9ae3a8
-        i440fx->pci_info.w32.begin = 0x80000000;
9ae3a8
-    } else if (ram_size <= 0xc0000000) {
9ae3a8
-        i440fx->pci_info.w32.begin = 0xc0000000;
9ae3a8
-    } else {
9ae3a8
-        i440fx->pci_info.w32.begin = 0xe0000000;
9ae3a8
-    }
9ae3a8
+    i440fx->pci_info.w32.begin = pci_hole_start;
9ae3a8
 
9ae3a8
     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
9ae3a8
                              pci_hole_start, pci_hole_size);
9ae3a8
-- 
9ae3a8
1.7.1
9ae3a8