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From b70ff3a2191f959098f12965c4c7e5adb60be59e Mon Sep 17 00:00:00 2001
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Message-Id: <b70ff3a2191f959098f12965c4c7e5adb60be59e.1387298827.git.minovotn@redhat.com>
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In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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From: "Michael S. Tsirkin" <mst@redhat.com>
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Date: Tue, 17 Dec 2013 15:17:24 +0100
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Subject: [PATCH 14/56] pc: pass PCI hole ranges to Guests
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RH-Author: Michael S. Tsirkin <mst@redhat.com>
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Message-id: <1387293161-4085-15-git-send-email-mst@redhat.com>
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Patchwork-id: 56320
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O-Subject: [PATCH qemu-kvm RHEL7.0 v2 14/57] pc: pass PCI hole ranges to Guests
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Bugzilla: 1034876
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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Guest currently has to jump through lots of hoops to guess the PCI hole
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ranges. It's fragile, and makes us change BIOS each time we add a new
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chipset. Let's report the window in a ROM file, to make BIOS do exactly
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what QEMU intends.
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit f8c457b88d72a48989f190bc3d7b79f4f3b7d11c)
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Conflicts:
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hw/i386/pc_piix.c
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hw/i386/pc_q35.c
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include/hw/i386/pc.h | 1 +
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hw/i386/pc.c | 26 ++++++++++++++++++++++++++
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hw/i386/pc_piix.c | 16 +++++++++++++++-
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hw/i386/pc_q35.c | 12 ++++++++++
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4 files changed, 52 insertions(+), 3 deletions(-)
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Signed-off-by: Michal Novotny <minovotn@redhat.com>
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hw/i386/pc.c | 26 ++++++++++++++++++++++++++
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hw/i386/pc_piix.c | 16 +++++++++++++++-
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hw/i386/pc_q35.c | 12 ++++++++++
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include/hw/i386/pc.h | 1 +
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4 files changed, 52 insertions(+), 3 deletions(-)
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diff
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index 68a8e1b..238f6a0 100644
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@@ -985,6 +985,31 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
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}
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}
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+
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+typedef struct PcRomPciInfo {
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+ uint64_t w32_min;
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+ uint64_t w32_max;
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+ uint64_t w64_min;
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+ uint64_t w64_max;
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+} PcRomPciInfo;
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+
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+static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
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+{
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+ PcRomPciInfo *info;
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+ if (!guest_info->has_pci_info) {
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+ return;
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+ }
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+
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+ info = g_malloc(sizeof *info);
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+ info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin);
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+ info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end);
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+ info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin);
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+ info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end);
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+
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+ * Required so guest PCI enumeration does the right thing. */
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+ fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
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+}
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+
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typedef struct PcGuestInfoState {
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PcGuestInfo info;
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Notifier machine_done;
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@@ -996,6 +1021,7 @@ void pc_guest_info_machine_done(Notifier *notifier, void *data)
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PcGuestInfoState *guest_info_state = container_of(notifier,
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PcGuestInfoState,
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machine_done);
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+ pc_fw_cfg_guest_info(&guest_info_state->info);
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}
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PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
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diff
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index 3a77998..6d50a4e 100644
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@@ -59,6 +59,7 @@ static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static bool smbios_type1_defaults = true;
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+static bool has_pci_info = true;
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static void pc_init1(QEMUMachineInitArgs *args,
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@@ -122,6 +123,7 @@ static void pc_init1(QEMUMachineInitArgs *args,
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}
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guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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+ guest_info->has_pci_info = has_pci_info;
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@@ -248,8 +250,15 @@ static void pc_init_pci(QEMUMachineInitArgs *args)
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#if 0 /* Disabled for Red Hat Enterprise Linux */
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+static void pc_init_pci_1_5(QEMUMachineInitArgs *args)
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+{
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+ has_pci_info = false;
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+ pc_init_pci(args);
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+}
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+
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static void pc_init_pci_1_4(QEMUMachineInitArgs *args)
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{
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+ has_pci_info = false;
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x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
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x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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pc_init_pci(args);
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@@ -257,6 +266,7 @@ static void pc_init_pci_1_4(QEMUMachineInitArgs *args)
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static void pc_init_pci_1_3(QEMUMachineInitArgs *args)
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{
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+ has_pci_info = false;
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enable_compat_apic_id_mode();
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pc_init_pci(args);
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}
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@@ -264,6 +274,7 @@ static void pc_init_pci_1_3(QEMUMachineInitArgs *args)
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/* PC machine init function for pc-1.1 to pc-1.2 */
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static void pc_init_pci_1_2(QEMUMachineInitArgs *args)
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{
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+ has_pci_info = false;
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disable_kvm_pv_eoi();
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enable_compat_apic_id_mode();
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pc_init_pci(args);
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@@ -272,6 +283,7 @@ static void pc_init_pci_1_2(QEMUMachineInitArgs *args)
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/* PC machine init function for pc-0.14 to pc-1.0 */
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static void pc_init_pci_1_0(QEMUMachineInitArgs *args)
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{
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+ has_pci_info = false;
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disable_kvm_pv_eoi();
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enable_compat_apic_id_mode();
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pc_init_pci(args);
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@@ -280,6 +292,7 @@ static void pc_init_pci_1_0(QEMUMachineInitArgs *args)
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/* PC init function for pc-0.10 to pc-0.13, and reused by xenfv */
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static void pc_init_pci_no_kvmclock(QEMUMachineInitArgs *args)
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{
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+ has_pci_info = false;
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disable_kvm_pv_eoi();
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enable_compat_apic_id_mode();
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pc_init1(args, get_system_memory(), get_system_io(), 1, 0);
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@@ -290,6 +303,7 @@ static void pc_init_isa(QEMUMachineInitArgs *args)
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if (!args->cpu_model) {
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args->cpu_model = "486";
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}
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+ has_pci_info = false;
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disable_kvm_pv_eoi();
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enable_compat_apic_id_mode();
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pc_init1(args, get_system_memory(), get_system_io(), 0, 1);
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@@ -310,7 +324,7 @@ static QEMUMachine pc_i440fx_machine_v1_5 = {
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.name = "pc-i440fx-1.5",
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.alias = "pc",
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.desc = "Standard PC (i440FX + PIIX, 1996)",
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- .init = pc_init_pci,
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+ .init = pc_init_pci_1_5,
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.hot_add_cpu = pc_hot_add_cpu,
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.max_cpus = 255,
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.is_default = 1,
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diff
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index 9fab93c..7a58b61 100644
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@@ -49,6 +49,7 @@
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#define MAX_SATA_PORTS 6
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static bool smbios_type1_defaults = true;
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+static bool has_pci_info = true;
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static void pc_q35_init(QEMUMachineInitArgs *args)
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@@ -108,6 +109,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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}
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guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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+ guest_info->has_pci_info = has_pci_info;
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/* allocate ram and load rom/bios */
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if (!xen_enabled()) {
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@@ -213,18 +215,24 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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#if 0 /* Disabled for Red Hat Enterprise Linux */
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+static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
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+{
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+ has_pci_info = false;
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+ pc_q35_init(args);
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+}
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+
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static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
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{
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x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
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x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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- pc_q35_init(args);
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+ pc_q35_init_1_5(args);
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}
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static QEMUMachine pc_q35_machine_v1_5 = {
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.name = "pc-q35-1.5",
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.alias = "q35",
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.desc = "Standard PC (Q35 + ICH9, 2009)",
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- .init = pc_q35_init,
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+ .init = pc_q35_init_1_5,
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.hot_add_cpu = pc_hot_add_cpu,
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.max_cpus = 255,
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.compat_props = (GlobalProperty[]) {
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diff
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index 2518db6..2992464 100644
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+++ b/include/hw/i386/pc.h
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@@ -21,6 +21,7 @@ typedef struct PcPciInfo {
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struct PcGuestInfo {
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PcPciInfo pci_info;
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+ bool has_pci_info;
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FWCfgState *fw_cfg;
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};
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--
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1.7.11.7
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