Blame SOURCES/kvm-linux-headers-Update-for-NVLink2-passthrough-downstr.patch

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From a0d3bac749cccf262986923b1b4f4e565472cfd8 Mon Sep 17 00:00:00 2001
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From: David Gibson <dgibson@redhat.com>
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Date: Thu, 30 May 2019 04:37:24 +0100
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Subject: [PATCH 3/8] linux-headers: Update for NVLink2 passthrough [downstream
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 only]
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: David Gibson <dgibson@redhat.com>
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Message-id: <20190530043728.32575-3-dgibson@redhat.com>
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Patchwork-id: 88424
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O-Subject: [RHEL-8.1 qemu-kvm PATCH 2/6] linux-headers: Update for NVLink2 passthrough [downstream only]
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Bugzilla: 1710662
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RH-Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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From: David Gibson <david@gibson.dropbear.id.au>
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Update with the necessary pieces for vfio passthrough of NVLink2
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devices.  Not a full header update, just pieces, since that's the
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convention downwstream.
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1710662
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Signed-off-by: David Gibson <dgibson@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 linux-headers/linux/vfio.h | 42 ++++++++++++++++++++++++++++++++++++++++++
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 1 file changed, 42 insertions(+)
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diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
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index 25c7b7d..12b23e5 100644
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--- a/linux-headers/linux/vfio.h
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+++ b/linux-headers/linux/vfio.h
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@@ -304,6 +304,21 @@ struct vfio_region_info_cap_type {
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 #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG	(3)
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 /*
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+ * 10de vendor sub-type
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+ *
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+ * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space.
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+ */
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+#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM	(1)
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+
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+/*
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+ * 1014 vendor sub-type
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+ *
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+ * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU
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+ * to do TLB invalidation on a GPU.
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+ */
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+#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD	(1)
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+
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+/*
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  * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped
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  * which allows direct access to non-MSIX registers which happened to be within
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  * the same system page.
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@@ -313,6 +328,33 @@ struct vfio_region_info_cap_type {
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  */
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 #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE	3
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+/*
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+ * Capability with compressed real address (aka SSA - small system address)
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+ * where GPU RAM is mapped on a system bus. Used by a GPU for DMA routing
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+ * and by the userspace to associate a NVLink bridge with a GPU.
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+ */
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+#define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT	4
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+
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+struct vfio_region_info_cap_nvlink2_ssatgt {
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+	struct vfio_info_cap_header header;
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+	__u64 tgt;
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+};
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+
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+/*
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+ * Capability with an NVLink link speed. The value is read by
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+ * the NVlink2 bridge driver from the bridge's "ibm,nvlink-speed"
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+ * property in the device tree. The value is fixed in the hardware
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+ * and failing to provide the correct value results in the link
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+ * not working with no indication from the driver why.
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+ */
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+#define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD	5
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+
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+struct vfio_region_info_cap_nvlink2_lnkspd {
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+	struct vfio_info_cap_header header;
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+	__u32 link_speed;
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+	__u32 __pad;
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+};
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+
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 /**
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  * VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9,
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  *				    struct vfio_irq_info)
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-- 
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1.8.3.1
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