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From df15f85e59fe41c2663242feb7b5213047a9f456 Mon Sep 17 00:00:00 2001
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From: Peter Xu <peterx@redhat.com>
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Date: Thu, 8 Nov 2018 06:29:33 +0000
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Subject: [PATCH 05/35] intel-iommu: start to use error_report_once
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Peter Xu <peterx@redhat.com>
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Message-id: <20181108062938.21143-3-peterx@redhat.com>
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Patchwork-id: 82961
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O-Subject: [RHEL-8 qemu-kvm PATCH 2/7] intel-iommu: start to use error_report_once
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Bugzilla: 1625173
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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Bugzilla: 1625173
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Replace existing trace_vtd_err() with error_report_once() then stderr
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will capture something if any of the error happens, meanwhile we don't
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suffer from any DDOS.  Then remove the trace point.  Since at it,
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provide more information where proper (now we can pass parameters into
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the report function).
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Message-Id: <20180815095328.32414-3-peterx@redhat.com>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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[Two format strings fixed, whitespace tidied up]
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Signed-off-by: Markus Armbruster <armbru@redhat.com>
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(cherry picked from commit 1376211f77bdcd84dc4acb877690f7399d8cf58a)
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/i386/intel_iommu.c | 65 +++++++++++++++++++++++++++++----------------------
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 hw/i386/trace-events  |  1 -
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 2 files changed, 37 insertions(+), 29 deletions(-)
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diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
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index b5a09b7..ab11cc4 100644
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--- a/hw/i386/intel_iommu.c
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+++ b/hw/i386/intel_iommu.c
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@@ -311,14 +311,14 @@ static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
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 {
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     if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
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         pre_fsts & VTD_FSTS_IQE) {
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-        trace_vtd_err("There are previous interrupt conditions "
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-                      "to be serviced by software, fault event "
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-                      "is not generated.");
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+        error_report_once("There are previous interrupt conditions "
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+                          "to be serviced by software, fault event "
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+                          "is not generated");
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         return;
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     }
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     vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
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     if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
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-        trace_vtd_err("Interrupt Mask set, irq is not generated.");
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+        error_report_once("Interrupt Mask set, irq is not generated");
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     } else {
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         vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
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         vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
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@@ -426,20 +426,20 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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     trace_vtd_dmar_fault(source_id, fault, addr, is_write);
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     if (fsts_reg & VTD_FSTS_PFO) {
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-        trace_vtd_err("New fault is not recorded due to "
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-                      "Primary Fault Overflow.");
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+        error_report_once("New fault is not recorded due to "
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+                          "Primary Fault Overflow");
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         return;
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     }
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     if (vtd_try_collapse_fault(s, source_id)) {
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-        trace_vtd_err("New fault is not recorded due to "
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-                      "compression of faults.");
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+        error_report_once("New fault is not recorded due to "
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+                          "compression of faults");
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         return;
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     }
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     if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
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-        trace_vtd_err("Next Fault Recording Reg is used, "
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-                      "new fault is not recorded, set PFO field.");
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+        error_report_once("Next Fault Recording Reg is used, "
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+                          "new fault is not recorded, set PFO field");
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         vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
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         return;
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     }
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@@ -447,8 +447,8 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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     vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
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     if (fsts_reg & VTD_FSTS_PPF) {
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-        trace_vtd_err("There are pending faults already, "
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-                      "fault event is not generated.");
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+        error_report_once("There are pending faults already, "
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+                          "fault event is not generated");
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         vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
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         s->next_frcd_reg++;
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         if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
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@@ -1056,8 +1056,10 @@ static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as,
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              * we just skip the sync for this time.  After all we even
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              * don't have the root table pointer!
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              */
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-            trace_vtd_err("Detected invalid context entry when "
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-                          "trying to sync shadow page table");
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+            error_report_once("%s: invalid context entry for bus 0x%x"
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+                              " devfn 0x%x",
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+                              __func__, pci_bus_num(vtd_as->bus),
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+                              vtd_as->devfn);
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             return 0;
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         }
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     }
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@@ -1514,7 +1516,8 @@ static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
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         break;
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     default:
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-        trace_vtd_err("Context cache invalidate type error.");
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+        error_report_once("%s: invalid context: 0x%" PRIx64,
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+                          __func__, val);
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         caig = 0;
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     }
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     return caig;
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@@ -1634,7 +1637,8 @@ static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
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         am = VTD_IVA_AM(addr);
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         addr = VTD_IVA_ADDR(addr);
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         if (am > VTD_MAMV) {
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-            trace_vtd_err("IOTLB PSI flush: address mask overflow.");
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+            error_report_once("%s: address mask overflow: 0x%" PRIx64,
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+                              __func__, vtd_get_quad_raw(s, DMAR_IVA_REG));
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             iaig = 0;
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             break;
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         }
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@@ -1643,7 +1647,8 @@ static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
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         break;
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     default:
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-        trace_vtd_err("IOTLB flush: invalid granularity.");
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+        error_report_once("%s: invalid granularity: 0x%" PRIx64,
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+                          __func__, val);
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         iaig = 0;
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     }
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     return iaig;
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@@ -1793,8 +1798,8 @@ static void vtd_handle_ccmd_write(IntelIOMMUState *s)
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     /* Context-cache invalidation request */
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     if (val & VTD_CCMD_ICC) {
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         if (s->qi_enabled) {
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-            trace_vtd_err("Queued Invalidation enabled, "
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-                          "should not use register-based invalidation");
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+            error_report_once("Queued Invalidation enabled, "
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+                              "should not use register-based invalidation");
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             return;
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         }
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         ret = vtd_context_cache_invalidate(s, val);
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@@ -1814,8 +1819,8 @@ static void vtd_handle_iotlb_write(IntelIOMMUState *s)
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     /* IOTLB invalidation request */
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     if (val & VTD_TLB_IVT) {
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         if (s->qi_enabled) {
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-            trace_vtd_err("Queued Invalidation enabled, "
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-                          "should not use register-based invalidation.");
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+            error_report_once("Queued Invalidation enabled, "
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+                              "should not use register-based invalidation");
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             return;
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         }
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         ret = vtd_iotlb_flush(s, val);
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@@ -1833,7 +1838,7 @@ static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
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     dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
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     if (dma_memory_read(&address_space_memory, addr, inv_desc,
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         sizeof(*inv_desc))) {
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-        trace_vtd_err("Read INV DESC failed.");
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+        error_report_once("Read INV DESC failed");
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         inv_desc->lo = 0;
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         inv_desc->hi = 0;
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         return false;
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@@ -2188,7 +2193,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
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     trace_vtd_reg_read(addr, size);
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     if (addr + size > DMAR_REG_SIZE) {
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-        trace_vtd_err("Read MMIO over range.");
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+        error_report_once("%s: MMIO over range: addr=0x%" PRIx64
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+                          " size=0x%u", __func__, addr, size);
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         return (uint64_t)-1;
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     }
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@@ -2239,7 +2245,8 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
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     trace_vtd_reg_write(addr, size, val);
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     if (addr + size > DMAR_REG_SIZE) {
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-        trace_vtd_err("Write MMIO over range.");
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+        error_report_once("%s: MMIO over range: addr=0x%" PRIx64
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+                          " size=0x%u", __func__, addr, size);
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         return;
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     }
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@@ -2610,7 +2617,8 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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     addr = iommu->intr_root + index * sizeof(*entry);
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     if (dma_memory_read(&address_space_memory, addr, entry,
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                         sizeof(*entry))) {
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-        trace_vtd_err("Memory read failed for IRTE.");
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+        error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64,
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+                          __func__, index, addr);
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         return -VTD_FR_IR_ROOT_INVAL;
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     }
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@@ -2742,14 +2750,15 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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     }
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     if (origin->address & VTD_MSI_ADDR_HI_MASK) {
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-        trace_vtd_err("MSI address high 32 bits non-zero when "
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-                      "Interrupt Remapping enabled.");
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+        error_report_once("%s: MSI address high 32 bits non-zero detected: "
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+                          "address=0x%" PRIx64, __func__, origin->address);
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         return -VTD_FR_IR_REQ_RSVD;
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     }
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     addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
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     if (addr.addr.__head != 0xfee) {
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-        trace_vtd_err("MSI addr low 32 bit invalid.");
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+        error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32,
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+                          __func__, addr.data);
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         return -VTD_FR_IR_REQ_RSVD;
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     }
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diff --git a/hw/i386/trace-events b/hw/i386/trace-events
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index e14d06e..922431b 100644
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--- a/hw/i386/trace-events
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+++ b/hw/i386/trace-events
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@@ -69,7 +69,6 @@ vtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PR
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 vtd_fsts_ppf(bool set) "FSTS PPF bit set to %d"
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 vtd_fsts_clear_ip(void) ""
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 vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64
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-vtd_err(const char *str) "%s"
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 vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64
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 vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" level %d"
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 vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bool is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d"
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-- 
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1.8.3.1
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