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From 8c311241e277756db896fdab983c6250ffde5fc0 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Sat, 13 Oct 2018 03:32:30 +0100
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Subject: [PATCH 17/17] i386: define the 'ssbd' CPUID feature bit
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(CVE-2018-3639)
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20181013033230.14687-2-ehabkost@redhat.com>
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Patchwork-id: 82685
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O-Subject: [RHEL8/rhel qemu-kvm PATCH 1/1] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)
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Bugzilla: 1633928
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Daniel P. Berrange <berrange@redhat.com>
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From: Daniel P. Berrangé <berrange@redhat.com>
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New microcode introduces the "Speculative Store Bypass Disable"
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CPUID feature bit. This needs to be exposed to guest OS to allow
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them to protect against CVE-2018-3639.
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Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Message-Id: <20180521215424.13520-2-berrange@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit d19d1f965904a533998739698020ff4ee8a103da)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 1 +
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2 files changed, 2 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 0215b20..228935f 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1008,7 +1008,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, "spec-ctrl", NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, "ssbd",
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},
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.cpuid_eax = 7,
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.cpuid_needs_ecx = true, .cpuid_ecx = 0,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c47db96..4a3ef4b 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -685,6 +685,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
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+#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
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#define KVM_HINTS_DEDICATED (1U << 0)
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--
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1.8.3.1
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