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From d00453667cb972dc2fe1242081d3b39313a6a925 Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Thu, 21 May 2020 23:56:52 +0100
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Subject: [PATCH 09/12] hmat acpi: Build Memory Side Cache Information
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 Structure(s)
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RH-Author: plai@redhat.com
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Message-id: <20200521235655.27141-9-plai@redhat.com>
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Patchwork-id: 96741
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O-Subject: [RHEL8.2.1 AV qemu-kvm PATCH 08/11] hmat acpi: Build Memory Side Cache Information Structure(s)
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Bugzilla: 1600217
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Liu Jingqi <jingqi.liu@intel.com>
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This structure describes memory side cache information for memory
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proximity domains if the memory side cache is present and the
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physical device forms the memory side cache.
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The software could use this information to effectively place
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the data in memory to maximize the performance of the system
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memory that use the memory side cache.
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Acked-by: Markus Armbruster <armbru@redhat.com>
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Reviewed-by: Igor Mammedov <imammedo@redhat.com>
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Reviewed-by: Daniel Black <daniel@linux.ibm.com>
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Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
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Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
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Signed-off-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <20191213011929.2520-7-tao3.xu@intel.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit a9c2b841af002db6e21e1297c9026b63fc22c875)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/acpi/hmat.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
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 1 file changed, 68 insertions(+), 1 deletion(-)
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diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
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index 4635d45..7c24bb5 100644
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--- a/hw/acpi/hmat.c
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+++ b/hw/acpi/hmat.c
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@@ -143,14 +143,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
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     g_free(entry_list);
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 }
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+/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
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+static void build_hmat_cache(GArray *table_data, uint8_t total_levels,
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+                             NumaHmatCacheOptions *hmat_cache)
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+{
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+    /*
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+     * Cache Attributes: Bits [3:0] – Total Cache Levels
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+     * for this Memory Proximity Domain
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+     */
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+    uint32_t cache_attr = total_levels;
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+
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+    /* Bits [7:4] : Cache Level described in this structure */
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+    cache_attr |= (uint32_t) hmat_cache->level << 4;
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+
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+    /* Bits [11:8] - Cache Associativity */
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+    cache_attr |= (uint32_t) hmat_cache->associativity << 8;
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+
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+    /* Bits [15:12] - Write Policy */
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+    cache_attr |= (uint32_t) hmat_cache->policy << 12;
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+
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+    /* Bits [31:16] - Cache Line size in bytes */
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+    cache_attr |= (uint32_t) hmat_cache->line << 16;
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+
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+    /* Type */
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+    build_append_int_noprefix(table_data, 2, 2);
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+    /* Reserved */
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+    build_append_int_noprefix(table_data, 0, 2);
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+    /* Length */
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+    build_append_int_noprefix(table_data, 32, 4);
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+    /* Proximity Domain for the Memory */
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+    build_append_int_noprefix(table_data, hmat_cache->node_id, 4);
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+    /* Reserved */
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+    build_append_int_noprefix(table_data, 0, 4);
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+    /* Memory Side Cache Size */
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+    build_append_int_noprefix(table_data, hmat_cache->size, 8);
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+    /* Cache Attributes */
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+    build_append_int_noprefix(table_data, cache_attr, 4);
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+    /* Reserved */
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+    build_append_int_noprefix(table_data, 0, 2);
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+    /*
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+     * Number of SMBIOS handles (n)
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+     * Linux kernel uses Memory Side Cache Information Structure
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+     * without SMBIOS entries for now, so set Number of SMBIOS handles
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+     * as 0.
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+     */
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+    build_append_int_noprefix(table_data, 0, 2);
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+}
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+
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 /* Build HMAT sub table structures */
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 static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
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 {
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     uint16_t flags;
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     uint32_t num_initiator = 0;
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     uint32_t initiator_list[MAX_NODES];
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-    int i, hierarchy, type;
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+    int i, hierarchy, type, cache_level, total_levels;
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     HMAT_LB_Info *hmat_lb;
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+    NumaHmatCacheOptions *hmat_cache;
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     for (i = 0; i < numa_state->num_nodes; i++) {
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         flags = 0;
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@@ -184,6 +232,25 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
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             }
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         }
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     }
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+
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+    /*
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+     * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
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+     * Table 5-147
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+     */
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+    for (i = 0; i < numa_state->num_nodes; i++) {
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+        total_levels = 0;
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+        for (cache_level = 1; cache_level < HMAT_LB_LEVELS; cache_level++) {
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+            if (numa_state->hmat_cache[i][cache_level]) {
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+                total_levels++;
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+            }
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+        }
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+        for (cache_level = 0; cache_level <= total_levels; cache_level++) {
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+            hmat_cache = numa_state->hmat_cache[i][cache_level];
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+            if (hmat_cache) {
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+                build_hmat_cache(table_data, total_levels, hmat_cache);
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+            }
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+        }
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+    }
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 }
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 void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state)
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-- 
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1.8.3.1
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