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From 96c218d6936795b087ceb493413221d5058118bc Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= <marcandre.lureau@redhat.com>
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Date: Wed, 13 Dec 2017 13:38:36 +0100
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Subject: [PATCH 05/41] Implement fw_cfg DMA interface
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Marc-André Lureau <marcandre.lureau@redhat.com>
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Message-id: <20171213133912.26176-6-marcandre.lureau@redhat.com>
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Patchwork-id: 78358
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O-Subject: [RHEL-7.5 qemu-kvm PATCH v3 05/41] Implement fw_cfg DMA interface
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Bugzilla: 1411490
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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From: Marc Marí <markmb@redhat.com>
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Based on the specifications on docs/specs/fw_cfg.txt
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This interface is an addon. The old interface can still be used as usual.
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Based on Gerd Hoffman's initial implementation.
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Signed-off-by: Marc Marí <markmb@redhat.com>
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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(cherry picked from commit a4c0d1deb785611c96a455f65ec032976b00b36f)
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RHEL: major rewrite due to lack of seperation between the MMIO & IO
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      introduced in upstream commit
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      5712db6ae5101db645f71edc393368cd59bfd314 and following commits.
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Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 hw/nvram/fw_cfg.c         | 223 ++++++++++++++++++++++++++++++++++++++++++++--
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 include/hw/nvram/fw_cfg.h |  12 +++
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 tests/fw_cfg-test.c       |   3 +-
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 3 files changed, 230 insertions(+), 8 deletions(-)
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diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
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index 01d4566..85e950c 100644
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--- a/hw/nvram/fw_cfg.c
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+++ b/hw/nvram/fw_cfg.c
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@@ -23,6 +23,7 @@
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  */
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 #include "hw/hw.h"
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 #include "sysemu/sysemu.h"
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+#include "sysemu/dma.h"
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 #include "hw/isa/isa.h"
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 #include "hw/nvram/fw_cfg.h"
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 #include "hw/sysbus.h"
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@@ -30,12 +31,22 @@
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 #include "qemu/error-report.h"
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 #include "qemu/config-file.h"
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-#define FW_CFG_SIZE 2
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+#define FW_CFG_CTL_SIZE 2
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 #define FW_CFG_DATA_SIZE 1
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 #define TYPE_FW_CFG "fw_cfg"
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 #define FW_CFG_NAME "fw_cfg"
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 #define FW_CFG_PATH "/machine/" FW_CFG_NAME
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+/* FW_CFG_VERSION bits */
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+#define FW_CFG_VERSION      0x01
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+#define FW_CFG_VERSION_DMA  0x02
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+
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+/* FW_CFG_DMA_CONTROL bits */
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+#define FW_CFG_DMA_CTL_ERROR   0x01
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+#define FW_CFG_DMA_CTL_READ    0x02
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+#define FW_CFG_DMA_CTL_SKIP    0x04
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+#define FW_CFG_DMA_CTL_SELECT  0x08
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+
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 typedef struct FWCfgEntry {
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     uint32_t len;
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     uint8_t *data;
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@@ -46,12 +57,17 @@ typedef struct FWCfgEntry {
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 struct FWCfgState {
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     SysBusDevice busdev;
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     MemoryRegion ctl_iomem, data_iomem, comb_iomem;
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-    uint32_t ctl_iobase, data_iobase;
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+    uint32_t ctl_iobase, data_iobase, dma_iobase;
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     FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
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     FWCfgFiles *files;
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     uint16_t cur_entry;
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     uint32_t cur_offset;
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     Notifier machine_ready;
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+
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+    bool dma_enabled;
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+    dma_addr_t dma_addr;
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+    DMAContext *dma;
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+    MemoryRegion dma_iomem;
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 };
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 #define JPG_FILE 0
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@@ -257,6 +273,124 @@ static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
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     fw_cfg_write(opaque, (uint8_t)value);
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 }
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+static void fw_cfg_dma_transfer(FWCfgState *s)
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+{
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+    dma_addr_t len;
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+    FWCfgDmaAccess dma;
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+    int arch;
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+    FWCfgEntry *e;
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+    int read;
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+    dma_addr_t dma_addr;
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+
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+    /* Reset the address before the next access */
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+    dma_addr = s->dma_addr;
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+    s->dma_addr = 0;
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+
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+    if (dma_memory_read(s->dma, dma_addr, &dma, sizeof(dma))) {
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+        stl_be_dma(s->dma, dma_addr + offsetof(FWCfgDmaAccess, control),
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+                   FW_CFG_DMA_CTL_ERROR);
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+        return;
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+    }
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+
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+    dma.address = be64_to_cpu(dma.address);
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+    dma.length = be32_to_cpu(dma.length);
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+    dma.control = be32_to_cpu(dma.control);
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+
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+    if (dma.control & FW_CFG_DMA_CTL_SELECT) {
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+        fw_cfg_select(s, dma.control >> 16);
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+    }
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+
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+    arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
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+    e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
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+
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+    if (dma.control & FW_CFG_DMA_CTL_READ) {
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+        read = 1;
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+    } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
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+        read = 0;
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+    } else {
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+        dma.length = 0;
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+    }
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+
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+    dma.control = 0;
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+
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+    while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
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+        if (s->cur_entry == FW_CFG_INVALID || !e->data ||
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+                                s->cur_offset >= e->len) {
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+            len = dma.length;
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+
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+            /* If the access is not a read access, it will be a skip access,
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+             * tested before.
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+             */
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+            if (read) {
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+                if (dma_memory_set(s->dma, dma.address, 0, len)) {
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+                    dma.control |= FW_CFG_DMA_CTL_ERROR;
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+                }
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+            }
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+
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+        } else {
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+            if (dma.length <= (e->len - s->cur_offset)) {
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+                len = dma.length;
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+            } else {
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+                len = (e->len - s->cur_offset);
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+            }
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+
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+            if (e->read_callback) {
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+                e->read_callback(e->callback_opaque, s->cur_offset);
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+            }
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+
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+            /* If the access is not a read access, it will be a skip access,
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+             * tested before.
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+             */
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+            if (read) {
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+                if (dma_memory_write(s->dma, dma.address,
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+                                    &e->data[s->cur_offset], len)) {
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+                    dma.control |= FW_CFG_DMA_CTL_ERROR;
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+                }
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+            }
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+
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+            s->cur_offset += len;
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+        }
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+
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+        dma.address += len;
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+        dma.length  -= len;
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+
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+    }
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+
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+    stl_be_dma(s->dma, dma_addr + offsetof(FWCfgDmaAccess, control),
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+                dma.control);
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+
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+    trace_fw_cfg_read(s, 0);
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+}
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+
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+static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
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+                                 uint64_t value, unsigned size)
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+{
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+    FWCfgState *s = opaque;
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+
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+    if (size == 4) {
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+        value = be32_to_cpu(value);
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+        if (addr == 0) {
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+            /* FWCfgDmaAccess high address */
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+            s->dma_addr = value << 32;
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+        } else if (addr == 4) {
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+            /* FWCfgDmaAccess low address */
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+            s->dma_addr |= value;
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+            fw_cfg_dma_transfer(s);
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+        }
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+    } else if (size == 8 && addr == 0) {
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+        value = be64_to_cpu(value);
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+        s->dma_addr = value;
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+        fw_cfg_dma_transfer(s);
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+    }
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+}
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+
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+static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
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+                                 unsigned size, bool is_write)
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+{
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+    return is_write && ((size == 4 && (addr == 0 || addr == 4)) ||
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+                        (size == 8 && addr == 0));
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+}
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+
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 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
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                                  uint64_t value, unsigned size)
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 {
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@@ -317,6 +451,14 @@ static const MemoryRegionOps fw_cfg_comb_mem_ops = {
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     .valid.accepts = fw_cfg_comb_valid,
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 };
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+static const MemoryRegionOps fw_cfg_dma_mem_ops = {
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+    .write = fw_cfg_dma_mem_write,
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+    .endianness = DEVICE_NATIVE_ENDIAN,
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+    .valid.accepts = fw_cfg_dma_mem_valid,
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+    .valid.max_access_size = 8,
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+    .impl.max_access_size = 8,
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+};
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+
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 static void fw_cfg_reset(DeviceState *d)
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 {
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     FWCfgState *s = DO_UPCAST(FWCfgState, busdev.qdev, d);
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@@ -357,6 +499,21 @@ static bool is_version_1(void *opaque, int version_id)
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     return version_id == 1;
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 }
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+static bool fw_cfg_dma_enabled(void *opaque)
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+{
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+    FWCfgState *s = opaque;
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+
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+    return s->dma_enabled;
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+}
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+
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+static const VMStateDescription vmstate_fw_cfg_dma = {
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+    .name = "fw_cfg/dma",
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+    .fields = (VMStateField[]) {
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+        VMSTATE_UINT64(dma_addr, FWCfgState),
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+        VMSTATE_END_OF_LIST()
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+    },
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+};
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+
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 static const VMStateDescription vmstate_fw_cfg = {
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     .name = "fw_cfg",
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     .version_id = 2,
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@@ -367,6 +524,14 @@ static const VMStateDescription vmstate_fw_cfg = {
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         VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
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         VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
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         VMSTATE_END_OF_LIST()
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+    },
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+    .subsections = (const VMStateSubsection[]) {
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+        {
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+            .vmsd = &vmstate_fw_cfg_dma,
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+            .needed = fw_cfg_dma_enabled,
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+        }, {
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+            /* empty */
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+        }
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     }
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 };
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@@ -478,16 +643,24 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data)
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     fw_cfg_add_file(s, "bootorder", (uint8_t*)bootindex, len);
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 }
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-FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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-                        hwaddr ctl_addr, hwaddr data_addr)
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+static FWCfgState *
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+fw_cfg_init_dma(uint32_t ctl_port, uint32_t data_port,
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+                uint32_t dma_port,
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+                hwaddr ctl_addr, hwaddr data_addr, hwaddr dma_addr,
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+                AddressSpace *dma_as)
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 {
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     DeviceState *dev;
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     SysBusDevice *d;
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     FWCfgState *s;
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+    uint32_t version = FW_CFG_VERSION;
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+    bool dma_enabled = dma_port && dma_as;
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     dev = qdev_create(NULL, "fw_cfg");
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     qdev_prop_set_uint32(dev, "ctl_iobase", ctl_port);
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     qdev_prop_set_uint32(dev, "data_iobase", data_port);
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+    qdev_prop_set_uint32(dev, "dma_iobase", dma_port);
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+    qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
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+
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     d = SYS_BUS_DEVICE(dev);
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     s = DO_UPCAST(FWCfgState, busdev.qdev, dev);
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@@ -505,8 +678,19 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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     if (data_addr) {
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         sysbus_mmio_map(d, 1, data_addr);
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     }
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+    if (dma_enabled) {
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+        /* 64 bits for the address field */
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+        s->dma = &dma_context_memory;
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+        s->dma_addr = 0;
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+
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+        version |= FW_CFG_VERSION_DMA;
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+        if (dma_addr) {
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+            sysbus_mmio_map(d, 2, dma_addr);
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+        }
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+    }
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+
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     fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
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-    fw_cfg_add_i32(s, FW_CFG_ID, 1);
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+    fw_cfg_add_i32(s, FW_CFG_ID, version);
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     fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
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     fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
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     fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
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@@ -520,19 +704,37 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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     return s;
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 }
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+FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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+                        hwaddr ctl_addr, hwaddr data_addr)
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+{
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+    return fw_cfg_init_dma(ctl_port, data_addr, 0, ctl_addr, data_addr, 0, NULL);
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+}
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+
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+FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
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+                               AddressSpace *dma_as)
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+{
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+    return fw_cfg_init_dma(iobase, iobase + 1, dma_iobase, 0, 0, 0, dma_as);
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+}
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+
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 static int fw_cfg_init1(SysBusDevice *dev)
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 {
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     FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
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     memory_region_init_io(&s->ctl_iomem, &fw_cfg_ctl_mem_ops, s,
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-                          "fwcfg.ctl", FW_CFG_SIZE);
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+                          "fwcfg.ctl", FW_CFG_CTL_SIZE);
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     sysbus_init_mmio(dev, &s->ctl_iomem);
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     memory_region_init_io(&s->data_iomem, &fw_cfg_data_mem_ops, s,
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                           "fwcfg.data", FW_CFG_DATA_SIZE);
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     sysbus_init_mmio(dev, &s->data_iomem);
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     /* In case ctl and data overlap: */
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     memory_region_init_io(&s->comb_iomem, &fw_cfg_comb_mem_ops, s,
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-                          "fwcfg", FW_CFG_SIZE);
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+                          "fwcfg", FW_CFG_CTL_SIZE);
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+
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+    if (s->dma_enabled) {
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+        memory_region_init_io(&s->dma_iomem, &fw_cfg_dma_mem_ops, s,
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+                              "fwcfg.dma", sizeof(dma_addr_t));
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+        sysbus_init_mmio(dev, &s->dma_iomem);
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+    }
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     if (s->ctl_iobase + 1 == s->data_iobase) {
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         sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
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@@ -544,12 +746,19 @@ static int fw_cfg_init1(SysBusDevice *dev)
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             sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
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         }
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     }
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+
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+    if (s->dma_iobase) {
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+        sysbus_add_io(dev, s->dma_iobase, &s->dma_iomem);
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+    }
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+
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     return 0;
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 }
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 static Property fw_cfg_properties[] = {
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     DEFINE_PROP_HEX32("ctl_iobase", FWCfgState, ctl_iobase, -1),
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     DEFINE_PROP_HEX32("data_iobase", FWCfgState, data_iobase, -1),
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+    DEFINE_PROP_HEX32("dma_iobase", FWCfgState, dma_iobase, -1),
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+    DEFINE_PROP_BOOL("dma_enabled", FWCfgState, dma_enabled, false),
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     DEFINE_PROP_END_OF_LIST(),
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 };
5d360b
 
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diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
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index aa5f351..b193e38 100644
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--- a/include/hw/nvram/fw_cfg.h
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+++ b/include/hw/nvram/fw_cfg.h
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@@ -7,6 +7,7 @@
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 #include "exec/hwaddr.h"
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 #include "qemu/typedefs.h"
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+#include "qemu/compiler.h"
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 #endif
5d360b
 
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 #define FW_CFG_SIGNATURE        0x00
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@@ -61,6 +62,15 @@ typedef struct FWCfgFiles {
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     FWCfgFile f[];
5d360b
 } FWCfgFiles;
5d360b
 
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+/* Control as first field allows for different structures selected by this
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+ * field, which might be useful in the future
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+ */
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+typedef struct FWCfgDmaAccess {
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+    uint32_t control;
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+    uint32_t length;
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+    uint64_t address;
5d360b
+} QEMU_PACKED FWCfgDmaAccess;
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+
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 typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
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 typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset);
5d360b
 
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@@ -76,6 +86,8 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
5d360b
                               void *data, size_t len);
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 FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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                         hwaddr crl_addr, hwaddr data_addr);
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+FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
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+                               AddressSpace *dma_as);
5d360b
 
5d360b
 FWCfgState *fw_cfg_find(void);
5d360b
 
5d360b
diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
5d360b
index 3428dca..24b8a28 100644
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--- a/tests/fw_cfg-test.c
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+++ b/tests/fw_cfg-test.c
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@@ -38,7 +38,8 @@ static void test_fw_cfg_signature(void)
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 static void test_fw_cfg_id(void)
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 {
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-    g_assert_cmpint(qfw_cfg_get_u32(fw_cfg, FW_CFG_ID), ==, 1);
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+    uint32_t id = qfw_cfg_get_u32(fw_cfg, FW_CFG_ID);
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+    g_assert((id == 1) || (id == 3));
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 }
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 static void test_fw_cfg_uuid(void)
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-- 
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1.8.3.1
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