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From 136eae41007e2e5b0d693cc656f3ec36cbabf16f Mon Sep 17 00:00:00 2001
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From: Miroslav Rezanina <mrezanin@redhat.com>
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Date: Fri, 19 Oct 2018 13:27:13 +0200
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Subject: Add ppc64 machine types
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Adding changes to add RHEL machine types for ppc64 architecture.
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Rebase changes (4.0.0):
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- remove instance options and use upstream solution
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- Use upstream compat handling
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- Replace SPAPR_PCI_2_7_MMIO_WIN_SIZE with value (changed upstream)
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- re-add handling of instance_options (removed upstream)
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- Use p8 as default for rhel machine types (p9 default upstream)
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- sPAPRMachineClass renamed to SpaprMachineClass (upstream)
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Rebase changes (4.1.0):
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- Update format for compat structures
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Merged patches (4.0.0):
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- 467d59a redhat: define pseries-rhel8.0.0 machine type
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Merged patches (4.1.0):
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- f21757edc target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type
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- 2511c63 redhat: sync pseries-rhel7.6.0 with rhel-av-8.0.1
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- 89f01da redhat: define pseries-rhel8.1.0 machine type
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Merged patches (4.2.0):
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- bcba728 redhat: update pseries-rhel8.1.0 machine type
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- redhat: update pseries-rhel-7.6.0 machine type (patch 93039)
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- redhat: define pseries-rhel8.2.0 machine type (patch 93041)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/ppc/spapr.c          | 278 ++++++++++++++++++++++++++++++++++++++++
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 hw/ppc/spapr_cpu_core.c |  13 ++
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 include/hw/ppc/spapr.h  |   1 +
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 target/ppc/compat.c     |  13 +-
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 target/ppc/cpu.h        |   1 +
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 5 files changed, 305 insertions(+), 1 deletion(-)
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diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
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index e076f6023c..8749c72066 100644
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--- a/hw/ppc/spapr.c
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+++ b/hw/ppc/spapr.c
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@@ -4447,6 +4447,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
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     smc->linux_pci_probe = true;
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     smc->smp_threads_vsmt = true;
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     smc->nr_xirqs = SPAPR_NR_XIRQS;
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+    smc->has_power9_support = true;
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 }
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 static const TypeInfo spapr_machine_info = {
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@@ -4491,6 +4492,7 @@ static const TypeInfo spapr_machine_info = {
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     }                                                                \
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     type_init(spapr_machine_register_##suffix)
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+#if 0 /* Disabled for Red Hat Enterprise Linux */
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 /*
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  * pseries-4.2
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  */
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@@ -4520,6 +4522,7 @@ static void spapr_machine_4_1_class_options(MachineClass *mc)
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 }
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 DEFINE_SPAPR_MACHINE(4_1, "4.1", false);
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+#endif
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 /*
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  * pseries-4.0
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@@ -4536,6 +4539,7 @@ static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
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     *nv2atsd = 0;
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 }
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+#if 0 /* Disabled for Red Hat Enterprise Linux */
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 static void spapr_machine_4_0_class_options(MachineClass *mc)
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 {
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     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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@@ -4695,6 +4699,7 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
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 /*
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  * pseries-2.7
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  */
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+#endif
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 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
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                               uint64_t *buid, hwaddr *pio,
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@@ -4749,6 +4754,7 @@ static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
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     *nv2atsd = 0;
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 }
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+#if 0 /* Disabled for Red Hat Enterprise Linux */
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 static void spapr_machine_2_7_class_options(MachineClass *mc)
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 {
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     SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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@@ -4863,6 +4869,278 @@ static void spapr_machine_2_1_class_options(MachineClass *mc)
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     compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
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 }
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 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
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+#endif
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+
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+/*
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+ * pseries-rhel8.2.0
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+ */
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+
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+static void spapr_machine_rhel820_class_options(MachineClass *mc)
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+{
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+    /* Defaults for the latest behaviour inherited from the base class */
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel820, "rhel8.2.0", true);
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+
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+/*
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+ * pseries-rhel8.1.0
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+ * like pseries-4.1
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+ */
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+
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+static void spapr_machine_rhel810_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+    static GlobalProperty compat[] = {
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+        /* Only allow 4kiB and 64kiB IOMMU pagesizes */
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+        { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
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+    };
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+
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+    spapr_machine_rhel820_class_options(mc);
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+
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+    /* from pseries-4.1 */
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+    smc->linux_pci_probe = false;
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+    smc->smp_threads_vsmt = false;
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+    compat_props_add(mc->compat_props, hw_compat_rhel_8_1,
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+                     hw_compat_rhel_8_1_len);
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+    compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
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+
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel810, "rhel8.1.0", false);
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+
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+/*
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+ * pseries-rhel8.0.0
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+ * like pseries-3.1 and pseries-4.0
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+ * except SPAPR_CAP_CFPC, SPAPR_CAP_SBBC and SPAPR_CAP_IBS
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+ * that have been backported to pseries-rhel8.0.0
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+ */
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+
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+static void spapr_machine_rhel800_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel810_class_options(mc);
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+    compat_props_add(mc->compat_props, hw_compat_rhel_8_0,
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+                     hw_compat_rhel_8_0_len);
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+
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+    /* pseries-4.0 */
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+    smc->phb_placement = phb_placement_4_0;
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+    smc->irq = &spapr_irq_xics;
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+    smc->pre_4_1_migration = true;
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+
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+    /* pseries-3.1 */
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+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
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+    smc->update_dt_enabled = false;
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+    smc->dr_phb_enabled = false;
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+    smc->broken_host_serial_model = true;
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+    smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel800, "rhel8.0.0", false);
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+
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+/*
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+ * pseries-rhel7.6.0
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+ * like spapr_compat_2_12 and spapr_compat_3_0
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+ * spapr_compat_0 is empty
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+ */
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+GlobalProperty spapr_compat_rhel7_6[] = {
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+    { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
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+    { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
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+};
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+const size_t spapr_compat_rhel7_6_len = G_N_ELEMENTS(spapr_compat_rhel7_6);
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+
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+
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+static void spapr_machine_rhel760_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel800_class_options(mc);
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+    compat_props_add(mc->compat_props, hw_compat_rhel_7_6, hw_compat_rhel_7_6_len);
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+    compat_props_add(mc->compat_props, spapr_compat_rhel7_6, spapr_compat_rhel7_6_len);
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+
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+    /* from spapr_machine_3_0_class_options() */
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+    smc->legacy_irq_allocation = true;
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+    smc->nr_xirqs = 0x400;
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+    smc->irq = &spapr_irq_xics_legacy;
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+
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+    /* from spapr_machine_2_12_class_options() */
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+    /* We depend on kvm_enabled() to choose a default value for the
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+     * hpt-max-page-size capability. Of course we can't do it here
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+     * because this is too early and the HW accelerator isn't initialzed
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+     * yet. Postpone this to machine init (see default_caps_with_cpu()).
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+     */
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+    smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
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+
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+    /* SPAPR_CAP_WORKAROUND enabled in pseries-rhel800 by
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+     * f21757edc554
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+     * "Enable mitigations by default for pseries-4.0 machine type")
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+     */
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+    smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
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+    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
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+    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel760, "rhel7.6.0", false);
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+
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+/*
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+ * pseries-rhel7.6.0-sxxm
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+ *
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+ * pseries-rhel7.6.0 with speculative execution exploit mitigations enabled by default
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+ */
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+
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+static void spapr_machine_rhel760sxxm_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel760_class_options(mc);
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+    smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel760sxxm, "rhel7.6.0-sxxm", false);
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+
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+static void spapr_machine_rhel750_class_options(MachineClass *mc)
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+{
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+    spapr_machine_rhel760_class_options(mc);
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+    compat_props_add(mc->compat_props, hw_compat_rhel_7_5, hw_compat_rhel_7_5_len);
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+
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel750, "rhel7.5.0", false);
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+
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+/*
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+ * pseries-rhel7.5.0-sxxm
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+ *
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+ * pseries-rhel7.5.0 with speculative execution exploit mitigations enabled by default
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+ */
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+
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+static void spapr_machine_rhel750sxxm_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel750_class_options(mc);
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+    smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel750sxxm, "rhel7.5.0-sxxm", false);
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+
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+/*
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+ * pseries-rhel7.4.0
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+ * like spapr_compat_2_9
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+ */
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+GlobalProperty spapr_compat_rhel7_4[] = {
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+    { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
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+};
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+const size_t spapr_compat_rhel7_4_len = G_N_ELEMENTS(spapr_compat_rhel7_4);
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+
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+static void spapr_machine_rhel740_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel750_class_options(mc);
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+    compat_props_add(mc->compat_props, hw_compat_rhel_7_4, hw_compat_rhel_7_4_len);
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+    compat_props_add(mc->compat_props, spapr_compat_rhel7_4, spapr_compat_rhel7_4_len);
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+    mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
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+    smc->has_power9_support = false;
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+    smc->pre_2_10_has_unused_icps = true;
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+    smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
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+    smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel740, "rhel7.4.0", false);
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+
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+/*
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+ * pseries-rhel7.4.0-sxxm
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+ *
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+ * pseries-rhel7.4.0 with speculative execution exploit mitigations enabled by default
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+ */
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+
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+static void spapr_machine_rhel740sxxm_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel740_class_options(mc);
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+    smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel740sxxm, "rhel7.4.0-sxxm", false);
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+
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+/*
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+ * pseries-rhel7.3.0
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+ * like spapr_compat_2_6/_2_7/_2_8 but "ddw" has been backported to RHEL7_3
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+ */
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+GlobalProperty spapr_compat_rhel7_3[] = {
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+    { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000" },
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+    { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0" },
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+    { TYPE_POWERPC_CPU, "pre-2.8-migration", "on" },
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+    { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on" },
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+    { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
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+};
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+const size_t spapr_compat_rhel7_3_len = G_N_ELEMENTS(spapr_compat_rhel7_3);
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+
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+static void spapr_machine_rhel730_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel740_class_options(mc);
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+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
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+    mc->default_machine_opts = "modern-hotplug-events=off";
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+    compat_props_add(mc->compat_props, hw_compat_rhel_7_3, hw_compat_rhel_7_3_len);
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+    compat_props_add(mc->compat_props, spapr_compat_rhel7_3, spapr_compat_rhel7_3_len);
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+
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+    smc->phb_placement = phb_placement_2_7;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel730, "rhel7.3.0", false);
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+
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+/*
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+ * pseries-rhel7.3.0-sxxm
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+ *
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+ * pseries-rhel7.3.0 with speculative execution exploit mitigations enabled by default
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+ */
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+
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+static void spapr_machine_rhel730sxxm_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel730_class_options(mc);
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+    smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
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+    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
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+}
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+
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+DEFINE_SPAPR_MACHINE(rhel730sxxm, "rhel7.3.0-sxxm", false);
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+
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+/*
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+ * pseries-rhel7.2.0
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+ */
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+/* Should be like spapr_compat_2_5 + 2_4 + 2_3, but "dynamic-reconfiguration"
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+ * has been backported to RHEL7_2 so we don't need it here.
902636
+ */
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+
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+GlobalProperty spapr_compat_rhel7_2[] = {
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+    { "spapr-vlan", "use-rx-buffer-pools", "off" },
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+    { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
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+};
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+const size_t spapr_compat_rhel7_2_len = G_N_ELEMENTS(spapr_compat_rhel7_2);
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+
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+static void spapr_machine_rhel720_class_options(MachineClass *mc)
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+{
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+    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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+
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+    spapr_machine_rhel730_class_options(mc);
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+    smc->use_ohci_by_default = true;
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+    mc->has_hotpluggable_cpus = NULL;
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+    compat_props_add(mc->compat_props, hw_compat_rhel_7_2, hw_compat_rhel_7_2_len);
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+    compat_props_add(mc->compat_props, spapr_compat_rhel7_2, spapr_compat_rhel7_2_len);
902636
+}
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+
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+DEFINE_SPAPR_MACHINE(rhel720, "rhel7.2.0", false);
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 static void spapr_machine_register_types(void)
902636
 {
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diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
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index 301cd7b4e4..ba5a8fb82b 100644
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--- a/hw/ppc/spapr_cpu_core.c
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+++ b/hw/ppc/spapr_cpu_core.c
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@@ -24,6 +24,7 @@
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 #include "sysemu/reset.h"
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 #include "sysemu/hw_accel.h"
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 #include "qemu/error-report.h"
902636
+#include "cpu-models.h"
902636
 
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 static void spapr_reset_vcpu(PowerPCCPU *cpu)
902636
 {
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@@ -242,6 +243,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
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     CPUPPCState *env = &cpu->env;
902636
     CPUState *cs = CPU(cpu);
902636
     Error *local_err = NULL;
902636
+    SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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902636
     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
902636
     if (local_err) {
902636
@@ -254,6 +256,17 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
902636
     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
902636
     kvmppc_set_papr(cpu);
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902636
+    if (!smc->has_power9_support &&
902636
+        (((spapr->max_compat_pvr &&
902636
+           ppc_compat_cmp(spapr->max_compat_pvr,
902636
+                          CPU_POWERPC_LOGICAL_3_00) >= 0)) ||
902636
+          (!spapr->max_compat_pvr &&
902636
+           ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 0)))) {
902636
+        error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND,
902636
+                  "POWER9 CPU is not supported by this machine class");
902636
+        return;
902636
+    }
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+
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     if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) {
902636
         goto error_intc_create;
902636
     }
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diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
902636
index d5ab5ea7b2..aa89cc4a95 100644
902636
--- a/include/hw/ppc/spapr.h
902636
+++ b/include/hw/ppc/spapr.h
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@@ -125,6 +125,7 @@ struct SpaprMachineClass {
902636
     bool linux_pci_probe;
902636
     bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
902636
 
902636
+    bool has_power9_support;
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     void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
902636
                           uint64_t *buid, hwaddr *pio, 
902636
                           hwaddr *mmio32, hwaddr *mmio64,
902636
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
902636
index 7de4bf3122..3e2e35342d 100644
902636
--- a/target/ppc/compat.c
902636
+++ b/target/ppc/compat.c
902636
@@ -105,8 +105,19 @@ static const CompatInfo *compat_by_pvr(uint32_t pvr)
902636
     return NULL;
902636
 }
902636
 
902636
+long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2)
902636
+{
902636
+    const CompatInfo *compat1 = compat_by_pvr(pvr1);
902636
+    const CompatInfo *compat2 = compat_by_pvr(pvr2);
902636
+
902636
+    g_assert(compat1);
902636
+    g_assert(compat2);
902636
+
902636
+    return compat1 - compat2;
902636
+}
902636
+
902636
 static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t compat_pvr,
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-                       uint32_t min_compat_pvr, uint32_t max_compat_pvr)
902636
+                      uint32_t min_compat_pvr, uint32_t max_compat_pvr)
902636
 {
902636
     const CompatInfo *compat = compat_by_pvr(compat_pvr);
902636
     const CompatInfo *min = compat_by_pvr(min_compat_pvr);
902636
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
902636
index e3e82327b7..5c53801cfd 100644
902636
--- a/target/ppc/cpu.h
902636
+++ b/target/ppc/cpu.h
902636
@@ -1367,6 +1367,7 @@ static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
902636
 
902636
 /* Compatibility modes */
902636
 #if defined(TARGET_PPC64)
902636
+long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2);
902636
 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
902636
                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
902636
 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
902636
-- 
902636
2.21.0
902636