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From f0fac2e6c70510f7a5c5c572831b1a851a29fc07 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 13 Dec 2017 15:47:36 -0200
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Subject: [PATCH 1/3] target-i386: add support for SPEC_CTRL MSR
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20171213174738.20852-2-ehabkost@redhat.com>
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Patchwork-id: n/a
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O-Subject: [CONFIDENTIAL][RHEL-7.5 qemu-kvm-rhev PATCH v2 1/3] target-i386: cpu:
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add new CPUID bits for indirect branch predictor restrictions
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Bugzilla: CVE-2017-5715
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target/i386/cpu.h | 3 +++
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target/i386/kvm.c | 14 ++++++++++++++
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target/i386/machine.c | 20 ++++++++++++++++++++
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3 files changed, 37 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index fd73888..4dfb859 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -335,6 +335,7 @@
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#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_TSC_ADJUST 0x0000003b
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+#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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@@ -1082,6 +1083,8 @@ typedef struct CPUX86State {
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uint32_t pkru;
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+ uint64_t spec_ctrl;
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+
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/* End of state preserved by INIT (dummy marker). */
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struct {} end_init_save;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index ee4e91f..3f59629 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -91,6 +91,7 @@ static bool has_msr_hv_synic;
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static bool has_msr_hv_stimer;
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static bool has_msr_hv_frequencies;
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static bool has_msr_xss;
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+static bool has_msr_spec_ctrl;
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static bool has_msr_architectural_pmu;
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static uint32_t num_architectural_pmu_counters;
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@@ -1145,6 +1146,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case HV_X64_MSR_TSC_FREQUENCY:
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has_msr_hv_frequencies = true;
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ has_msr_spec_ctrl = true;
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+ break;
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}
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}
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}
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@@ -1627,6 +1631,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_xss) {
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kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
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}
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+ if (has_msr_spec_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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+ }
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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@@ -1635,6 +1642,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
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}
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#endif
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+
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/*
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* The following MSRs have side effects on the guest or are too heavy
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* for normal writeback. Limit them to reset or full state updates.
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@@ -2000,6 +2008,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_xss) {
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kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
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}
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+ if (has_msr_spec_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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+ }
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if (!env->tsc_valid) {
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@@ -2349,6 +2360,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
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}
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ env->spec_ctrl = msrs[i].data;
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+ break;
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}
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}
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index 6156626..0212270 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -838,6 +838,25 @@ static const VMStateDescription vmstate_xsave ={
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}
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};
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+static bool spec_ctrl_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return env->spec_ctrl != 0;
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+}
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+
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+static const VMStateDescription vmstate_spec_ctrl = {
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+ .name = "cpu/spec_ctrl",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = spec_ctrl_needed,
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+ .fields = (VMStateField[]){
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+ VMSTATE_UINT64(env.spec_ctrl, X86CPU),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@@ -956,6 +975,7 @@ VMStateDescription vmstate_x86_cpu = {
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#ifdef TARGET_X86_64
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&vmstate_pkru,
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#endif
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+ &vmstate_spec_ctrl,
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&vmstate_mcg_ext_ctl,
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&vmstate_xsave,
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NULL
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--
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1.8.3.1
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