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From 423e8d79df3ef4548d74854a8feeee84cd5e159c Mon Sep 17 00:00:00 2001
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From: David Gibson <dgibson@redhat.com>
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Date: Fri, 19 Jan 2018 02:34:37 +0100
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Subject: [PATCH 09/21] spapr: Treat Hardware Transactional Memory (HTM) as an
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optional capability
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RH-Author: David Gibson <dgibson@redhat.com>
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Message-id: <20180119023442.28577-3-dgibson@redhat.com>
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Patchwork-id: 78670
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O-Subject: [RHEL-7.5 qemu-kvm-rhev PATCH 2/7] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability
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Bugzilla: 1523414
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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From: David Gibson <david@gibson.dropbear.id.au>
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This adds an spapr capability bit for Hardware Transactional Memory. It is
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enabled by default for pseries-2.11 and earlier machine types. with POWER8
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or later CPUs (as it must be, since earlier qemu versions would implicitly
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allow it). However it is disabled by default for the latest pseries-2.12
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machine type.
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This means that with the latest machine type, HTM will not be available,
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regardless of CPU, unless it is explicitly enabled on the command line.
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That change is made on the basis that:
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* This way running with -M pseries,accel=tcg will start with whatever cpu
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and will provide the same guest visible model as with accel=kvm.
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- More specifically, this means existing make check tests don't have
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to be modified to use cap-htm=off in order to run with TCG
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* We hope to add a new "HTM without suspend" feature in the not too
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distant future which could work on both POWER8 and POWER9 cpus, and
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could be enabled by default.
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* Best guesses suggest that future POWER cpus may well only support the
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HTM-without-suspend model, not the (frankly, horribly overcomplicated)
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POWER8 style HTM with suspend.
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* Anecdotal evidence suggests problems with HTM being enabled when it
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wasn't wanted are more common than being missing when it was.
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Reviewed-by: Greg Kurz <groug@kaod.org>
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(cherry picked from commit ee76a09fc72cfbfab2bb5529320ef7e460adffd8)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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hw/ppc/spapr.c
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Conflicts due to replacement of upstream machine types with downstream
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ones. Omitted original logic since it affects the 2.11 machine type
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which isn't in downstream (even in comments). Replaced with logic to
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enable HTM capability only for pseries-rhel7.4.0 and earlier machine
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types.
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1523414
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Signed-off-by: David Gibson <dgibson@redhat.com>
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---
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hw/ppc/spapr.c | 13 ++++++++-----
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hw/ppc/spapr_caps.c | 29 ++++++++++++++++++++++++++++-
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include/hw/ppc/spapr.h | 3 +++
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3 files changed, 39 insertions(+), 6 deletions(-)
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diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
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index 7a4191d..2068a1f 100644
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--- a/hw/ppc/spapr.c
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+++ b/hw/ppc/spapr.c
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@@ -253,7 +253,9 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
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}
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/* Populate the "ibm,pa-features" property */
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-static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
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+static void spapr_populate_pa_features(sPAPRMachineState *spapr,
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+ PowerPCCPU *cpu,
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+ void *fdt, int offset,
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bool legacy_guest)
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{
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CPUPPCState *env = &cpu->env;
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@@ -318,7 +320,7 @@ static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
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*/
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pa_features[3] |= 0x20;
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}
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- if (kvmppc_has_cap_htm() && pa_size > 24) {
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+ if (spapr_has_cap(spapr, SPAPR_CAP_HTM) && pa_size > 24) {
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pa_features[24] |= 0x80; /* Transactional memory support */
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}
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if (legacy_guest && pa_size > 40) {
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@@ -385,8 +387,8 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
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return ret;
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}
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- spapr_populate_pa_features(cpu, fdt, offset,
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- spapr->cas_legacy_guest_workaround);
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+ spapr_populate_pa_features(spapr, cpu, fdt, offset,
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+ spapr->cas_legacy_guest_workaround);
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}
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return ret;
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}
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@@ -582,7 +584,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
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page_sizes_prop, page_sizes_prop_size)));
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}
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- spapr_populate_pa_features(cpu, fdt, offset, false);
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+ spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
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cs->cpu_index / vcpus_per_socket)));
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@@ -4046,6 +4048,7 @@ static void spapr_machine_rhel740_class_options(MachineClass *mc)
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smc->has_power9_support = false;
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smc->pre_2_10_has_unused_icps = true;
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smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
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+ smc->default_caps = spapr_caps(SPAPR_CAP_HTM);
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}
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DEFINE_SPAPR_MACHINE(rhel740, "rhel7.4.0", false);
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diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
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index 968ba7b..3b35b91 100644
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--- a/hw/ppc/spapr_caps.c
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+++ b/hw/ppc/spapr_caps.c
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@@ -24,6 +24,10 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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+#include "sysemu/hw_accel.h"
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+#include "target/ppc/cpu.h"
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+#include "cpu-models.h"
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+#include "kvm_ppc.h"
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#include "hw/ppc/spapr.h"
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@@ -40,18 +44,41 @@ typedef struct sPAPRCapabilityInfo {
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void (*disallow)(sPAPRMachineState *spapr, Error **errp);
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} sPAPRCapabilityInfo;
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+static void cap_htm_allow(sPAPRMachineState *spapr, Error **errp)
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+{
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+ if (tcg_enabled()) {
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+ error_setg(errp,
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+ "No Transactional Memory support in TCG, try cap-htm=off");
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+ } else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
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+ error_setg(errp,
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+"KVM implementation does not support Transactional Memory, try cap-htm=off"
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+ );
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+ }
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+}
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+
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static sPAPRCapabilityInfo capability_table[] = {
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+ {
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+ .name = "htm",
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+ .description = "Allow Hardware Transactional Memory (HTM)",
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+ .flag = SPAPR_CAP_HTM,
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+ .allow = cap_htm_allow,
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+ /* TODO: add cap_htm_disallow */
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+ },
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};
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static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
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CPUState *cs)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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+ PowerPCCPU *cpu = POWERPC_CPU(cs);
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sPAPRCapabilities caps;
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caps = smc->default_caps;
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- /* TODO: clamp according to cpu model */
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+ if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07,
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+ 0, spapr->max_compat_pvr)) {
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+ caps.mask &= ~SPAPR_CAP_HTM;
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+ }
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return caps;
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}
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diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
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index 7267151..77dc3fb 100644
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--- a/include/hw/ppc/spapr.h
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+++ b/include/hw/ppc/spapr.h
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@@ -54,6 +54,9 @@ typedef enum {
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* Capabilities
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*/
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+/* Hardware Transactional Memory */
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+#define SPAPR_CAP_HTM 0x0000000000000001ULL
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+
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typedef struct sPAPRCapabilities sPAPRCapabilities;
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struct sPAPRCapabilities {
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uint64_t mask;
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--
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1.8.3.1
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