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From a80ee7295748aeadc1e2c37a71ee46699c9324cb Mon Sep 17 00:00:00 2001
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From: Peter Xu <peterx@redhat.com>
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Date: Fri, 9 Feb 2018 06:02:44 +0100
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Subject: [PATCH 03/15] pci/bus: let it has higher migration priority
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RH-Author: Peter Xu <peterx@redhat.com>
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Message-id: <20180209060244.17420-1-peterx@redhat.com>
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Patchwork-id: 78963
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O-Subject: [RHEL-7.5 qemu-kvm-rhev PATCH] pci/bus: let it has higher migration priority
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Bugzilla: 1538953
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RH-Acked-by: Marcel Apfelbaum <marcel@redhat.com>
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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NOTE: downstream does not have hw/pci-bridge/pcie_pci_bridge.c, so the
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original change to that file is not needed.
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In the past, we prioritized IOMMU migration so that we have such a
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priority order:
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IOMMU > PCI Devices
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When migrating a guest with both vIOMMU and a pcie-root-port, we'll
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always migrate vIOMMU first, since pci buses will be seen to have the
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same priority of general PCI devices.
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That's problematic.
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The thing is that PCI bus number information is stored in the root port,
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and that is needed by vIOMMU during post_load(), e.g., to figure out
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context entry for a device. If we don't have correct bus numbers for
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devices, we won't be able to recover device state of the DMAR memory
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regions, and things will be messed up.
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So let's boost the PCIe root ports to be even with higher priority:
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PCIe Root Port > IOMMU > PCI Devices
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A smoke test shows that this patch fixes bug 1538953.
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Also, apply this rule to all the PCI bus/bridge devices: ioh3420,
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xio3130_downstream, xio3130_upstream, pcie_pci_bridge, pci-pci bridge,
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i82801b11.
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I noted that we set pcie_pci_bridge_dev_vmstate twice. Clean that up
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together.
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CC: Alex Williamson <alex.williamson@redhat.com>
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CC: Marcel Apfelbaum <marcel@redhat.com>
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CC: Michael S. Tsirkin <mst@redhat.com>
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CC: Dr. David Alan Gilbert <dgilbert@redhat.com>
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CC: Juan Quintela <quintela@redhat.com>
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CC: Laurent Vivier <lvivier@redhat.com>
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Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1538953
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Reported-by: Maxime Coquelin <maxime.coquelin@redhat.com>
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 9d6b9db19c4b99ce5a1ad75b490c01edd2c2b0cf)
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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hw/pci-bridge/gen_pcie_root_port.c | 1 +
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hw/pci-bridge/i82801b11.c | 1 +
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hw/pci-bridge/ioh3420.c | 1 +
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hw/pci-bridge/pci_bridge_dev.c | 1 +
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hw/pci-bridge/xio3130_downstream.c | 1 +
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hw/pci-bridge/xio3130_upstream.c | 1 +
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include/migration/vmstate.h | 1 +
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7 files changed, 7 insertions(+)
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diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
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index 0e2f2e8..435fbaa 100644
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--- a/hw/pci-bridge/gen_pcie_root_port.c
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+++ b/hw/pci-bridge/gen_pcie_root_port.c
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@@ -101,6 +101,7 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
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static const VMStateDescription vmstate_rp_dev = {
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.name = "pcie-root-port",
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+ .priority = MIG_PRI_PCI_BUS,
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
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index cb522bf..60df9b2 100644
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--- a/hw/pci-bridge/i82801b11.c
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+++ b/hw/pci-bridge/i82801b11.c
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@@ -80,6 +80,7 @@ err_bridge:
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static const VMStateDescription i82801b11_bridge_dev_vmstate = {
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.name = "i82801b11_bridge",
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+ .priority = MIG_PRI_PCI_BUS,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
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VMSTATE_END_OF_LIST()
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diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
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index da4e5bd..a26d104 100644
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--- a/hw/pci-bridge/ioh3420.c
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+++ b/hw/pci-bridge/ioh3420.c
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@@ -85,6 +85,7 @@ static void ioh3420_interrupts_uninit(PCIDevice *d)
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static const VMStateDescription vmstate_ioh3420 = {
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.name = "ioh-3240-express-root-port",
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+ .priority = MIG_PRI_PCI_BUS,
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
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index d56f663..b2d861d 100644
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--- a/hw/pci-bridge/pci_bridge_dev.c
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+++ b/hw/pci-bridge/pci_bridge_dev.c
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@@ -174,6 +174,7 @@ static bool pci_device_shpc_present(void *opaque, int version_id)
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static const VMStateDescription pci_bridge_dev_vmstate = {
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.name = "pci_bridge",
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+ .priority = MIG_PRI_PCI_BUS,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
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SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),
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diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
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index 1e09d2a..4dd2e65 100644
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--- a/hw/pci-bridge/xio3130_downstream.c
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+++ b/hw/pci-bridge/xio3130_downstream.c
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@@ -161,6 +161,7 @@ static Property xio3130_downstream_props[] = {
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static const VMStateDescription vmstate_xio3130_downstream = {
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.name = "xio3130-express-downstream-port",
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+ .priority = MIG_PRI_PCI_BUS,
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
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index 227997c..c5f02a6 100644
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--- a/hw/pci-bridge/xio3130_upstream.c
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+++ b/hw/pci-bridge/xio3130_upstream.c
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@@ -133,6 +133,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
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static const VMStateDescription vmstate_xio3130_upstream = {
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.name = "xio3130-express-upstream-port",
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+ .priority = MIG_PRI_PCI_BUS,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
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index 85e43da..d23555b 100644
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--- a/include/migration/vmstate.h
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+++ b/include/migration/vmstate.h
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@@ -148,6 +148,7 @@ enum VMStateFlags {
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typedef enum {
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MIG_PRI_DEFAULT = 0,
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MIG_PRI_IOMMU, /* Must happen before PCI devices */
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+ MIG_PRI_PCI_BUS, /* Must happen before IOMMU */
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MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */
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MIG_PRI_GICV3, /* Must happen before the ITS */
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MIG_PRI_MAX,
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--
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1.8.3.1
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