From a80ee7295748aeadc1e2c37a71ee46699c9324cb Mon Sep 17 00:00:00 2001

From: Peter Xu <peterx@redhat.com>

Date: Fri, 9 Feb 2018 06:02:44 +0100

Subject: [PATCH 03/15] pci/bus: let it has higher migration priority

RH-Author: Peter Xu <peterx@redhat.com>

Message-id: <20180209060244.17420-1-peterx@redhat.com>

Patchwork-id: 78963

O-Subject: [RHEL-7.5 qemu-kvm-rhev PATCH] pci/bus: let it has higher migration priority

Bugzilla: 1538953

RH-Acked-by: Marcel Apfelbaum <marcel@redhat.com>

RH-Acked-by: Auger Eric <eric.auger@redhat.com>

RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

NOTE: downstream does not have hw/pci-bridge/pcie_pci_bridge.c, so the

      original change to that file is not needed.

In the past, we prioritized IOMMU migration so that we have such a

priority order:

    IOMMU > PCI Devices

When migrating a guest with both vIOMMU and a pcie-root-port, we'll

always migrate vIOMMU first, since pci buses will be seen to have the

same priority of general PCI devices.

That's problematic.

The thing is that PCI bus number information is stored in the root port,

and that is needed by vIOMMU during post_load(), e.g., to figure out

context entry for a device.  If we don't have correct bus numbers for

devices, we won't be able to recover device state of the DMAR memory

regions, and things will be messed up.

So let's boost the PCIe root ports to be even with higher priority:

   PCIe Root Port > IOMMU > PCI Devices

A smoke test shows that this patch fixes bug 1538953.

Also, apply this rule to all the PCI bus/bridge devices: ioh3420,

xio3130_downstream, xio3130_upstream, pcie_pci_bridge, pci-pci bridge,

i82801b11.

I noted that we set pcie_pci_bridge_dev_vmstate twice.  Clean that up

together.

CC: Alex Williamson <alex.williamson@redhat.com>

CC: Marcel Apfelbaum <marcel@redhat.com>

CC: Michael S. Tsirkin <mst@redhat.com>

CC: Dr. David Alan Gilbert <dgilbert@redhat.com>

CC: Juan Quintela <quintela@redhat.com>

CC: Laurent Vivier <lvivier@redhat.com>

Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1538953

Reported-by: Maxime Coquelin <maxime.coquelin@redhat.com>

Signed-off-by: Peter Xu <peterx@redhat.com>

Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>

Reviewed-by: Michael S. Tsirkin <mst@redhat.com>

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

(cherry picked from commit 9d6b9db19c4b99ce5a1ad75b490c01edd2c2b0cf)

Signed-off-by: Peter Xu <peterx@redhat.com>

Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>

---

 hw/pci-bridge/gen_pcie_root_port.c | 1 +

 hw/pci-bridge/i82801b11.c          | 1 +

 hw/pci-bridge/ioh3420.c            | 1 +

 hw/pci-bridge/pci_bridge_dev.c     | 1 +

 hw/pci-bridge/xio3130_downstream.c | 1 +

 hw/pci-bridge/xio3130_upstream.c   | 1 +

 include/migration/vmstate.h        | 1 +

 7 files changed, 7 insertions(+)

diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c

index 0e2f2e8..435fbaa 100644

--- a/hw/pci-bridge/gen_pcie_root_port.c

+++ b/hw/pci-bridge/gen_pcie_root_port.c

@@ -101,6 +101,7 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)

 static const VMStateDescription vmstate_rp_dev = {

     .name = "pcie-root-port",

+    .priority = MIG_PRI_PCI_BUS,

     .version_id = 1,

     .minimum_version_id = 1,

     .post_load = pcie_cap_slot_post_load,

diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c

index cb522bf..60df9b2 100644

--- a/hw/pci-bridge/i82801b11.c

+++ b/hw/pci-bridge/i82801b11.c

@@ -80,6 +80,7 @@ err_bridge:

 static const VMStateDescription i82801b11_bridge_dev_vmstate = {

     .name = "i82801b11_bridge",

+    .priority = MIG_PRI_PCI_BUS,

     .fields = (VMStateField[]) {

         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),

         VMSTATE_END_OF_LIST()

diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c

index da4e5bd..a26d104 100644

--- a/hw/pci-bridge/ioh3420.c

+++ b/hw/pci-bridge/ioh3420.c

@@ -85,6 +85,7 @@ static void ioh3420_interrupts_uninit(PCIDevice *d)

 static const VMStateDescription vmstate_ioh3420 = {

     .name = "ioh-3240-express-root-port",

+    .priority = MIG_PRI_PCI_BUS,

     .version_id = 1,

     .minimum_version_id = 1,

     .post_load = pcie_cap_slot_post_load,

diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c

index d56f663..b2d861d 100644

--- a/hw/pci-bridge/pci_bridge_dev.c

+++ b/hw/pci-bridge/pci_bridge_dev.c

@@ -174,6 +174,7 @@ static bool pci_device_shpc_present(void *opaque, int version_id)

 static const VMStateDescription pci_bridge_dev_vmstate = {

     .name = "pci_bridge",

+    .priority = MIG_PRI_PCI_BUS,

     .fields = (VMStateField[]) {

         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),

         SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),

diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c

index 1e09d2a..4dd2e65 100644

--- a/hw/pci-bridge/xio3130_downstream.c

+++ b/hw/pci-bridge/xio3130_downstream.c

@@ -161,6 +161,7 @@ static Property xio3130_downstream_props[] = {

 static const VMStateDescription vmstate_xio3130_downstream = {

     .name = "xio3130-express-downstream-port",

+    .priority = MIG_PRI_PCI_BUS,

     .version_id = 1,

     .minimum_version_id = 1,

     .post_load = pcie_cap_slot_post_load,

diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c

index 227997c..c5f02a6 100644

--- a/hw/pci-bridge/xio3130_upstream.c

+++ b/hw/pci-bridge/xio3130_upstream.c

@@ -133,6 +133,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,

 static const VMStateDescription vmstate_xio3130_upstream = {

     .name = "xio3130-express-upstream-port",

+    .priority = MIG_PRI_PCI_BUS,

     .version_id = 1,

     .minimum_version_id = 1,

     .fields = (VMStateField[]) {

diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h

index 85e43da..d23555b 100644

--- a/include/migration/vmstate.h

+++ b/include/migration/vmstate.h

@@ -148,6 +148,7 @@ enum VMStateFlags {

 typedef enum {

     MIG_PRI_DEFAULT = 0,

     MIG_PRI_IOMMU,              /* Must happen before PCI devices */

+    MIG_PRI_PCI_BUS,            /* Must happen before IOMMU */

     MIG_PRI_GICV3_ITS,          /* Must happen before PCI devices */

     MIG_PRI_GICV3,              /* Must happen before the ITS */

     MIG_PRI_MAX,

-- 

1.8.3.1