|
 |
1bdc94 |
From a075f54393d3a00554855b938f3adfd7aaafec76 Mon Sep 17 00:00:00 2001
|
|
|
1bdc94 |
From: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
1bdc94 |
Date: Thu, 30 Aug 2018 14:18:05 +0200
|
|
|
1bdc94 |
Subject: [PATCH 06/29] i386: define the 'ssbd' CPUID feature bit
|
|
|
1bdc94 |
(CVE-2018-3639)
|
|
|
1bdc94 |
MIME-Version: 1.0
|
|
|
1bdc94 |
Content-Type: text/plain; charset=UTF-8
|
|
|
1bdc94 |
Content-Transfer-Encoding: 8bit
|
|
|
1bdc94 |
|
|
|
1bdc94 |
RH-Author: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
1bdc94 |
Message-id: <20180830141805.6667-2-ehabkost@redhat.com>
|
|
|
1bdc94 |
Patchwork-id: 81977
|
|
|
1bdc94 |
O-Subject: [RHEL-7.6 qemu-kvm-rhev PATCH 1/1] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)
|
|
|
1bdc94 |
Bugzilla: 1574216
|
|
|
1bdc94 |
RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
|
|
|
1bdc94 |
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
|
|
|
1bdc94 |
RH-Acked-by: Daniel P. Berrange <berrange@redhat.com>
|
|
|
1bdc94 |
|
|
|
1bdc94 |
From: Daniel P. Berrangé <berrange@redhat.com>
|
|
|
1bdc94 |
|
|
|
1bdc94 |
New microcode introduces the "Speculative Store Bypass Disable"
|
|
|
1bdc94 |
CPUID feature bit. This needs to be exposed to guest OS to allow
|
|
|
1bdc94 |
them to protect against CVE-2018-3639.
|
|
|
1bdc94 |
|
|
|
1bdc94 |
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
|
|
|
1bdc94 |
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
|
|
1bdc94 |
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
|
|
1bdc94 |
Message-Id: <20180521215424.13520-2-berrange@redhat.com>
|
|
|
1bdc94 |
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
1bdc94 |
(cherry picked from commit d19d1f965904a533998739698020ff4ee8a103da)
|
|
|
1bdc94 |
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
1bdc94 |
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
1bdc94 |
---
|
|
|
1bdc94 |
target/i386/cpu.c | 2 +-
|
|
|
1bdc94 |
target/i386/cpu.h | 1 +
|
|
|
1bdc94 |
2 files changed, 2 insertions(+), 1 deletion(-)
|
|
|
1bdc94 |
|
|
|
1bdc94 |
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
|
1bdc94 |
index e6ad66c..e317aaf 100644
|
|
|
1bdc94 |
--- a/target/i386/cpu.c
|
|
|
1bdc94 |
+++ b/target/i386/cpu.c
|
|
|
1bdc94 |
@@ -1008,7 +1008,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
|
|
1bdc94 |
NULL, NULL, NULL, NULL,
|
|
|
1bdc94 |
NULL, NULL, NULL, NULL,
|
|
|
1bdc94 |
NULL, NULL, "spec-ctrl", NULL,
|
|
|
1bdc94 |
- NULL, NULL, NULL, NULL,
|
|
|
1bdc94 |
+ NULL, NULL, NULL, "ssbd",
|
|
|
1bdc94 |
},
|
|
|
1bdc94 |
.cpuid_eax = 7,
|
|
|
1bdc94 |
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
1bdc94 |
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
|
1bdc94 |
index c80c461..75cf5ed 100644
|
|
|
1bdc94 |
--- a/target/i386/cpu.h
|
|
|
1bdc94 |
+++ b/target/i386/cpu.h
|
|
|
1bdc94 |
@@ -686,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
|
|
|
1bdc94 |
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
|
|
|
1bdc94 |
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
|
|
|
1bdc94 |
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
|
|
|
1bdc94 |
+#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
|
|
|
1bdc94 |
|
|
|
1bdc94 |
#define KVM_HINTS_DEDICATED (1U << 0)
|
|
|
1bdc94 |
|
|
|
1bdc94 |
--
|
|
|
1bdc94 |
1.8.3.1
|
|
|
1bdc94 |
|