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From 31d4822f7d25e9438de3dc7d689cfe3dd5544cc7 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Tue, 3 Jul 2018 17:23:53 +0200
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Subject: [PATCH 08/89] i386: Add support for CPUID_8000_001E for AMD
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20180703172356.21038-8-ehabkost@redhat.com>
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Patchwork-id: 81217
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O-Subject: [RHEL-7.6 qemu-kvm-rhev PATCH v3 07/10] i386: Add support for CPUID_8000_001E for AMD
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Bugzilla: 1481253
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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From: Babu Moger <babu.moger@amd.com>
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Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
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match the underlying hardware. Please refer to the Processor Programming
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Reference (PPR) for AMD Family 17h Model for more details.
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Message-Id: <1528498581-131037-2-git-send-email-babu.moger@amd.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit ed78467a214595a63af7800a073a03ffe37cd7db)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target/i386/cpu.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 86 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 57f74c6..643d3b1 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -429,6 +429,87 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
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(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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}
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+/* Data structure to hold the configuration info for a given core index */
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+struct core_topology {
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+ /* core complex id of the current core index */
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+ int ccx_id;
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+ /*
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+ * Adjusted core index for this core in the topology
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+ * This can be 0,1,2,3 with max 4 cores in a core complex
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+ */
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+ int core_id;
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+ /* Node id for this core index */
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+ int node_id;
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+ /* Number of nodes in this config */
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+ int num_nodes;
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+};
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+
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+/*
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+ * Build the configuration closely match the EPYC hardware. Using the EPYC
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+ * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
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+ * right now. This could change in future.
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+ * nr_cores : Total number of cores in the config
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+ * core_id : Core index of the current CPU
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+ * topo : Data structure to hold all the config info for this core index
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+ */
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+static void build_core_topology(int nr_cores, int core_id,
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+ struct core_topology *topo)
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+{
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+ int nodes, cores_in_ccx;
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+
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+ /* First get the number of nodes required */
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+ nodes = nodes_in_socket(nr_cores);
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+
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+ cores_in_ccx = cores_in_core_complex(nr_cores);
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+
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+ topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
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+ topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
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+ topo->core_id = core_id % cores_in_ccx;
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+ topo->num_nodes = nodes;
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+}
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+
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+/* Encode cache info for CPUID[8000001E] */
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+static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
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+ uint32_t *eax, uint32_t *ebx,
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+ uint32_t *ecx, uint32_t *edx)
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+{
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+ struct core_topology topo = {0};
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+
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+ build_core_topology(cs->nr_cores, cpu->core_id, &topo;;
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+ *eax = cpu->apic_id;
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+ /*
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+ * CPUID_Fn8000001E_EBX
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+ * 31:16 Reserved
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+ * 15:8 Threads per core (The number of threads per core is
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+ * Threads per core + 1)
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+ * 7:0 Core id (see bit decoding below)
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+ * SMT:
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+ * 4:3 node id
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+ * 2 Core complex id
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+ * 1:0 Core id
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+ * Non SMT:
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+ * 5:4 node id
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+ * 3 Core complex id
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+ * 1:0 Core id
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+ */
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+ if (cs->nr_threads - 1) {
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+ *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
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+ (topo.ccx_id << 2) | topo.core_id;
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+ } else {
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+ *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
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+ }
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+ /*
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+ * CPUID_Fn8000001E_ECX
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+ * 31:11 Reserved
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+ * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
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+ * 7:0 Node id (see bit decoding below)
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+ * 2 Socket id
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+ * 1:0 Node id
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+ */
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+ *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | topo.node_id;
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+ *edx = 0;
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+}
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+
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/*
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* Definitions of the hardcoded cache entries we expose:
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* These are legacy cache values. If there is a need to change any
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@@ -4105,6 +4186,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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}
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break;
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+ case 0x8000001E:
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+ assert(cpu->core_id <= 255);
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+ encode_topo_cpuid8000001e(cs, cpu,
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+ eax, ebx, ecx, edx);
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+ break;
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case 0xC0000000:
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*eax = env->cpuid_xlevel2;
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*ebx = 0;
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--
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1.8.3.1
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