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From 00a6c6f0214ad15a68870ad753e656e17a12afe6 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Fri, 4 Oct 2019 19:57:12 +0200
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Subject: [PATCH 2/4] i386: Add new model of Cascadelake-Server
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20191004195714.10176-2-ehabkost@redhat.com>
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Patchwork-id: 90960
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O-Subject: [RHEL-7.8 qemu-kvm-rhev PATCH 1/3] i386: Add new model of Cascadelake-Server
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Bugzilla: 1638472
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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From: Tao Xu <tao3.xu@intel.com>
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New CPU models mostly inherit features from ancestor Skylake-Server,
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while addin new features: AVX512_VNNI, Intel PT.
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SSBD support for speculative execution
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side channel mitigations.
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Note:
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On Cascadelake, some capabilities (RDCL_NO, IBRS_ALL, RSBA,
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SKIP_L1DFL_VMENTRY and SSB_NO) are enumerated by MSR.
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These features rely on MSR based feature support patch.
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Will be added later after that patch's in.
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http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00074.html
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Signed-off-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <20180919031122.28487-2-tao3.xu@intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target/i386/cpu.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 5d6b45b..2b85193 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -2483,6 +2483,60 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Intel Xeon Processor (Skylake, IBRS)",
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},
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{
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+ .name = "Cascadelake-Server",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_INTEL,
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+ .family = 6,
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+ .model = 85,
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+ .stepping = 5,
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+ .features[FEAT_1_EDX] =
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+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+ CPUID_DE | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
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+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
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+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
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+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
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+ CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
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+ CPUID_7_0_EBX_INTEL_PT,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
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+ CPUID_7_0_ECX_AVX512VNNI,
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+ .features[FEAT_7_0_EDX] =
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+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
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+ /* Missing: XSAVES (not supported by some Linux versions,
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+ * including v4.1 to v4.12).
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+ * KVM doesn't yet expose any XSAVES state save component,
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+ * and the only one defined in Skylake (processor tracing)
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+ * probably will block migration anyway.
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+ */
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .xlevel = 0x80000008,
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+ .model_id = "Intel Xeon Processor (Cascadelake)",
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+ },
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+ {
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.name = "Opteron_G1",
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.level = 5,
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.vendor = CPUID_VENDOR_AMD,
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--
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1.8.3.1
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