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From 888e98c6d61b16f59867b91e41af9c878f4d1193 Mon Sep 17 00:00:00 2001
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From: Marcel Apfelbaum <marcel@redhat.com>
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Date: Fri, 17 Nov 2017 16:26:38 +0100
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Subject: [PATCH 29/30] hw/pci-host: Fix x86 Host Bridges 64bit PCI hole
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RH-Author: Marcel Apfelbaum <marcel@redhat.com>
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Message-id: <20171117162638.34466-1-marcel@redhat.com>
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Patchwork-id: 77746
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O-Subject: [RHEL-7.5 qemu-kvm-rhev PATCH] hw/pci-host: Fix x86 Host Bridges 64bit PCI hole
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Bugzilla: 1390346
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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Tests: Hotplug an ivshmem device with 2G on Q35 and I440fx machines
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(passes only if this patch is applied)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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- include/hw/i386/pc.h
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Moved x-pci-hole64-fix compat property from PC_COMPAT_2_10
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to PC_RHEL7_4_COMPAT
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Currently there is no MMIO range over 4G
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reserved for PCI hotplug. Since the 32bit PCI hole
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depends on the number of cold-plugged PCI devices
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and other factors, it is very possible is too small
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to hotplug PCI devices with large BARs.
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Fix it by reserving 2G for I4400FX chipset
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in order to comply with older Win32 Guest OSes
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and 32G for Q35 chipset.
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Even if the new defaults of pci-hole64-size will appear in
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"info qtree" also for older machines, the property was
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not implemented so no changes will be visible to guests.
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Note this is a regression since prev QEMU versions had
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some range reserved for 64bit PCI hotplug.
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 9fa99d2519cbf71f871e46871df12cb446dc1c3e)
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Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
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---
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hw/i386/pc.c | 22 ++++++++++++++++++++++
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hw/pci-host/piix.c | 32 ++++++++++++++++++++++++++++++--
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hw/pci-host/q35.c | 42 +++++++++++++++++++++++++++++++++++++++---
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include/hw/i386/pc.h | 12 +++++++++++-
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include/hw/pci-host/q35.h | 1 +
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5 files changed, 103 insertions(+), 6 deletions(-)
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diff --git a/hw/i386/pc.c b/hw/i386/pc.c
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index 83df57f..f37d60a 100644
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--- a/hw/i386/pc.c
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+++ b/hw/i386/pc.c
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@@ -1482,6 +1482,28 @@ void pc_memory_init(PCMachineState *pcms,
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pcms->ioapic_as = &address_space_memory;
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}
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+/*
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+ * The 64bit pci hole starts after "above 4G RAM" and
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+ * potentially the space reserved for memory hotplug.
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+ */
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+uint64_t pc_pci_hole64_start(void)
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+{
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+ PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
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+ PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
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+ uint64_t hole64_start = 0;
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+
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+ if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) {
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+ hole64_start = pcms->hotplug_memory.base;
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+ if (!pcmc->broken_reserved_end) {
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+ hole64_start += memory_region_size(&pcms->hotplug_memory.mr);
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+ }
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+ } else {
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+ hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
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+ }
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+
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+ return ROUND_UP(hole64_start, 1ULL << 30);
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+}
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+
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qemu_irq pc_allocate_cpu_irq(void)
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{
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return qemu_allocate_irq(pic_irq_request, NULL, 0);
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diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
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index 68c3922..dc37bdf 100644
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--- a/hw/pci-host/piix.c
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+++ b/hw/pci-host/piix.c
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@@ -50,6 +50,7 @@ typedef struct I440FXState {
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PCIHostState parent_obj;
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Range pci_hole;
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uint64_t pci_hole64_size;
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+ bool pci_hole64_fix;
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uint32_t short_root_bus;
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} I440FXState;
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@@ -112,6 +113,9 @@ struct PCII440FXState {
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#define I440FX_PAM_SIZE 7
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#define I440FX_SMRAM 0x72
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+/* Keep it 2G to comply with older win32 guests */
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+#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
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+
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/* Older coreboot versions (4.0 and older) read a config register that doesn't
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* exist in real hardware, to get the RAM size from QEMU.
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*/
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@@ -238,29 +242,52 @@ static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
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visit_type_uint32(v, name, &value, errp);
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}
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+/*
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+ * The 64bit PCI hole start is set by the Guest firmware
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+ * as the address of the first 64bit PCI MEM resource.
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+ * If no PCI device has resources on the 64bit area,
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+ * the 64bit PCI hole will start after "over 4G RAM" and the
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+ * reserved space for memory hotplug if any.
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+ */
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static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
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const char *name,
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void *opaque, Error **errp)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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Range w64;
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uint64_t value;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_lob(&w64);
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+ if (!value && s->pci_hole64_fix) {
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+ value = pc_pci_hole64_start();
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+ }
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visit_type_uint64(v, name, &value, errp);
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}
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+/*
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+ * The 64bit PCI hole end is set by the Guest firmware
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+ * as the address of the last 64bit PCI MEM resource.
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+ * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
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+ * that can be configured by the user.
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+ */
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static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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+ uint64_t hole64_start = pc_pci_hole64_start();
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Range w64;
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- uint64_t value;
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+ uint64_t value, hole64_end;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
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+ hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
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+ if (s->pci_hole64_fix && value < hole64_end) {
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+ value = hole64_end;
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+ }
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visit_type_uint64(v, name, &value, errp);
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}
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@@ -863,8 +890,9 @@ static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
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static Property i440fx_props[] = {
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DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
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- pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
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+ pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
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DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
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+ DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
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index 9cd07ce..d7cc898 100644
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--- a/hw/pci-host/q35.c
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+++ b/hw/pci-host/q35.c
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@@ -37,6 +37,8 @@
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* Q35 host
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*/
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+#define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35)
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+
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static void q35_host_realize(DeviceState *dev, Error **errp)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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@@ -99,29 +101,52 @@ static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
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visit_type_uint32(v, name, &value, errp);
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}
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+/*
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+ * The 64bit PCI hole start is set by the Guest firmware
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+ * as the address of the first 64bit PCI MEM resource.
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+ * If no PCI device has resources on the 64bit area,
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+ * the 64bit PCI hole will start after "over 4G RAM" and the
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+ * reserved space for memory hotplug if any.
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+ */
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static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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Range w64;
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uint64_t value;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_lob(&w64);
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+ if (!value && s->pci_hole64_fix) {
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+ value = pc_pci_hole64_start();
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+ }
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visit_type_uint64(v, name, &value, errp);
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}
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+/*
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+ * The 64bit PCI hole end is set by the Guest firmware
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+ * as the address of the last 64bit PCI MEM resource.
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+ * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
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+ * that can be configured by the user.
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+ */
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static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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+ uint64_t hole64_start = pc_pci_hole64_start();
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Range w64;
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- uint64_t value;
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+ uint64_t value, hole64_end;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
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+ hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
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+ if (s->pci_hole64_fix && value < hole64_end) {
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+ value = hole64_end;
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+ }
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visit_type_uint64(v, name, &value, errp);
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}
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4a2fec |
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@@ -133,16 +158,25 @@ static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
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visit_type_uint64(v, name, &e->size, errp);
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}
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+/*
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+ * NOTE: setting defaults for the mch.* fields in this table
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+ * doesn't work, because mch is a separate QOM object that is
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+ * zeroed by the object_initialize(&s->mch, ...) call inside
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+ * q35_host_initfn(). The default values for those
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+ * properties need to be initialized manually by
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+ * q35_host_initfn() after the object_initialize() call.
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+ */
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static Property q35_host_props[] = {
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DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
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DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
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- mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
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+ mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT),
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DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
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DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
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4a2fec |
mch.below_4g_mem_size, 0),
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4a2fec |
DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
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4a2fec |
mch.above_4g_mem_size, 0),
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4a2fec |
+ DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true),
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4a2fec |
DEFINE_PROP_END_OF_LIST(),
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4a2fec |
};
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4a2fec |
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4a2fec |
@@ -174,7 +208,9 @@ static void q35_host_initfn(Object *obj)
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4a2fec |
object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
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4a2fec |
qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
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4a2fec |
qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
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4a2fec |
-
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4a2fec |
+ /* mch's object_initialize resets the default value, set it again */
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4a2fec |
+ qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE,
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4a2fec |
+ Q35_PCI_HOST_HOLE64_SIZE_DEFAULT);
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4a2fec |
object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
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4a2fec |
q35_host_get_pci_hole_start,
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4a2fec |
NULL, NULL, NULL, NULL);
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4a2fec |
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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4a2fec |
index 6f65d79..7b46121 100644
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4a2fec |
--- a/include/hw/i386/pc.h
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4a2fec |
+++ b/include/hw/i386/pc.h
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4a2fec |
@@ -241,7 +241,6 @@ void pc_guest_info_init(PCMachineState *pcms);
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4a2fec |
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
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4a2fec |
#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
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4a2fec |
#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
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4a2fec |
-#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
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4a2fec |
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4a2fec |
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4a2fec |
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
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4a2fec |
@@ -252,6 +251,7 @@ void pc_memory_init(PCMachineState *pcms,
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4a2fec |
MemoryRegion *system_memory,
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4a2fec |
MemoryRegion *rom_memory,
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4a2fec |
MemoryRegion **ram_memory);
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4a2fec |
+uint64_t pc_pci_hole64_start(void);
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|
4a2fec |
qemu_irq pc_allocate_cpu_irq(void);
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|
4a2fec |
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
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|
4a2fec |
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
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4a2fec |
@@ -1015,6 +1015,16 @@ extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
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|
4a2fec |
.driver = "ICH9-LPC",\
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4a2fec |
.property = "__com.redhat_force-rev1-fadt",\
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|
4a2fec |
.value = "on",\
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|
4a2fec |
+ },\
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|
4a2fec |
+ { /* PC_RHEL7_4_COMPAT from PC_COMPAT_2_10 */ \
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|
4a2fec |
+ .driver = "i440FX-pcihost",\
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|
4a2fec |
+ .property = "x-pci-hole64-fix",\
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|
4a2fec |
+ .value = "off",\
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|
4a2fec |
+ },\
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|
4a2fec |
+ { /* PC_RHEL7_4_COMPAT from PC_COMPAT_2_10 */ \
|
|
|
4a2fec |
+ .driver = "q35-pcihost",\
|
|
|
4a2fec |
+ .property = "x-pci-hole64-fix",\
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|
|
4a2fec |
+ .value = "off",\
|
|
|
4a2fec |
},
|
|
|
4a2fec |
|
|
|
4a2fec |
|
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|
4a2fec |
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
|
|
|
4a2fec |
index 58983c0..8f4ddde 100644
|
|
|
4a2fec |
--- a/include/hw/pci-host/q35.h
|
|
|
4a2fec |
+++ b/include/hw/pci-host/q35.h
|
|
|
4a2fec |
@@ -68,6 +68,7 @@ typedef struct Q35PCIHost {
|
|
|
4a2fec |
PCIExpressHost parent_obj;
|
|
|
4a2fec |
/*< public >*/
|
|
|
4a2fec |
|
|
|
4a2fec |
+ bool pci_hole64_fix;
|
|
|
4a2fec |
MCHPCIState mch;
|
|
|
4a2fec |
} Q35PCIHost;
|
|
|
4a2fec |
|
|
|
4a2fec |
--
|
|
|
4a2fec |
1.8.3.1
|
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|
4a2fec |
|