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From 47d47cf36d5172dbe6d2c3b3794817d30d10610c Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Mon, 27 Jan 2014 16:07:43 +0100
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Subject: pc: Disable RDTSCP on AMD CPU models
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <1390838863-11030-3-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 56961
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O-Subject: [RHEL7 qemu-kvm PATCH v2 2/2] pc: Disable RDTSCP on AMD CPU models
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Bugzilla: 1056428
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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Bugzilla: 874400
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Upstream status: not applicable (see notes below)
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Brew scratch build: http://brewweb.devel.redhat.com/brew/taskinfo?taskID=6953316
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KVM can't expose RDTSCP to guests on AMD CPUs, so there's no point in
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having RDTSCP enabled on AMD CPU models.
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About upstream status and rationale for making it RHEL-specific:
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This is another case where independently from the upstream decision, we
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will want to add RHEL-specific code to fiddle with the CPU definitions.
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TCG does support RDTSCP, so it makes sense for upstream to keep RDTSCP
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enabled on those CPU models. We, on the other hand, care about KVM and
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know libvirt doesn't use enforce mode yet (but should eventually use
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it), so it makes sense to disable RDTSCP on AMD models in RHEL.
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(This will eventually be a problem for libvirt upstream, when it starts
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using or emulating "enforce" mode. I have added notes at:
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http://wiki.qemu.org/Features/CPUModels#Disabling_features_that_were_always_disabled_on_KVM )
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Changes v1 -> v2:
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* Fix typo: "phenon" -> "phenom"
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
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index a10fb4f..2a6ac6d 100644
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--- a/hw/i386/pc_piix.c
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+++ b/hw/i386/pc_piix.c
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@@ -937,6 +937,20 @@ static void pc_compat_rhel700(MachineState *machine)
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x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+
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+ /* KVM can't expose RDTSCP on AMD CPUs, so there's no point in enabling it
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+ * on AMD CPU models.
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+ */
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+ x86_cpu_compat_set_features("phenom", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G2", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G3", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G4", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G5", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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}
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static void pc_init_rhel700(MachineState *machine)
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diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
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index 0b88f43..df60f2e 100644
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--- a/hw/i386/pc_q35.c
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+++ b/hw/i386/pc_q35.c
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@@ -448,6 +448,20 @@ static void pc_q35_compat_rhel700(MachineState *machine)
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x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+
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+ /* KVM can't expose RDTSCP on AMD CPUs, so there's no point in enabling it
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+ * on AMD CPU models.
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+ */
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+ x86_cpu_compat_set_features("phenom", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G2", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G3", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G4", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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+ x86_cpu_compat_set_features("Opteron_G5", FEAT_8000_0001_EDX, 0,
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+ CPUID_EXT2_RDTSCP);
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}
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static void pc_q35_init_rhel700(MachineState *machine)
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