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commit 6964aa356fa606f320c7b871123aceb5c1f21999
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Author: Masahiko, Yamada <yamada.masahiko@fujitsu.com>
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Date: Tue Aug 24 14:17:29 2021 +0900
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Fix the PAPI_FUL_CCY setting for a64fx
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In a64fx, the maximum number of instruction commits is 4, so the following setting was incorrect.
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PAPI_FUL_CCY=CPU_CYCLES-0INST_COMMIT-1INST_COMMIT-2INST_COMMIT-3INST_COMMIT-4INST_COMMIT
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The correct settings are:.
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PAPI_FUL_CCY=CPU_CYCLES-0INST_COMMIT-1INST_COMMIT-2INST_COMMIT-3INST_COMMIT
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 4ef647959..74deb712f 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1934,7 +1934,7 @@ PRESET,PAPI_PRF_DM,DERIVED_SUB,L2D_CACHE_REFILL_PRF,L2D_CACHE_MIBMCH_PRF
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PRESET,PAPI_MEM_SCY,NOT_DERIVED,LD_COMP_WAIT_L2_MISS
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PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
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PRESET,PAPI_STL_CCY,NOT_DERIVED,0INST_COMMIT
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-PRESET,PAPI_FUL_CCY,DERIVED_SUB,CPU_CYCLES,0INST_COMMIT,1INST_COMMIT,2INST_COMMIT,3INST_COMMIT,4INST_COMMIT
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+PRESET,PAPI_FUL_CCY,DERIVED_SUB,CPU_CYCLES,0INST_COMMIT,1INST_COMMIT,2INST_COMMIT,3INST_COMMIT
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PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
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PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
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PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
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commit fbf3b9e3d17c4ec4bd7e33410c44fc5aed57e36f
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Author: Masahiko, Yamada <yamada.masahiko@fujitsu.com>
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Date: Fri Mar 4 15:41:30 2022 +0900
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Add PAPI idle-related preset events for a64fx
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For a64fx, add four PAPI idle-related preset events
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(PAPI_BRU_IDL/PAPI_FXU_IDL/PAPI_FPU_IDL/PAPI_LSU_IDL).
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PAPI_BRU_IDL = BR_COMP_WAIT
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PAPI_FXU_IDL = EU_COMP_WAIT - FL_COMP_WAIT
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PAPI_FPU_IDL = FL_COMP_WAIT
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PAPI_LSU_IDL = LD_COMP_WAIT
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The specifications of BR_COMP_WAIT, EU_COMP_WAIT, FL_COMP_WAIT,
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and LD_COMP_WAIT can be found in the "14.4. Cycle Accounting"
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on A64FX_Microarchitecture_Manual_en_1.5.pdf at the following URL:.
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https://github.com/fujitsu/A64FX/blob/master/doc
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Signed-off-by: Masahiko, Yamada <yamada.masahiko@fujitsu.com>
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 74deb712f..1cd498e91 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1935,6 +1935,10 @@ PRESET,PAPI_MEM_SCY,NOT_DERIVED,LD_COMP_WAIT_L2_MISS
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PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
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PRESET,PAPI_STL_CCY,NOT_DERIVED,0INST_COMMIT
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PRESET,PAPI_FUL_CCY,DERIVED_SUB,CPU_CYCLES,0INST_COMMIT,1INST_COMMIT,2INST_COMMIT,3INST_COMMIT
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+PRESET,PAPI_BRU_IDL,NOT_DERIVED,BR_COMP_WAIT
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+PRESET,PAPI_FXU_IDL,DERIVED_SUB,EU_COMP_WAIT,FL_COMP_WAIT
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+PRESET,PAPI_FPU_IDL,NOT_DERIVED,FL_COMP_WAIT
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+PRESET,PAPI_LSU_IDL,NOT_DERIVED,LD_COMP_WAIT
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PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
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PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
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PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
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