commit 34d0065a1a790fc2be05a5ef1d8b0bbf28b814fe

Author: William Cohen <wcohen@redhat.com>

Date:   Wed Feb 12 08:05:38 2014 -0600

    Provide basic AArch64 (ARMv8) support

    The AArch64 (ARMv8) support is provided as an ARM variant to allow use

    in both 32-bit and 64-bit ARM environments.  The support in this patch

    is just the basic events described in the AArch64 documentation.

    AArch64 processor implementation may provide additional implementation

    specific events.  One could add code to recognize those processor

    specific implementations and include the armv8-pmuv3-common base

    events into the event sets for the processor implementations.

    The APM X-Gene processor type is included in this patch as an

    implementation, although there are no known processor-specific events

    to add at this time.

    Below is example run on the ARM Foundation simulator collecting data

    on a build of OProfile.

    $ cd oprofile

    $ operf make

    ...

    $ opreport -t 5

    Using /home/wcohen/oprofile/oprofile/oprofile_data/samples/ for samples directory.

    WARNING: Lost samples detected! See /home/wcohen/oprofile/oprofile/oprofile_data/samples/operf.log for details.

    CPU: ARM AArch64

    Counted CPU_CYCLES events (Cycle) with a unit mask of 0x00 (No unit mask) count 100000

    CPU_CYCLES:100000|

      samples|      %|

    ------------------

        10943 90.5877 make

    	CPU_CYCLES:100000|

    	  samples|      %|

    	------------------

    	     5281 48.2592 make

    	     4543 41.5151 libc-2.17.so

    	     1079  9.8602 kallsyms

    	       40  0.3655 ld-2.17.so

          735  6.0844 sh

    	CPU_CYCLES:100000|

    	  samples|      %|

    	------------------

    	      321 43.6735 kallsyms

    	      298 40.5442 libc-2.17.so

    	       94 12.7891 bash

    	       22  2.9932 ld-2.17.so

    Signed-off-by: William Cohen <wcohen@redhat.com>

diff --git a/events/Makefile.am b/events/Makefile.am

index ad45642..3e43d10 100644

--- a/events/Makefile.am

+++ b/events/Makefile.am

@@ -59,6 +59,8 @@ event_files = \

 	arm/armv7-ca7/events arm/armv7-ca7/unit_masks \

 	arm/armv7-ca15/events arm/armv7-ca15/unit_masks \

 	arm/mpcore/events arm/mpcore/unit_masks \

+	arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \

+	arm/armv8-xgene/events arm/armv8-xgene/unit_masks \

 	avr32/events avr32/unit_masks \

 	mips/20K/events mips/20K/unit_masks \

 	mips/24K/events mips/24K/unit_masks \

diff --git a/events/arm/armv8-pmuv3-common/events b/events/arm/armv8-pmuv3-common/events

new file mode 100644

index 0000000..3cdff03

--- /dev/null

+++ b/events/arm/armv8-pmuv3-common/events

@@ -0,0 +1,38 @@

+#

+# Copyright (c) Red Hat, 2014.

+# Contributed by William Cohen <wcohen@redhat.com>

+#

+# ARMv8 pmu v3 architected events

+

+event:0x00 um:zero minimum:500 name:SW_INCR : Instruction architecturally executed, condition code check pass, software increment

+event:0x01 um:zero minimum:5000 name:L1I_CACHE_REFILL : Level 1 instruction cache refill

+event:0x02 um:zero minimum:5000 name:L1I_TLB_REFILL : Level 1 instruction TLB refill

+event:0x03 um:zero minimum:5000 name:L1D_CACHE_REFILL : Level 1 data cache refill

+event:0x04 um:zero minimum:5000 name:L1D_CACHE : Level 1 data cache access

+event:0x05 um:zero minimum:5000 name:L1D_TLB_REFILL : Level 1 data TLB refill

+event:0x06 um:zero minimum:100000 name:LD_RETIRED : Instruction architecturally executed, condition code check pass, load

+event:0x07 um:zero minimum:100000 name:ST_RETIRED : Instruction architecturally executed, condition code check pass, store

+event:0x08 um:zero minimum:100000 name:INST_RETIRED : Instruction architecturally executed

+event:0x09 um:zero minimum:500 name:EXC_TAKEN : Exception taken

+event:0x0A um:zero minimum:500 name:EXC_RETURN : Instruction architecturally executed, condition code check pass, exception return

+event:0x0B um:zero minimum:500 name:CID_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, write to CONTEXTIDR

+event:0x0C um:zero minimum:5000 name:PC_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, software change of the PC

+event:0x0D um:zero minimum:5000 name:BR_IMMED_RETIRED : Instruction architecturally executed, immediate branch

+event:0x0E um:zero minimum:5000 name:BR_RETURN_RETIRED : Instruction architecturally executed, condition code check pass, procedure return

+event:0x0F um:zero minimum:500 name:UNALIGNED_LDST_RETIRED : Instruction architecturally executed, condition code check pass, unaligned load or store

+event:0x10 um:zero minimum:5000 name:BR_MIS_PRED : Mispredicted or not predicted branch speculatively executed

+event:0x11 um:zero minimum:100000 name:CPU_CYCLES : Cycle

+event:0x12 um:zero minimum:5000 name:BR_PRED : Predictable branch speculatively executed

+event:0x13 um:zero minimum:100000 name:MEM_ACCESS : Data memory access

+event:0x14 um:zero minimum:5000 name:L1I_CACHE : Level 1 instruction cache access

+event:0x15 um:zero minimum:5000 name:L1D_CACHE_WB : Level 1 data cache write-back

+event:0x16 um:zero minimum:5000 name:L2D_CACHE : Level 2 data cache access

+event:0x17 um:zero minimum:5000 name:L2D_CACHE_REFILL : Level 2 data cache refill

+event:0x18 um:zero minimum:5000 name:L2D_CACHE_WB : Level 2 data cache write-back

+event:0x19 um:zero minimum:5000 name:BUS_ACCESS : Bus access

+event:0x1A um:zero minimum:500 name:MEMORY_ERROR : Local memory error

+event:0x1B um:zero minimum:100000 name:INST_SPEC : Operation speculatively executed

+event:0x1C um:zero minimum:5000 name:TTBR_WRITE_RETIRED : Instruction architecturally executed, condition code check pass, write to TTBR

+event:0x1D um:zero minimum:5000 name:BUS_CYCLES : Bus cycle

+event:0x1F um:zero minimum:5000 name:L1D_CACHE_ALLOCATE : Level 1 data cache allocation without refill

+event:0x20 um:zero minimum:5000 name:L2D_CACHE_ALLOCATE : Level 2 data cache allocation without refill

diff --git a/events/arm/armv8-pmuv3-common/unit_masks b/events/arm/armv8-pmuv3-common/unit_masks

new file mode 100644

index 0000000..7666c35

--- /dev/null

+++ b/events/arm/armv8-pmuv3-common/unit_masks

@@ -0,0 +1,4 @@

+# ARMv8 architected events unit masks

+#

+name:zero type:mandatory default:0x00

+	0x00 No unit mask

diff --git a/events/arm/armv8-xgene/events b/events/arm/armv8-xgene/events

new file mode 100644

index 0000000..3e28463

--- /dev/null

+++ b/events/arm/armv8-xgene/events

@@ -0,0 +1,7 @@

+#

+# Copyright (c) Red Hat, 2014.

+# Contributed by William Cohen <wcohen@redhat.com>

+#

+# Basic ARM V8 events

+#

+include:arm/armv8-pmuv3-common

diff --git a/events/arm/armv8-xgene/unit_masks b/events/arm/armv8-xgene/unit_masks

new file mode 100644

index 0000000..9ace2eb

--- /dev/null

+++ b/events/arm/armv8-xgene/unit_masks

@@ -0,0 +1,3 @@

+# ARMv8 architected events unit masks

+#

+include:arm/armv8-pmuv3-common

diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c

index 1ae2913..0cfb4ea 100644

--- a/libop/op_cpu_type.c

+++ b/libop/op_cpu_type.c

@@ -129,6 +129,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {

 	{ "ppc64 POWER8", "ppc64/power8", CPU_PPC64_POWER8, 6 },

 	{ "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 },

 	{ "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 },

+	{ "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 },

 };

 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);

@@ -395,6 +396,11 @@ static op_cpu _get_arm_cpu_type(void)

 		case 0xc0f:

 			return op_get_cpu_number("arm/armv7-ca15");

 		}

+	} else if (vendorid == 0x50) {	/* Applied Micro Circuits Corporation */

+		switch (cpuid) {

+		case 0x000:

+			return op_get_cpu_number("arm/armv8-xgene");

+		}

 	} else if (vendorid == 0x69) {	/* Intel xscale */

 		switch (cpuid >> 9) {

 		case 1:

@@ -631,7 +637,8 @@ static op_cpu __get_cpu_type_alt_method(void)

 	if (strncmp(uname_info.machine, "ppc64", 5) == 0) {

 		return _get_ppc64_cpu_type();

 	}

-	if (strncmp(uname_info.machine, "arm", 3) == 0) {

+	if (strncmp(uname_info.machine, "arm", 3) == 0 ||

+	    strncmp(uname_info.machine, "aarch64", 7) == 0) {

 		return _get_arm_cpu_type();

 	}

 	if (strncmp(uname_info.machine, "tile", 4) == 0) {

diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h

index 67e16de..7c478ad 100644

--- a/libop/op_cpu_type.h

+++ b/libop/op_cpu_type.h

@@ -109,6 +109,7 @@ typedef enum {

 	CPU_PPC64_POWER8, /**< ppc64 POWER8 family */

 	CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */

 	CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */

+	CPU_ARM_V8_APM_XGENE, /* APM X-Gene */

 	MAX_CPU_TYPE

 } op_cpu;

diff --git a/libop/op_events.c b/libop/op_events.c

index 358a154..e0d3ed5 100644

--- a/libop/op_events.c

+++ b/libop/op_events.c

@@ -1253,6 +1253,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)

 		case CPU_AVR32:

 		case CPU_ARM_SCORPION:

 		case CPU_ARM_SCORPIONMP:

+		case CPU_ARM_V8_XGENE:

 			descr->name = "CPU_CYCLES";

 			break;

diff --git a/utils/opcontrol b/utils/opcontrol

index 38bb1ac..04a4a91 100755

--- a/utils/opcontrol

+++ b/utils/opcontrol

@@ -400,6 +400,11 @@ do_init()

 				do_deinit

 				exit 1

 				;;

+		        aarch64/*)

+				echo "*** ARM AArch64 processors are not supported with opcontrol.  Please use operf instead. ***"

+				do_deinit

+				exit 1

+				;;

 		esac

 	fi

diff --git a/utils/ophelp.c b/utils/ophelp.c

index af4c1e5..35f47bc 100644

--- a/utils/ophelp.c

+++ b/utils/ophelp.c

@@ -656,6 +656,13 @@ int main(int argc, char const * argv[])

 			"Cortex A15 DDI (ARM DDI 0438F, revision r3p1)\n";

 		break;

+	case CPU_ARM_V8_APM_XGENE:

+		event_doc =

+			"See ARM Architecture Reference Manual \n"

+			"ARMv8, for ARMv8-A architecture profile\n"

+			"DDI (ARM DDI0487A.a)\n";

+		break;

+

 	case CPU_PPC64_PA6T:

 		event_doc =

 			"See PA6T Power Implementation Features Book IV\n"

commit a5eec42a9324915947e78634ddcce55b159a5dd2

Author: Maynard Johnson <maynardj@us.ibm.com>

Date:   Wed Feb 12 08:29:15 2014 -0600

    Minor fixup for previous commit

    The previous commit for the new APM X-Gene (AaArch64 ARMv8)

    processor went through a number of iterations before acceptance.

    I missed changing one of the references to the new CPU type

    from CPU_ARM_V8_XGENE to CPU_ARM_V8_APM_XGENE when I committed it.

    This patch fixes that.

    Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>

diff --git a/libop/op_events.c b/libop/op_events.c

index e0d3ed5..77fc8a5 100644

--- a/libop/op_events.c

+++ b/libop/op_events.c

@@ -1253,7 +1253,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)

 		case CPU_AVR32:

 		case CPU_ARM_SCORPION:

 		case CPU_ARM_SCORPIONMP:

-		case CPU_ARM_V8_XGENE:

+		case CPU_ARM_V8_APM_XGENE

 			descr->name = "CPU_CYCLES";

 			break;

commit c4e390042458aee07016da0cab251b0ad67b8d2b

Author: William Cohen <wcohen@redhat.com>

Date:   Wed Feb 12 11:56:39 2014 -0500

    Add missing ':' on case statement for CPU_ARM_V8_APM_XGENE

diff --git a/libop/op_events.c b/libop/op_events.c

index 77fc8a5..968ff04 100644

--- a/libop/op_events.c

+++ b/libop/op_events.c

@@ -1253,7 +1253,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)

 		case CPU_AVR32:

 		case CPU_ARM_SCORPION:

 		case CPU_ARM_SCORPIONMP:

-		case CPU_ARM_V8_APM_XGENE

+		case CPU_ARM_V8_APM_XGENE:

 			descr->name = "CPU_CYCLES";

 			break;

From 40adac210cf9ac8d79a90609c91b8ee5e05b8a2f Mon Sep 17 00:00:00 2001

From: William Cohen <wcohen@redhat.com>

Date: Mon, 21 Jul 2014 14:36:23 -0400

Subject: [PATCH 1/2] Add oprofile support for ARM Cortex A57 microarchitecture

This patch adds the event list of the ARM Cortex A57 architecture.

The patch is very straight forward: just add the model numbers and

type in the usual places and add the event list.

Passes make check

Signed-off-by: William Cohen <wcohen@redhat.com>

---

 events/Makefile.am               |  1 +

 events/arm/armv8-ca57/events     | 67 ++++++++++++++++++++++++++++++++++++++++

 events/arm/armv8-ca57/unit_masks |  3 ++

 libop/op_cpu_type.c              |  3 ++

 libop/op_cpu_type.h              |  1 +

 libop/op_events.c                |  1 +

 utils/ophelp.c                   |  6 ++++

 7 files changed, 82 insertions(+)

 create mode 100644 events/arm/armv8-ca57/events

 create mode 100644 events/arm/armv8-ca57/unit_masks

diff --git a/events/Makefile.am b/events/Makefile.am

index f6fd3d7..b4bca1e 100644

--- a/events/Makefile.am

+++ b/events/Makefile.am

@@ -62,6 +62,7 @@ event_files = \

 	arm/mpcore/events arm/mpcore/unit_masks \

 	arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \

 	arm/armv8-xgene/events arm/armv8-xgene/unit_masks \

+	arm/armv8-ca57/events arm/armv8-ca57/unit_masks \

 	avr32/events avr32/unit_masks \

 	mips/20K/events mips/20K/unit_masks \

 	mips/24K/events mips/24K/unit_masks \

diff --git a/events/arm/armv8-ca57/events b/events/arm/armv8-ca57/events

new file mode 100644

index 0000000..62974c1

--- /dev/null

+++ b/events/arm/armv8-ca57/events

@@ -0,0 +1,67 @@

+#

+# Copyright (c) Red Hat, 2014.

+# Contributed by William Cohen <wcohen@redhat.com>

+#

+# ARM Cortex A57 events

+# From Cortex A57 TRM

+#

+include:arm/armv8-pmuv3-common

+event:0x40 um:zero minimum:10007 name:L1D_CACHE_LD : Level 1 data cache access - Read

+event:0x41 um:zero minimum:10007 name:L1D_CACHE_ST : Level 1 data cache access - Write

+event:0x42 um:zero minimum:10007 name:L1D_CACHE_REFILL_LD : Level 1 data cache refill - Read

+event:0x43 um:zero minimum:10007 name:L1D_CACHE_REFILL_ST : Level 1 data cache refill - Write

+event:0x46 um:zero minimum:10007 name:L1D_CACHE_WB_VICTIM : Level 1 data cache Write-back - Victim

+event:0x47 um:zero minimum:10007 name:L1D_CACHE_WB_CLEAN : Level 1 data cache Write-back - Cleaning event:and coherency

+event:0x48 um:zero minimum:10007 name:L1D_CACHE_INVAL : Level 1 data cache invalidate

+event:0x4C um:zero minimum:10007 name:L1D_TLB_REFILL_LD : Level 1 data TLB refill - Read

+event:0x4D um:zero minimum:10007 name:L1D_TLB_REFILL_ST : Level 1 data TLB refill - Write

+event:0x50 um:zero minimum:10007 name:L2D_CACHE_LD : Level 2 data cache access - Read

+event:0x51 um:zero minimum:10007 name:L2D_CACHE_ST : Level 2 data cache access - Write

+event:0x52 um:zero minimum:10007 name:L2D_CACHE_REFILL_LD : Level 2 data cache refill - Read

+event:0x53 um:zero minimum:10007 name:L2D_CACHE_REFILL_ST : Level 2 data cache refill - Write

+event:0x56 um:zero minimum:10007 name:L2D_CACHE_WB_VICTIM : Level 2 data cache Write-back - Victim

+event:0x57 um:zero minimum:10007 name:L2D_CACHE_WB_CLEAN : Level 2 data cache Write-back - Cleaning and coherency

+event:0x58 um:zero minimum:10007 name:L2D_CACHE_INVAL : Level 2 data cache invalidate

+event:0x60 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read

+event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write

+event:0x62 um:zero minimum:10007 name:BUS_ACCESS_SHARED : Bus access - Normal

+event:0x63 um:zero minimum:10007 name:BUS_ACCESS_NOT_SHARED : Bus access - Not normal

+event:0x64 um:zero minimum:10007 name:BUS_ACCESS_NORMAL : Bus access - Normal

+event:0x65 um:zero minimum:10007 name:BUS_ACCESS_PERIPH : Bus access - Peripheral

+event:0x66 um:zero minimum:10007 name:MEM_ACCESS_LD : Data memory access - Read

+event:0x67 um:zero minimum:10007 name:MEM_ACCESS_ST : Data memory access - Write

+event:0x68 um:zero minimum:10007 name:UNALIGNED_LD_SPEC : Unaligned access - Read

+event:0x69 um:zero minimum:10007 name:UNALIGNED_ST_SPEC : Unaligned access - Write

+event:0x6A um:zero minimum:10007 name:UNALIGNED_LDST_SPEC : Unaligned access

+event:0x6C um:zero minimum:10007 name:LDREX_SPEC : Exclusive operation speculatively executed - LDREX

+event:0x6D um:zero minimum:10007 name:STREX_PASS_SPEC : Exclusive instruction speculatively executed - STREX pass

+event:0x6E um:zero minimum:10007 name:STREX_FAIL_SPEC : Exclusive operation speculatively executed - STREX fail

+event:0x70 um:zero minimum:10007 name:LD_SPEC : Operation speculatively executed - Load

+event:0x71 um:zero minimum:10007 name:ST_SPEC : Operation speculatively executed - Store

+event:0x72 um:zero minimum:10007 name:LDST_SPEC : Operation speculatively executed - Load or store

+event:0x73 um:zero minimum:10007 name:DP_SPEC : Operation speculatively executed - Integer data processing

+event:0x74 um:zero minimum:10007 name:ASE_SPEC : Operation speculatively executed - Advanced SIMD

+event:0x75 um:zero minimum:10007 name:VFP_SPEC : Operation speculatively executed - VFP

+event:0x76 um:zero minimum:10007 name:PC_WRITE_SPEC : Operation speculatively executed - Software change of the PC

+event:0x77 um:zero minimum:10007 name:CRYPTO_SPEC : Operation speculatively executed, crypto data processing

+event:0x78 um:zero minimum:10007 name:BR_IMMED_SPEC : Branch speculatively executed - Immediate branch

+event:0x79 um:zero minimum:10007 name:BR_RETURN_SPEC : Branch speculatively executed - Procedure return

+event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch

+event:0x7C um:zero minimum:10007 name:ISB_SPEC : Barrier speculatively executed - ISB

+event:0x7D um:zero minimum:10007 name:DSB_SPEC : Barrier speculatively executed - DSB

+event:0x7E um:zero minimum:10007 name:DMB_SPEC : Barrier speculatively executed - DMB

+event:0x81 um:zero minimum:10007 name:EXC_UNDEF : Exception taken, other synchronous

+event:0x82 um:zero minimum:10007 name:EXC_SVC : Exception taken, Supervisor Call

+event:0x83 um:zero minimum:10007 name:EXC_PABORT : Exception taken, Instruction Abort

+event:0x84 um:zero minimum:10007 name:EXC_DABORT : Exception taken, Data Abort or SError

+event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ

+event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ

+event:0x88 um:zero minimum:10007 name:EXC_SMC : Exception taken, Secure Monitor Call

+event:0x8A um:zero minimum:10007 name:EXC_HVC : Exception taken, Hypervisor Call

+event:0x8B um:zero minimum:10007 name:EXC_TRAP_PABORT : Exception taken, Instruction Abort not taken locally

+event:0x8C um:zero minimum:10007 name:EXC_TRAP_DABORT : Exception taken, Data Abort, or SError not taken locally

+event:0x8D um:zero minimum:10007 name:EXC_TRAP_OTHER : Exception taken – Other traps not taken locally

+event:0x8E um:zero minimum:10007 name:EXC_TRAP_IRQ : Exception taken, IRQ not taken locally

+event:0x8F um:zero minimum:10007 name:EXC_TRAP_FIQ : Exception taken, FIQ not taken locally

+event:0x90 um:zero minimum:10007 name:RC_LD_SPEC : Release consistency instruction speculatively executed – Load-Acquire

+event:0x91 um:zero minimum:10007 name:RC_ST_SPEC : Release consistency instruction speculatively executed – Store-Release

diff --git a/events/arm/armv8-ca57/unit_masks b/events/arm/armv8-ca57/unit_masks

new file mode 100644

index 0000000..5d69263

--- /dev/null

+++ b/events/arm/armv8-ca57/unit_masks

@@ -0,0 +1,3 @@

+# ARMv8 Cortex A57 unit masks

+#

+include:arm/armv8-pmuv3-common

diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c

index bce230a..163bd1c 100644

--- a/libop/op_cpu_type.c

+++ b/libop/op_cpu_type.c

@@ -131,6 +131,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {

 	{ "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 },

 	{ "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 },

 	{ "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 },

+	{ "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6},

 };

 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);

@@ -396,6 +397,8 @@ static op_cpu _get_arm_cpu_type(void)

 			return op_get_cpu_number("arm/armv7-ca9");

 		case 0xc0f:

 			return op_get_cpu_number("arm/armv7-ca15");

+		case 0xd07:

+			return op_get_cpu_number("arm/armv8-ca57");

 		}

 	} else if (vendorid == 0x50) {	/* Applied Micro Circuits Corporation */

 		switch (cpuid) {

diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h

index 3754156..aebd7f6 100644

--- a/libop/op_cpu_type.h

+++ b/libop/op_cpu_type.h

@@ -111,6 +111,7 @@ typedef enum {

 	CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */

 	CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */

 	CPU_ARM_V8_APM_XGENE, /* APM X-Gene */

+	CPU_ARM_V8_CA57, /* ARM Cortex-A57 */

 	MAX_CPU_TYPE

 } op_cpu;

diff --git a/libop/op_events.c b/libop/op_events.c

index b8900a5..d5249b7 100644

--- a/libop/op_events.c

+++ b/libop/op_events.c

@@ -1255,6 +1255,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)

 		case CPU_ARM_SCORPION:

 		case CPU_ARM_SCORPIONMP:

 		case CPU_ARM_V8_APM_XGENE:

+		case CPU_ARM_V8_CA57:

 			descr->name = "CPU_CYCLES";

 			break;

diff --git a/utils/ophelp.c b/utils/ophelp.c

index bf3fbcb..a5edf56 100644

--- a/utils/ophelp.c

+++ b/utils/ophelp.c

@@ -664,6 +664,12 @@ int main(int argc, char const * argv[])

 			"DDI (ARM DDI0487A.a)\n";

 		break;

+	case CPU_ARM_V8_CA57:

+		event_doc =

+			"See Cortex-A57 MPCore Technical Reference Manual\n"

+			"Cortex A57 DDI (ARM DDI 0488D, revision r1p1)\n";

+		break;

+

 	case CPU_PPC64_PA6T:

 		event_doc =

 			"See PA6T Power Implementation Features Book IV\n"

-- 

1.9.3

From 78db0d3eb65e6005931b0402484e759c35df79f1 Mon Sep 17 00:00:00 2001

From: William Cohen <wcohen@redhat.com>

Date: Wed, 23 Jul 2014 23:25:21 -0400

Subject: [PATCH] Add oprofile support for ARM Cortex A53 microarchitecture

This patch adds the event list of the ARM Cortex A53 architecture.

The patch is very straight forward: just add the model numbers and

type in the usual places and add the event list.

Passes make check

Signed-off-by: William Cohen <wcohen@redhat.com>

---

 events/Makefile.am               |  1 +

 events/arm/armv8-ca53/events     | 38 ++++++++++++++++++++++++++++++++++++++

 events/arm/armv8-ca53/unit_masks |  3 +++

 libop/op_cpu_type.c              |  3 +++

 libop/op_cpu_type.h              |  1 +

 libop/op_events.c                |  1 +

 utils/ophelp.c                   |  6 ++++++

 7 files changed, 53 insertions(+)

 create mode 100644 events/arm/armv8-ca53/events

 create mode 100644 events/arm/armv8-ca53/unit_masks

diff --git a/events/Makefile.am b/events/Makefile.am

index b4bca1e..67be125 100644

--- a/events/Makefile.am

+++ b/events/Makefile.am

@@ -63,6 +63,7 @@ event_files = \

 	arm/armv8-pmuv3-common/events arm/armv8-pmuv3-common/unit_masks \

 	arm/armv8-xgene/events arm/armv8-xgene/unit_masks \

 	arm/armv8-ca57/events arm/armv8-ca57/unit_masks \

+	arm/armv8-ca53/events arm/armv8-ca53/unit_masks \

 	avr32/events avr32/unit_masks \

 	mips/20K/events mips/20K/unit_masks \

 	mips/24K/events mips/24K/unit_masks \

diff --git a/events/arm/armv8-ca53/events b/events/arm/armv8-ca53/events

new file mode 100644

index 0000000..5e1b4d8

--- /dev/null

+++ b/events/arm/armv8-ca53/events

@@ -0,0 +1,38 @@

+#

+# Copyright (c) Red Hat, 2014.

+# Contributed by William Cohen <wcohen@redhat.com>

+#

+# ARM Cortex A53 events

+# From Cortex A53 TRM

+#

+include:arm/armv8-pmuv3-common

+event:0x60 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read

+event:0x61 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write

+event:0x7A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculatively executed - Indirect branch

+event:0x86 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ

+event:0x87 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ

+event:0xC0 um:zero minimum:10007 name:EXT_MEM_REQ : External memory request

+event:0xC1 um:zero minimum:10007 name:EXT_MEM_REQ_NC : Non-cacheable external memory request

+event:0xC2 um:zero minimum:10007 name:PREFETCH_LINEFILL : Linefill because of prefetch

+event:0xC3 um:zero minimum:10007 name:PREFETCH_LINEFILL_DROP : Instruction Cache Throttle occurred

+event:0xC4 um:zero minimum:10007 name:READ_ALLOC_ENTER : Entering read allocate mode

+event:0xC5 um:zero minimum:10007 name:READ_ALLOC : Read allocate mode

+event:0xC6 um:zero minimum:10007 name:PRE_DECODE_ERR : Pre-decode error

+event:0xC7 um:zero minimum:10007 name:STALL_SB_FULL : Data Write operation that stalls the pipeline because the store buffer is full

+event:0xC8 um:zero minimum:10007 name:EXT_SNOOP : SCU Snooped data from another CPU for this CPU

+event:0xC9 um:zero minimum:10007 name:BR_COND : Conditional branch executed

+event:0xCA um:zero minimum:10007 name:BR_INDIRECT_MISPRED : Indirect branch mispredicted

+event:0xCB um:zero minimum:10007 name:BR_INDIRECT_MISPRED_ADDR : Indirect branch mispredicted because of address miscompare

+event:0xCC um:zero minimum:10007 name:BR_COND_MISPRED : Conditional branch mispredicted

+event:0xD0 um:zero minimum:10007 name:L1I_CACHE_ERR : L1 Instruction Cache (data or tag) memory error

+event:0xD1 um:zero minimum:10007 name:L1D_CACHE_ERR : L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable

+event:0xD2 um:zero minimum:10007 name:TLB_ERR : TLB memory error

+event:0xE0 um:zero minimum:10007 name:OTHER_IQ_DEP_STALL : Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error

+event:0xE1 um:zero minimum:10007 name:IC_DEP_STALL : Cycles the DPU IQ is empty and there is an instruction cache miss being processed

+event:0xE2 um:zero minimum:10007 name:IUTLB_DEP_STALL : Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed

+event:0xE3 um:zero minimum:10007 name:DECODE_DEP_STALL : Cycles the DPU IQ is empty and there is a pre-decode error being processed

+event:0xE4 um:zero minimum:10007 name:OTHER_INTERLOCK_STALL : Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction

+event:0xE5 um:zero minimum:10007 name:AGU_DEP_STALL : Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU

+event:0xE6 um:zero minimum:10007 name:SIMD_DEP_STALL : Cycles there is an interlock for an Advanced SIMD/Floating-point operation.

+event:0xE7 um:zero minimum:10007 name:LD_DEP_STALL : Cycles there is a stall in the Wr stage because of a load miss

+event:0xE8 um:zero minimum:10007 name:ST_DEP_STALL : Cycles there is a stall in the Wr stage because of a store

diff --git a/events/arm/armv8-ca53/unit_masks b/events/arm/armv8-ca53/unit_masks

new file mode 100644

index 0000000..42b12b4

--- /dev/null

+++ b/events/arm/armv8-ca53/unit_masks

@@ -0,0 +1,3 @@

+# ARMv8 Cortex A53 unit masks

+#

+include:arm/armv8-pmuv3-common

diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c

index 163bd1c..055c64b 100644

--- a/libop/op_cpu_type.c

+++ b/libop/op_cpu_type.c

@@ -132,6 +132,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {

 	{ "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 },

	{ "APM X-Gene", "arm/armv8-xgene", CPU_ARM_V8_APM_XGENE, 6 },

	{ "ARM Cortex-A57", "arm/armv8-ca57", CPU_ARM_V8_CA57, 6},

+	{ "ARM Cortex-A53", "arm/armv8-ca53", CPU_ARM_V8_CA53, 6},

 };

 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);

@@ -399,6 +400,8 @@ static op_cpu _get_arm_cpu_type(void)

 			return op_get_cpu_number("arm/armv7-ca15");

 		case 0xd07:

 			return op_get_cpu_number("arm/armv8-ca57");

+		case 0xd03:

+			return op_get_cpu_number("arm/armv8-ca53");

 		}

 	} else if (vendorid == 0x50) {	/* Applied Micro Circuits Corporation */

 		switch (cpuid) {

diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h

index aebd7f6..a6bb323 100644

--- a/libop/op_cpu_type.h

+++ b/libop/op_cpu_type.h

@@ -112,6 +112,7 @@ typedef enum {

 	CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */

 	CPU_ARM_V8_APM_XGENE, /* APM X-Gene */

 	CPU_ARM_V8_CA57, /* ARM Cortex-A57 */

+	CPU_ARM_V8_CA53, /* ARM Cortex-A53 */

 	MAX_CPU_TYPE

 } op_cpu;

diff --git a/libop/op_events.c b/libop/op_events.c

index d5249b7..bbeb212 100644

--- a/libop/op_events.c

+++ b/libop/op_events.c

@@ -1256,6 +1256,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)

 		case CPU_ARM_SCORPIONMP:

 		case CPU_ARM_V8_APM_XGENE:

 		case CPU_ARM_V8_CA57:

+		case CPU_ARM_V8_CA53:

 			descr->name = "CPU_CYCLES";

 			break;

diff --git a/utils/ophelp.c b/utils/ophelp.c

index a5edf56..980c6dc 100644

--- a/utils/ophelp.c

+++ b/utils/ophelp.c

@@ -670,6 +670,12 @@ int main(int argc, char const * argv[])

 			"Cortex A57 DDI (ARM DDI 0488D, revision r1p1)\n";

 		break;

+	case CPU_ARM_V8_CA53:

+		event_doc =

+			"See Cortex-A53 MPCore Technical Reference Manual\n"

+			"Cortex A57 DDI (ARM DDI 0500D, revision r0p2)\n";

+		break;

+

 	case CPU_PPC64_PA6T:

 		event_doc =

 			"See PA6T Power Implementation Features Book IV\n"

-- 

1.9.3

From 76464b279cf20bb0bb40e758afb32eaf4195d861 Mon Sep 17 00:00:00 2001

From: Maynard Johnson <maynardj@us.ibm.com>

Date: Fri, 1 Aug 2014 09:06:17 -0500

Subject: [PATCH 1/2] Add another ARM internal mapping symbol to ignore

Ignore "$x" symbols, which can show up as internal

mapping symbols in binaries built on Aarch64.

Reported-byP: Andrew Haley <aph@redhat.com>

Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>

---

 libutil++/bfd_support.cpp | 3 ++-

 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/libutil++/bfd_support.cpp b/libutil++/bfd_support.cpp

index a3bee99..0554616 100644

--- a/libutil++/bfd_support.cpp

+++ b/libutil++/bfd_support.cpp

@@ -475,7 +475,8 @@ bool interesting_symbol(asymbol * sym)

 	/* ARM assembler internal mapping symbols aren't interesting */

 	if ((strcmp("$a", sym->name) == 0) ||

 	    (strcmp("$t", sym->name) == 0) ||

-	    (strcmp("$d", sym->name) == 0))

+	    (strcmp("$d", sym->name) == 0))||

+	    (strcmp("$x", sym->name) == 0))

 		return false;

 	// C++ exception stuff

-- 

1.9.3

From a4bdbc9ce94b15df3d19d60a11e4c4f2fc729cd9 Mon Sep 17 00:00:00 2001

From: Maynard Johnson <maynardj@us.ibm.com>

Date: Fri, 1 Aug 2014 09:25:55 -0500

Subject: [PATCH 2/2] Fix mis-placed parentheses in previous commit that caused

 build error

Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>

---

 libutil++/bfd_support.cpp | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libutil++/bfd_support.cpp b/libutil++/bfd_support.cpp

index 0554616..d5fd70d 100644

--- a/libutil++/bfd_support.cpp

+++ b/libutil++/bfd_support.cpp

@@ -475,7 +475,7 @@ bool interesting_symbol(asymbol * sym)

 	/* ARM assembler internal mapping symbols aren't interesting */

 	if ((strcmp("$a", sym->name) == 0) ||

 	    (strcmp("$t", sym->name) == 0) ||

-	    (strcmp("$d", sym->name) == 0))||

+	    (strcmp("$d", sym->name) == 0) ||

 	    (strcmp("$x", sym->name) == 0))

 		return false;

-- 

1.9.3