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From a89427d52a20633be40056fe008b7eeec5ded7dd Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Nicol=C3=A1s=20Ojeda=20B=C3=A4r?= <n.oje.bar@gmail.com>
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Date: Tue, 15 May 2018 07:17:06 +0000
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Subject: [PATCH 7/8] Adapt to 4.07
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---
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asmcomp/riscv/emit.mlp | 28 +++++++++++++++++-----------
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asmcomp/riscv/selection.ml | 2 +-
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2 files changed, 18 insertions(+), 12 deletions(-)
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diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
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index 51165d0f1..718dca080 100644
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--- a/asmcomp/riscv/emit.mlp
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+++ b/asmcomp/riscv/emit.mlp
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@@ -461,19 +461,25 @@ let emit_instr i =
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` {emit_string name} {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}, {emit_label lbl}\n`
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| Iinttest_imm _ ->
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fatal_error "Emit.emit_instr (Iinttest_imm _)"
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- | Ifloattest(cmp, neg) ->
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- let neg = match cmp with
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- | Ceq -> ` feq.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`; neg
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- | Cne -> ` feq.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`; not neg
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- | Clt -> ` flt.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`; neg
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- | Cgt -> ` flt.d {emit_reg reg_tmp1}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(0)}\n`; neg
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- | Cle -> ` fle.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`; neg
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- | Cge -> ` fle.d {emit_reg reg_tmp1}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(0)}\n`; neg
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- in
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- if neg then
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+ | Ifloattest cmp ->
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+ begin match cmp with
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+ | CFeq | CFneq ->
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+ ` feq.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
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+ | CFlt | CFnlt ->
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+ ` flt.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
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+ | CFgt | CFngt ->
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+ ` flt.d {emit_reg reg_tmp1}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(0)}\n`
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+ | CFle | CFnle ->
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+ ` fle.d {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
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+ | CFge | CFnge ->
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+ ` fle.d {emit_reg reg_tmp1}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(0)}\n`
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+ end;
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+ begin match cmp with
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+ | CFneq | CFnlt | CFngt | CFnle | CFnge ->
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` beqz {emit_reg reg_tmp1}, {emit_label lbl}\n`
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- else
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+ | CFeq | CFlt | CFgt | CFle | CFge ->
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` bnez {emit_reg reg_tmp1}, {emit_label lbl}\n`
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+ end
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| Ioddtest ->
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` andi {emit_reg reg_tmp1}, {emit_reg i.arg.(0)}, 1\n`;
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` bnez {emit_reg reg_tmp1}, {emit_label lbl}\n`
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diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
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index 092ca88aa..1f0af6abc 100644
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--- a/asmcomp/riscv/selection.ml
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+++ b/asmcomp/riscv/selection.ml
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@@ -61,7 +61,7 @@ method! select_condition = function
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| Cop(Ccmpa cmp, args, _) ->
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(Iinttest(Iunsigned cmp), Ctuple args)
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| Cop(Ccmpf cmp, args, _) ->
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- (Ifloattest(cmp, false), Ctuple args)
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+ (Ifloattest cmp, Ctuple args)
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| Cop(Cand, [arg; Cconst_int 1], _) ->
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(Ioddtest, arg)
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| arg ->
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--
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2.17.1
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