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@@ -0,0 +1,428 @@
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+ From c5d4db8ba7b2f3964f12bcde5d8fa5f27aa6c500 Mon Sep 17 00:00:00 2001
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+ From: Hiral Patel <patelhiral@fb.com>
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+ Date: Sat, 18 Feb 2023 01:03:11 -0800
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+ Subject: [PATCH 1/3] Added SPD decoding and dimm_slot_info CCI command support
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+
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+ ---
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+ cxl/builtin.h | 1 +
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+ cxl/cxl.c | 1 +
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+ cxl/lib/libcxl.c | 154 +++++++++++++++++++++++++++++++++++----------
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+ cxl/lib/libcxl.sym | 1 +
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+ cxl/libcxl.h | 1 +
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+ cxl/memdev.c | 24 +++++++
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+ 6 files changed, 149 insertions(+), 33 deletions(-)
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+
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+ diff --git a/cxl/builtin.h b/cxl/builtin.h
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+ index ca8be68..5775f4a 100644
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+ --- a/cxl/builtin.h
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+ +++ b/cxl/builtin.h
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+ @@ -115,4 +115,5 @@ int cmd_osa_misc_trig_cfg(int argc, const char **argv, struct cxl_ctx *ctx);
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+ int cmd_osa_data_read(int argc, const char **argv, struct cxl_ctx *ctx);
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+ int cmd_dimm_spd_read(int argc, const char **argv, struct cxl_ctx *ctx);
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+ int cmd_ddr_training_status(int argc, const char **argv, struct cxl_ctx *ctx);
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+ +int cmd_dimm_slot_info(int argc, const char **argv, struct cxl_ctx *ctx);
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+ #endif /* _CXL_BUILTIN_H_ */
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+ diff --git a/cxl/cxl.c b/cxl/cxl.c
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+ index e5b5732..4b430b5 100644
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+ --- a/cxl/cxl.c
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+ +++ b/cxl/cxl.c
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+ @@ -171,6 +171,7 @@ static struct cmd_struct commands[] = {
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+ { "osa-data-read", .c_fn = cmd_osa_data_read },
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+ { "dimm-spd-read", .c_fn = cmd_dimm_spd_read },
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+ { "ddr-training-status", .c_fn = cmd_ddr_training_status },
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+ + { "dimm-slot-info", .c_fn = cmd_dimm_slot_info },
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+ };
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+
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+ int main(int argc, const char **argv)
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+ diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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+ index cd9fcb5..a65f14a 100644
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+ --- a/cxl/lib/libcxl.c
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+ +++ b/cxl/lib/libcxl.c
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+ @@ -9646,6 +9646,26 @@ struct cxl_mbox_dimm_spd_read_in {
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+ __le32 num_bytes;
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+ } __attribute__((packed));
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+
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+ +#define SPD_MODULE_SERIAL_NUMBER_LEN (328 - 325 + 1) // 4 Bytes
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+ +
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+ +void static
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+ +IntToString (u8 *String, u8 *Integer, u8 SizeInByte) {
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+ + u8 Index;
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+ +
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+ + for (Index = 0; Index < SizeInByte; Index++) {
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+ + *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F;
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+ + *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F;
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+ + }
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+ + for (Index = 0; Index < (SizeInByte * 2); Index++) {
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+ + if (*(String + Index) >= 0x0A) {
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+ + *(String + Index) += 0x37;
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+ + } else {
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+ + *(String + Index) += 0x30;
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+ + }
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+ + }
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+ + *(String + SizeInByte * 2) = 0x0;
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+ +}
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+ +
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+ static char * decode_ddr4_module_type(u8 *bytes) {
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+ char *type;
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+ switch (bytes[3]) {
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+ @@ -9670,23 +9690,17 @@ static float ddr4_mtb_ftb_calc(unsigned char b1, signed char b2) {
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+ return b1 * mtb + b2 * ftb;
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+ }
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+
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+ -static void decode_ddr4_module_speed(u8 *bytes, float *ddr_clock, int *pc4_speed) {
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+ +static int decode_ddr4_module_speed(u8 *bytes) {
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+ float ctime;
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+ float ddrclk;
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+ - int tbits, pcclk;
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+
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+ ctime = ddr4_mtb_ftb_calc(bytes[18], bytes[125]);
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+ ddrclk = 2 * (1000 / ctime);
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+ - tbits = 8 << (bytes[13] & 7);
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+ -
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+ - pcclk = ddrclk * tbits / 8;
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+ - pcclk -= pcclk % 100;
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+
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+ - if (ddr_clock) { *ddr_clock = (int)ddrclk; }
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+ - if (pc4_speed) { *pc4_speed = pcclk; }
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+ + return ddrclk;
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+ }
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+
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+ -static double decode_ddr4_module_size(u8 *bytes) {
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+ +static int decode_ddr4_module_size(u8 *bytes) {
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+ double size;
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+ int sdrcap = 256 << (bytes[4] & 15);
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+ int buswidth = 8 << (bytes[13] & 7);
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+ @@ -9696,19 +9710,7 @@ static double decode_ddr4_module_size(u8 *bytes) {
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+
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+ if (signal_loading == 2) lranks_per_dimm *= ((bytes[6] >> 4) & 7) + 1;
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+ size = sdrcap / 8 * buswidth / sdrwidth * lranks_per_dimm;
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+ - return size;
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+ -}
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+ -
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+ -
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+ -static char * decode_ddr4_module_detail(u8 *bytes) {
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+ - char *type_detail = malloc(256);
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+ - float ddr_clock;
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+ - int pc4_speed;
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+ - if (type_detail) {
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+ - decode_ddr4_module_speed(bytes, &ddr_clock, &pc4_speed);
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+ - snprintf(type_detail, 255, "DDR4-%.0f (PC4-%d)", ddr_clock, pc4_speed);
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+ - }
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+ - return type_detail;
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+ + return (int) size/1024;
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+ }
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+
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+ static char * decode_ddr4_manufacturer(u8 *bytes){
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+ @@ -9729,7 +9731,7 @@ static char * decode_ddr4_manufacturer(u8 *bytes){
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+ manufacturer = NULL;
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+ return manufacturer;
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+ }
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+ - manufacturer = (char *) vendors[bank][index];
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+ + manufacturer = (char *) vendors[bank][index-1];
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+ return manufacturer;
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+ }
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+
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+ @@ -9776,8 +9778,8 @@ static int decode_ram_type(u8 *bytes) {
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+
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+ static const char *ram_types[] = {"Unknown", "Direct Rambus", "Rambus", "FPM DRAM",
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+ "EDO", "Pipelined Nibble", "SDR SDRAM", "Multiplexed ROM",
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+ - "DDR SGRAM", "DDR SDRAM", "DDR2 SDRAM", "DDR3 SDRAM",
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+ - "DDR4 SDRAM"};
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+ + "DDR SGRAM", "DDR SDRAM", "DDR2", "DDR3",
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+ + "DDR4"};
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+
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+ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
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+ u32 spd_id, u32 offset, u32 num_bytes)
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+ @@ -9787,7 +9789,9 @@ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
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+ struct cxl_command_info *cinfo;
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+ struct cxl_mbox_dimm_spd_read_in *dimm_spd_read_in;
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+ u8 *dimm_spd_read_out;
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+ + u8 serial[9];
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+ int rc = 0;
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+ + int buswidth;
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+ RamType ram_type;
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+
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+ cmd = cxl_cmd_new_raw(memdev, CXL_MEM_COMMAND_ID_DIMM_SPD_READ_OPCODE);
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+ @@ -9838,6 +9842,7 @@ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
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+
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+ dimm_spd_read_out = (u8*)cmd->send_cmd->out.payload;
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+ ram_type = decode_ram_type(dimm_spd_read_out);
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+ +
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+ fprintf(stdout, "=========================== DIMM SPD READ Data ============================\n");
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+ fprintf(stdout, "Output Payload:");
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+ for(int i=0; i<cmd->send_cmd->out.size; i++){
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+ @@ -9850,15 +9855,25 @@ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
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+ fprintf(stdout, "%02x ", dimm_spd_read_out[i]);
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+ }
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+ }
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+ +
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+ // Decoding SPD data for only DDR4 SDRAM.
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+ - if (ram_type == DDR4_SDRAM) {
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+ - fprintf(stdout, "\n\n");
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+ - fprintf(stdout, "DDR RAM Type: %s\n", ram_types[ram_type]);
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+ - fprintf(stdout, "DDR Module Type: %s\n", decode_ddr4_module_type(dimm_spd_read_out));
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+ - fprintf(stdout, "DDR Module Size: %1f\n", decode_ddr4_module_size(dimm_spd_read_out));
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+ - fprintf(stdout, "DDR Module Detail: %s\n", decode_ddr4_module_detail(dimm_spd_read_out));
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+ - fprintf(stdout, "DDR Manufacturer: %s\n", decode_ddr4_manufacturer(dimm_spd_read_out));
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+ - }
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+ +
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+ + buswidth = 8 << (dimm_spd_read_out[13] & 7);
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+ +
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+ + fprintf(stdout, "Total Width: %s\n", "TBD");
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+ + fprintf(stdout, "Data Width: %d bits\n", buswidth);
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+ + fprintf(stdout, "Size: %d GB\n", decode_ddr4_module_size(dimm_spd_read_out));
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+ + fprintf(stdout, "Form Factor: %s\n", "TBD");
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+ + fprintf(stdout, "Set: %s\n", "TBD");
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+ + fprintf(stdout, "Locator: %s\n", "DIMM_X");
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+ + fprintf(stdout, "Bank Locator: %s\n", "_Node1_ChannelX_DimmX");
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+ + fprintf(stdout, "Type: %s\n", ram_types[ram_type]);
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+ + fprintf(stdout, "Type Detail: %s\n", decode_ddr4_module_type(dimm_spd_read_out));
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+ + fprintf(stdout, "Speed: %d MT/s\n", decode_ddr4_module_speed(dimm_spd_read_out));
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+ + fprintf(stdout, "Manufacturer: %s\n", decode_ddr4_manufacturer(dimm_spd_read_out));
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+ + IntToString(serial, &dimm_spd_read_out[325], SPD_MODULE_SERIAL_NUMBER_LEN);
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+ + fprintf(stdout, "Serial Number: %s\n", serial);
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+ + fprintf(stdout, "Asset Tag: %s\n", "TBD");
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+
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+ out:
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+ cxl_cmd_unref(cmd);
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+ @@ -9946,3 +9961,76 @@ out:
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+ cxl_cmd_unref(cmd);
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+ return rc;
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+ }
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+ +
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+ +#define CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO CXL_MEM_COMMAND_ID_RAW
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+ +#define CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO_OPCODE 0xC520
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+ +#define CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO_PAYLOAD_IN_SIZE 0
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+ +
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+ +CXL_EXPORT int cxl_memdev_dimm_slot_info(struct cxl_memdev *memdev)
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+ +{
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+ + struct cxl_cmd *cmd;
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+ + struct cxl_mem_query_commands *query;
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+ + struct cxl_command_info *cinfo;
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+ + u8 *dimm_slot_info;
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+ + int rc = 0;
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+ + int offset = 0;
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+ +
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+ +
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+ + cmd = cxl_cmd_new_raw(memdev, CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO_OPCODE);
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+ + if (!cmd) {
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+ + fprintf(stderr, "%s: cxl_cmd_new_raw returned Null output\n",
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+ + cxl_memdev_get_devname(memdev));
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+ + return -ENOMEM;
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+ + }
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+ +
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+ + query = cmd->query_cmd;
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+ + cinfo = &query->commands[cmd->query_idx];
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+ +
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+ + cinfo->size_in = CXL_MEM_COMMAND_ID_LOG_INFO_PAYLOAD_IN_SIZE;
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+ + if (cinfo->size_in > 0) {
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+ + cmd->input_payload = calloc(1, cinfo->size_in);
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+ + if (!cmd->input_payload)
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+ + return -ENOMEM;
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+ + cmd->send_cmd->in.payload = (u64)cmd->input_payload;
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+ + cmd->send_cmd->in.size = cinfo->size_in;
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+ + }
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+ +
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+ + rc = cxl_cmd_submit(cmd);
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+ + if (rc < 0) {
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+ + fprintf(stderr, "%s: cmd submission failed: %d (%s)\n",
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+ + cxl_memdev_get_devname(memdev), rc, strerror(-rc));
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+ + goto out;
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+ + }
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+ +
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+ + rc = cxl_cmd_get_mbox_status(cmd);
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+ + if (rc != 0) {
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+ + fprintf(stderr, "%s: firmware status: %d:\n%s\n",
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+ + cxl_memdev_get_devname(memdev), rc, DEVICE_ERRORS[rc]);
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+ + rc = -ENXIO;
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+ + goto out;
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+ + }
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+ +
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+ + if (cmd->send_cmd->id != CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO) {
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+ + fprintf(stderr, "%s: invalid command id 0x%x (expecting 0x%x)\n",
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+ + cxl_memdev_get_devname(memdev), cmd->send_cmd->id, CXL_MEM_COMMAND_ID_DIMM_SLOT_INFO);
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+ + return -EINVAL;
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+ + }
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+ +
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+ + dimm_slot_info = (u8*)cmd->send_cmd->out.payload;
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+ + fprintf(stdout, "=========================== DIMM SLOT INFO ============================\n");
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+ + fprintf(stdout, "Output Payload:\n");
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+ + for(int i=0; i<cmd->send_cmd->out.size; i++){
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+ + if (i % 16 == 0)
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+ + {
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+ + fprintf(stdout, "\n%04x %02x ", i+offset, dimm_slot_info[i]);
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+ + }
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+ + else
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+ + {
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+ + fprintf(stdout, "%02x ", dimm_slot_info[i]);
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+ + }
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+ + }
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+ + fprintf(stdout, "\n");
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+ +out:
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+ + cxl_cmd_unref(cmd);
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+ + return rc;
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+ +}
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+ diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
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+ index e68bd89..aaf2d65 100644
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+ --- a/cxl/lib/libcxl.sym
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+ +++ b/cxl/lib/libcxl.sym
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+ @@ -168,4 +168,5 @@ global:
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+ cxl_memdev_osa_data_read;
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+ cxl_memdev_dimm_spd_read;
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+ cxl_memdev_ddr_training_status;
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+ + cxl_memdev_dimm_slot_info;
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+ } LIBCXL_3;
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+ diff --git a/cxl/libcxl.h b/cxl/libcxl.h
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+ index 498de7d..0c24579 100644
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+ --- a/cxl/libcxl.h
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+ +++ b/cxl/libcxl.h
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+ @@ -235,6 +235,7 @@ int cxl_memdev_osa_data_read(struct cxl_memdev *memdev, u8 cxl_mem_id,
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+ int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev, u32 spd_id,
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+ u32 offset, u32 num_bytes);
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+ int cxl_memdev_ddr_training_status(struct cxl_memdev *memdev);
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+ +int cxl_memdev_dimm_slot_info(struct cxl_memdev *memdev);
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+
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+ #define cxl_memdev_foreach(ctx, memdev) \
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+ for (memdev = cxl_memdev_get_first(ctx); \
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+ diff --git a/cxl/memdev.c b/cxl/memdev.c
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+ index d3a6f67..64ba7e0 100644
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+ --- a/cxl/memdev.c
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+ +++ b/cxl/memdev.c
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+ @@ -1895,6 +1895,11 @@ static const struct option cmd_ddr_training_status_options[] = {
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+ OPT_END(),
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+ };
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+
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+ +static const struct option cmd_dimm_slot_info_options[] = {
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+ + BASE_OPTIONS(),
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+ + OPT_END(),
|
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+ +};
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+ +
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+ static int action_cmd_clear_event_records(struct cxl_memdev *memdev, struct action_context *actx)
|
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+ {
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+ u16 record_handle;
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+ @@ -3438,6 +3443,17 @@ static int action_cmd_ddr_training_status(struct cxl_memdev *memdev, struct acti
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+ return cxl_memdev_ddr_training_status(memdev);
|
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+ }
|
| |
+
|
| |
+ +static int action_cmd_dimm_slot_info(struct cxl_memdev *memdev, struct action_context *actx)
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| |
+ +{
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| |
+ + if (cxl_memdev_is_active(memdev)) {
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+ + fprintf(stderr, "%s: memdev active, abort dimm_slot_info\n",
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| |
+ + cxl_memdev_get_devname(memdev));
|
| |
+ + return -EBUSY;
|
| |
+ + }
|
| |
+ +
|
| |
+ + return cxl_memdev_dimm_slot_info(memdev);
|
| |
+ +}
|
| |
+ +
|
| |
+ static int action_write(struct cxl_memdev *memdev, struct action_context *actx)
|
| |
+ {
|
| |
+ size_t size = param.len, read_len;
|
| |
+ @@ -4495,3 +4511,11 @@ int cmd_ddr_training_status(int argc, const char **argv, struct cxl_ctx *ctx)
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+
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+ return rc >= 0 ? 0 : EXIT_FAILURE;
|
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+ }
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+ +
|
| |
+ +int cmd_dimm_slot_info(int argc, const char **argv, struct cxl_ctx *ctx)
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| |
+ +{
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+ + int rc = memdev_action(argc, argv, ctx, action_cmd_dimm_slot_info, cmd_dimm_slot_info_options,
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| |
+ + "cxl ddr-slot-info <mem0> [<mem1>..<memN>] [<options>]");
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| |
+ +
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| |
+ + return rc >= 0 ? 0 : EXIT_FAILURE;
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+ +}
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+ --
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+ 2.39.2
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+
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+
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| |
+ From 86dc9d17c940b400bee7452121e64419e858cc8d Mon Sep 17 00:00:00 2001
|
| |
+ From: Hiral Patel <patelhiral@fb.com>
|
| |
+ Date: Sat, 18 Feb 2023 01:10:13 -0800
|
| |
+ Subject: [PATCH 2/3] fix stdout format
|
| |
+
|
| |
+ ---
|
| |
+ cxl/lib/libcxl.c | 1 +
|
| |
+ 1 file changed, 1 insertion(+)
|
| |
+
|
| |
+ diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
|
| |
+ index a65f14a..2a1b6f6 100644
|
| |
+ --- a/cxl/lib/libcxl.c
|
| |
+ +++ b/cxl/lib/libcxl.c
|
| |
+ @@ -9855,6 +9855,7 @@ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
|
| |
+ fprintf(stdout, "%02x ", dimm_spd_read_out[i]);
|
| |
+ }
|
| |
+ }
|
| |
+ + fprintf(stdout, "\n\n");
|
| |
+
|
| |
+ // Decoding SPD data for only DDR4 SDRAM.
|
| |
+
|
| |
+ --
|
| |
+ 2.39.2
|
| |
+
|
| |
+
|
| |
+ From 7fcbe3d7dc7eff5673baf2c55ec7f59e68a3bda6 Mon Sep 17 00:00:00 2001
|
| |
+ From: Panos Christeas <xrg@meta.com>
|
| |
+ Date: Mon, 20 Feb 2023 15:39:16 +0000
|
| |
+ Subject: [PATCH 3/3] add separator between SPD payload and decoding
|
| |
+
|
| |
+ Summary:
|
| |
+ Printing the SPD decoding would be on the same last line of hex payload,
|
| |
+ giving the parser a headache.
|
| |
+ Just add a separator
|
| |
+
|
| |
+ Test Plan:
|
| |
+ before:
|
| |
+ ```
|
| |
+ cxl dimm-spd-read mem0 -s 0 -o 0 -n 512
|
| |
+ =========================== DIMM SPD READ Data ============================
|
| |
+ Output Payload:
|
| |
+ 0000 23 11 0c 01 85 ...
|
| |
+ ...
|
| |
+ 01f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Total Width: TBD
|
| |
+ Data Width: 64 bits
|
| |
+ Size: ...
|
| |
+
|
| |
+ ```
|
| |
+
|
| |
+ After:
|
| |
+ ```
|
| |
+ ========================= DIMM SPD READ Data ============================
|
| |
+ Output Payload:
|
| |
+ 0000 23 11 0c 01 85 ...
|
| |
+ ...
|
| |
+ 01f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
| |
+
|
| |
+ ====== DIMM SPD DECODE ============
|
| |
+ Total Width: TBD
|
| |
+ Data Width: 64 bits
|
| |
+ Size: ...
|
| |
+ Form Factor: TBD
|
| |
+ Set: TBD
|
| |
+ Locator: ...
|
| |
+ ```
|
| |
+
|
| |
+ Reviewers:
|
| |
+
|
| |
+ Subscribers:
|
| |
+
|
| |
+ Tasks:
|
| |
+
|
| |
+ Tags:
|
| |
+ ---
|
| |
+ cxl/lib/libcxl.c | 1 +
|
| |
+ 1 file changed, 1 insertion(+)
|
| |
+
|
| |
+ diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
|
| |
+ index 2a1b6f6..8d39d2c 100644
|
| |
+ --- a/cxl/lib/libcxl.c
|
| |
+ +++ b/cxl/lib/libcxl.c
|
| |
+ @@ -9861,6 +9861,7 @@ CXL_EXPORT int cxl_memdev_dimm_spd_read(struct cxl_memdev *memdev,
|
| |
+
|
| |
+ buswidth = 8 << (dimm_spd_read_out[13] & 7);
|
| |
+
|
| |
+ + fprintf(stdout, "\n\n====== DIMM SPD DECODE ============\n");
|
| |
+ fprintf(stdout, "Total Width: %s\n", "TBD");
|
| |
+ fprintf(stdout, "Data Width: %d bits\n", buswidth);
|
| |
+ fprintf(stdout, "Size: %d GB\n", decode_ddr4_module_size(dimm_spd_read_out));
|
| |
+ --
|
| |
+ 2.39.2
|
| |
+
|
| |
