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From 2ceddb91d3a0d70a59242b3a9dab401be6e5c825 Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Fri, 5 Aug 2022 13:38:20 -0700
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Subject: [PATCH 205/217] cxl/list: Add 'depth' to port listings
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Simplify the task of determining how deep a port is in the hierarchy by
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just emitting what libcxl already counted. This is useful for validating
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interleave math.
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Link: https://lore.kernel.org/r/165973190022.1528532.6351628365510289908.stgit@dwillia2-xfh.jf.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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Documentation/cxl/lib/libcxl.txt | 1 +
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cxl/json.c | 4 ++++
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cxl/lib/libcxl.c | 5 +++++
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cxl/lib/libcxl.sym | 1 +
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cxl/libcxl.h | 1 +
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5 files changed, 12 insertions(+)
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diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
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index 6756d2f..fd2962a 100644
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--- a/Documentation/cxl/lib/libcxl.txt
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+++ b/Documentation/cxl/lib/libcxl.txt
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@@ -290,6 +290,7 @@ int cxl_port_is_enabled(struct cxl_port *port);
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bool cxl_port_is_root(struct cxl_port *port);
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bool cxl_port_is_switch(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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+int cxl_port_get_depth(struct cxl_port *port);
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bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
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int cxl_port_get_nr_dports(struct cxl_port *port);
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----
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diff --git a/cxl/json.c b/cxl/json.c
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index c3d9299..63c1751 100644
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--- a/cxl/json.c
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+++ b/cxl/json.c
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@@ -769,6 +769,10 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
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if (jobj)
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json_object_object_add(jport, "host", jobj);
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+ jobj = json_object_new_int(cxl_port_get_depth(port));
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+ if (jobj)
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+ json_object_object_add(jport, "depth", jobj);
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+
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if (!cxl_port_is_enabled(port)) {
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jobj = json_object_new_string("disabled");
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if (jobj)
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diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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index ff85b23..021d59f 100644
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--- a/cxl/lib/libcxl.c
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+++ b/cxl/lib/libcxl.c
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@@ -2417,6 +2417,11 @@ CXL_EXPORT bool cxl_port_is_endpoint(struct cxl_port *port)
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return port->type == CXL_PORT_ENDPOINT;
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}
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+CXL_EXPORT int cxl_port_get_depth(struct cxl_port *port)
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+{
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+ return port->depth;
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+}
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+
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CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port)
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{
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struct cxl_bus *bus;
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diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
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index 385a8f0..8bb91e0 100644
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--- a/cxl/lib/libcxl.sym
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+++ b/cxl/lib/libcxl.sym
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@@ -96,6 +96,7 @@ global:
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cxl_port_get_parent;
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cxl_port_is_root;
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cxl_port_is_switch;
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+ cxl_port_get_depth;
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cxl_port_to_bus;
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cxl_port_is_endpoint;
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cxl_port_to_endpoint;
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diff --git a/cxl/libcxl.h b/cxl/libcxl.h
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index 2498fa1..9fe4e99 100644
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--- a/cxl/libcxl.h
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+++ b/cxl/libcxl.h
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@@ -90,6 +90,7 @@ int cxl_port_is_enabled(struct cxl_port *port);
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struct cxl_port *cxl_port_get_parent(struct cxl_port *port);
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bool cxl_port_is_root(struct cxl_port *port);
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bool cxl_port_is_switch(struct cxl_port *port);
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+int cxl_port_get_depth(struct cxl_port *port);
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struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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struct cxl_endpoint *cxl_port_to_endpoint(struct cxl_port *port);
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--
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2.27.0
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