Blame SOURCES/0160-cxl-list-Auto-enable-single-mode-for-port-listings.patch
|
 |
26ccd9 |
From 2124f62aad2fcc00def36d119cfcdee22a7961e9 Mon Sep 17 00:00:00 2001
|
|
|
26ccd9 |
From: Dan Williams <dan.j.williams@intel.com>
|
|
|
26ccd9 |
Date: Thu, 28 Apr 2022 15:10:32 -0700
|
|
|
26ccd9 |
Subject: [PATCH 160/217] cxl/list: Auto-enable 'single' mode for port listings
|
|
|
26ccd9 |
|
|
|
26ccd9 |
The --single parameter instructs the filter code to gate listing of
|
|
|
26ccd9 |
ancestor ports. However, that behavior can be inferred by attempts to list
|
|
|
26ccd9 |
a port without the --ports option, i.e. make:
|
|
|
26ccd9 |
|
|
|
26ccd9 |
cxl list -p $port
|
|
|
26ccd9 |
|
|
|
26ccd9 |
...equivalent to:
|
|
|
26ccd9 |
|
|
|
26ccd9 |
cxl list -P -S -p $port
|
|
|
26ccd9 |
|
|
|
26ccd9 |
Link: https://lore.kernel.org/r/165118383246.1676208.2097194779584921177.stgit@dwillia2-desk3.amr.corp.intel.com
|
|
|
26ccd9 |
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
|
|
|
26ccd9 |
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
|
|
|
26ccd9 |
---
|
|
|
26ccd9 |
cxl/list.c | 1 +
|
|
|
26ccd9 |
1 file changed, 1 insertion(+)
|
|
|
26ccd9 |
|
|
|
26ccd9 |
diff --git a/cxl/list.c b/cxl/list.c
|
|
|
26ccd9 |
index 1e9d441..940782d 100644
|
|
|
26ccd9 |
--- a/cxl/list.c
|
|
|
26ccd9 |
+++ b/cxl/list.c
|
|
|
26ccd9 |
@@ -104,6 +104,7 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx)
|
|
|
26ccd9 |
error("please specify entities to list, e.g. using -m/-M\n");
|
|
|
26ccd9 |
usage_with_options(u, options);
|
|
|
26ccd9 |
}
|
|
|
26ccd9 |
+ param.single = true;
|
|
|
26ccd9 |
}
|
|
|
26ccd9 |
|
|
|
26ccd9 |
log_init(¶m.ctx, "cxl list", "CXL_LIST_LOG");
|
|
|
26ccd9 |
--
|
|
|
26ccd9 |
2.27.0
|
|
|
26ccd9 |
|