Blame SOURCES/openssl-1.0.2a-padlock64.patch

aa8173
diff -up openssl-1.0.2a/engines/e_padlock.c.padlock64 openssl-1.0.2a/engines/e_padlock.c
aa8173
--- openssl-1.0.2a/engines/e_padlock.c.padlock64	2015-03-19 14:19:00.000000000 +0100
aa8173
+++ openssl-1.0.2a/engines/e_padlock.c	2015-04-22 16:23:44.105617468 +0200
aa8173
@@ -101,7 +101,10 @@
aa8173
  */
aa8173
 #  undef COMPILE_HW_PADLOCK
aa8173
 #  if !defined(I386_ONLY) && !defined(OPENSSL_NO_INLINE_ASM)
aa8173
-#   if (defined(__GNUC__) && (defined(__i386__) || defined(__i386))) || \
aa8173
+#  if (defined(__GNUC__) && __GNUC__>=2 && \
aa8173
+       (defined(__i386__) || defined(__i386) || \
aa8173
+        defined(__x86_64__) || defined(__x86_64)) \
aa8173
+     ) || \
aa8173
      (defined(_MSC_VER) && defined(_M_IX86))
aa8173
 #    define COMPILE_HW_PADLOCK
aa8173
 #   endif
aa8173
@@ -140,7 +143,7 @@ void ENGINE_load_padlock(void)
aa8173
 #    endif
aa8173
 #   elif defined(__GNUC__)
aa8173
 #    ifndef alloca
aa8173
-#     define alloca(s) __builtin_alloca(s)
aa8173
+#     define alloca(s) __builtin_alloca((s))
aa8173
 #    endif
aa8173
 #   endif
aa8173
 
aa8173
@@ -303,6 +306,7 @@ static volatile struct padlock_cipher_da
aa8173
  * =======================================================
aa8173
  */
aa8173
 #   if defined(__GNUC__) && __GNUC__>=2
aa8173
+#    if defined(__i386__) || defined(__i386)
aa8173
 /*
aa8173
  * As for excessive "push %ebx"/"pop %ebx" found all over.
aa8173
  * When generating position-independent code GCC won't let
aa8173
@@ -379,22 +383,6 @@ static int padlock_available(void)
aa8173
     return padlock_use_ace + padlock_use_rng;
aa8173
 }
aa8173
 
aa8173
-#    ifndef OPENSSL_NO_AES
aa8173
-#     ifndef AES_ASM
aa8173
-/* Our own htonl()/ntohl() */
aa8173
-static inline void padlock_bswapl(AES_KEY *ks)
aa8173
-{
aa8173
-    size_t i = sizeof(ks->rd_key) / sizeof(ks->rd_key[0]);
aa8173
-    unsigned int *key = ks->rd_key;
aa8173
-
aa8173
-    while (i--) {
aa8173
-        asm volatile ("bswapl %0":"+r" (*key));
aa8173
-        key++;
aa8173
-    }
aa8173
-}
aa8173
-#     endif
aa8173
-#    endif
aa8173
-
aa8173
 /*
aa8173
  * Force key reload from memory to the CPU microcode. Loading EFLAGS from the
aa8173
  * stack clears EFLAGS[30] which does the trick.
aa8173
@@ -404,7 +392,7 @@ static inline void padlock_reload_key(vo
aa8173
     asm volatile ("pushfl; popfl");
aa8173
 }
aa8173
 
aa8173
-#    ifndef OPENSSL_NO_AES
aa8173
+#     ifndef OPENSSL_NO_AES
aa8173
 /*
aa8173
  * This is heuristic key context tracing. At first one
aa8173
  * believes that one should use atomic swap instructions,
aa8173
@@ -448,6 +436,101 @@ static inline void *name(size_t cnt,
aa8173
                 : "edx", "cc", "memory");       \
aa8173
         return iv;                              \
aa8173
 }
aa8173
+#     endif
aa8173
+
aa8173
+#    elif defined(__x86_64__) || defined(__x86_64)
aa8173
+
aa8173
+/* Load supported features of the CPU to see if
aa8173
+   the PadLock is available. */
aa8173
+static int padlock_available(void)
aa8173
+{
aa8173
+    char vendor_string[16];
aa8173
+    unsigned int eax, edx;
aa8173
+
aa8173
+    /* Are we running on the Centaur (VIA) CPU? */
aa8173
+    eax = 0x00000000;
aa8173
+    vendor_string[12] = 0;
aa8173
+    asm volatile ("cpuid\n"
aa8173
+                  "movl   %%ebx,(%1)\n"
aa8173
+                  "movl   %%edx,4(%1)\n"
aa8173
+                  "movl   %%ecx,8(%1)\n":"+a" (eax):"r"(vendor_string):"rbx",
aa8173
+                  "rcx", "rdx");
aa8173
+    if (strcmp(vendor_string, "CentaurHauls") != 0)
aa8173
+        return 0;
aa8173
+
aa8173
+    /* Check for Centaur Extended Feature Flags presence */
aa8173
+    eax = 0xC0000000;
aa8173
+    asm volatile ("cpuid":"+a" (eax)::"rbx", "rcx", "rdx");
aa8173
+    if (eax < 0xC0000001)
aa8173
+        return 0;
aa8173
+
aa8173
+    /* Read the Centaur Extended Feature Flags */
aa8173
+    eax = 0xC0000001;
aa8173
+    asm volatile ("cpuid":"+a" (eax), "=d"(edx)::"rbx", "rcx");
aa8173
+
aa8173
+    /* Fill up some flags */
aa8173
+    padlock_use_ace = ((edx & (0x3 << 6)) == (0x3 << 6));
aa8173
+    padlock_use_rng = ((edx & (0x3 << 2)) == (0x3 << 2));
aa8173
+
aa8173
+    return padlock_use_ace + padlock_use_rng;
aa8173
+}
aa8173
+
aa8173
+/* Force key reload from memory to the CPU microcode.
aa8173
+   Loading EFLAGS from the stack clears EFLAGS[30]
aa8173
+   which does the trick. */
aa8173
+static inline void padlock_reload_key(void)
aa8173
+{
aa8173
+    asm volatile ("pushfq; popfq");
aa8173
+}
aa8173
+
aa8173
+#     ifndef OPENSSL_NO_AES
aa8173
+/*
aa8173
+ * This is heuristic key context tracing. At first one
aa8173
+ * believes that one should use atomic swap instructions,
aa8173
+ * but it's not actually necessary. Point is that if
aa8173
+ * padlock_saved_context was changed by another thread
aa8173
+ * after we've read it and before we compare it with cdata,
aa8173
+ * our key *shall* be reloaded upon thread context switch
aa8173
+ * and we are therefore set in either case...
aa8173
+ */
aa8173
+static inline void padlock_verify_context(struct padlock_cipher_data *cdata)
aa8173
+{
aa8173
+    asm volatile ("pushfq\n"
aa8173
+                  "       btl     $30,(%%rsp)\n"
aa8173
+                  "       jnc     1f\n"
aa8173
+                  "       cmpq    %2,%1\n"
aa8173
+                  "       je      1f\n"
aa8173
+                  "       popfq\n"
aa8173
+                  "       subq    $8,%%rsp\n"
aa8173
+                  "1:     addq    $8,%%rsp\n"
aa8173
+                  "       movq    %2,%0":"+m" (padlock_saved_context)
aa8173
+                  :"r"(padlock_saved_context), "r"(cdata):"cc");
aa8173
+}
aa8173
+
aa8173
+/* Template for padlock_xcrypt_* modes */
aa8173
+/* BIG FAT WARNING:
aa8173
+ *      The offsets used with 'leal' instructions
aa8173
+ *      describe items of the 'padlock_cipher_data'
aa8173
+ *      structure.
aa8173
+ */
aa8173
+#      define PADLOCK_XCRYPT_ASM(name,rep_xcrypt)     \
aa8173
+static inline void *name(size_t cnt,            \
aa8173
+        struct padlock_cipher_data *cdata,      \
aa8173
+        void *out, const void *inp)             \
aa8173
+{       void *iv;                               \
aa8173
+        asm volatile ( "leaq    16(%0),%%rdx\n" \
aa8173
+                "       leaq    32(%0),%%rbx\n" \
aa8173
+                        rep_xcrypt "\n"         \
aa8173
+                : "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
aa8173
+                : "0"(cdata), "1"(cnt), "2"(out), "3"(inp)  \
aa8173
+                : "rbx", "rdx", "cc", "memory");        \
aa8173
+        return iv;                              \
aa8173
+}
aa8173
+#     endif
aa8173
+
aa8173
+#    endif                      /* cpu */
aa8173
+
aa8173
+#    ifndef OPENSSL_NO_AES
aa8173
 
aa8173
 /* Generate all functions with appropriate opcodes */
aa8173
 /* rep xcryptecb */
aa8173
@@ -458,6 +541,20 @@ PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb, "
aa8173
     PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb, ".byte 0xf3,0x0f,0xa7,0xe0")
aa8173
 /* rep xcryptofb */
aa8173
     PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb, ".byte 0xf3,0x0f,0xa7,0xe8")
aa8173
+
aa8173
+#     ifndef AES_ASM
aa8173
+/* Our own htonl()/ntohl() */
aa8173
+static inline void padlock_bswapl(AES_KEY *ks)
aa8173
+{
aa8173
+    size_t i = sizeof(ks->rd_key) / sizeof(ks->rd_key[0]);
aa8173
+    unsigned int *key = ks->rd_key;
aa8173
+
aa8173
+    while (i--) {
aa8173
+        asm volatile ("bswapl %0":"+r" (*key));
aa8173
+        key++;
aa8173
+    }
aa8173
+}
aa8173
+#     endif
aa8173
 #    endif
aa8173
 /* The RNG call itself */
aa8173
 static inline unsigned int padlock_xstore(void *addr, unsigned int edx_in)
aa8173
@@ -485,8 +582,8 @@ static inline unsigned int padlock_xstor
aa8173
 static inline unsigned char *padlock_memcpy(void *dst, const void *src,
aa8173
                                             size_t n)
aa8173
 {
aa8173
-    long *d = dst;
aa8173
-    const long *s = src;
aa8173
+    size_t *d = dst;
aa8173
+    const size_t *s = src;
aa8173
 
aa8173
     n /= sizeof(*d);
aa8173
     do {