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Some Intel Skylake CPU models (SKL-H/S/Xeon E3 v5, family 6, model 94,
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stepping 3) have reports of possible system hangs when revision 0xdc
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of microcode, that is included in microcode-20200609 update to address
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CVE-2020-0543, CVE-2020-0548, and CVE-2020-0549, is applied[1]. In order
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to address this, microcode update to the newer revision has been disabled
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by default on these systems, and the previously published microcode revision
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0xd6 is used by default for the OS-driven microcode update.
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31#issuecomment-644885826
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For the reference, SHA1 checksums of 06-5e-03 microcode files containing
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microcode revisions in question are listed below:
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* 06-5e-03, revision 0xd6: 86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a
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* 06-5e-03, revision 0xdc: 5e1020a10678cfc60980131c3d3a2cfd462b4dd7
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* 06-5e-03, revision 0xe2: 031e6e148b590d1c9cfdb6677539eeb4899e831c
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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required for mitigating specific side-channel cache attacks, please refer
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to the following knowledge base articles:
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* CVE-2017-5715 ("Spectre"):
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https://access.redhat.com/articles/3436091
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* CVE-2018-3639 ("Speculative Store Bypass"):
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https://access.redhat.com/articles/3540901
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* CVE-2018-3620, CVE-2018-3646 ("L1 Terminal Fault Attack"):
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https://access.redhat.com/articles/3562741
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* CVE-2018-12130, CVE-2018-12126, CVE-2018-12127, and CVE-2019-11091
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("Microarchitectural Data Sampling"):
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https://access.redhat.com/articles/4138151
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* CVE-2019-0117 (Intel SGX Information Leak),
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CVE-2019-0123 (Intel SGX Privilege Escalation),
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CVE-2019-11135 (TSX Asynchronous Abort),
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CVE-2019-11139 (Voltage Setting Modulation):
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https://access.redhat.com/solutions/2019-microcode-nov
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* CVE-2020-0543 (Special Register Buffer Data Sampling),
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding enforcing microcode update is provided below.
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To enforce usage of the latest 06-5e-03 microcode revision for a specific kernel
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version, please create a file "force-intel-06-5e-03" inside
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/lib/firmware/<kernel_version> directory, run
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"/usr/libexec/microcode_ctl/update_ucode" to add it to firmware directory
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where microcode will be available for late microcode update, and run
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"dracut -f --kver <kernel_version>", so initramfs for this kernel version
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is regenerated and the microcode can be loaded early, for example:
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touch /lib/firmware/3.10.0-862.9.1/force-intel-06-5e-03
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --kver 3.10.0-862.9.1
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After that, it is possible to perform a late microcode update by executing
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"/usr/libexec/microcode_ctl/reload_microcode" or by writing value "1" to
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"/sys/devices/system/cpu/microcode/reload" directly.
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To enforce addition of this microcode for all kernels, please create file
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"/etc/microcode_ctl/ucode_with_caveats/force-intel-06-5e-03", run
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"/usr/libexec/microcode_ctl/update_ucode" for enabling late microcode updates,
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and "dracut -f --regenerate-all" for enabling early microcode updates:
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mkdir -p /etc/microcode_ctl/ucode_with_caveats
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touch /etc/microcode_ctl/ucode_with_caveats/force-intel-06-5e-03
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --regenerate-all
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Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
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information.
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