|
 |
27aa66 |
Some Intel Skylake CPU models (SKL-U/Y, family 6, model 78, stepping 3)
|
|
|
27aa66 |
have reports of system hangs when revision 0xdc of microcode, that is included
|
|
|
27aa66 |
since microcode-20200609 update to address CVE-2020-0543, CVE-2020-0548,
|
|
|
27aa66 |
and CVE-2020-0549, is applied[1]. In order to address this, microcode update
|
|
|
27aa66 |
to the newer revision has been disabled by default on these systems,
|
|
|
27aa66 |
and the previously published microcode revision 0xd6 is used by default
|
|
|
27aa66 |
for the OS-driven microcode update.
|
|
|
27aa66 |
|
|
|
27aa66 |
[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31
|
|
|
27aa66 |
|
|
|
da1320 |
For the reference, SHA1 checksums of 06-4e-03 microcode files containing
|
|
|
27aa66 |
microcode revisions in question are listed below:
|
|
|
27aa66 |
* 06-4e-03, revision 0xd6: 06432a25053c823b0e2a6b8e84e2e2023ee3d43e
|
|
|
27aa66 |
* 06-4e-03, revision 0xdc: cd1733458d187486999337ff8b51eeaa0cfbca6c
|
|
|
da1320 |
* 06-4e-03, revision 0xe2: 41f4513cf563605bc85db38056ac430dec948366
|
|
|
2c8f3d |
* 06-4e-03, revision 0xea: 5a54cab9f22f69b819d663e5747ed6ea2a326c55
|
|
|
79687e |
* 06-4e-03, revision 0xec: d949a8543d2464d955f5dc4b0777cac863f48729
|
|
|
d205e1 |
* 06-4e-03, revision 0xf0: 37475bac70457ba8df2c1a32bba81bd7bd27d5e8
|
|
|
27aa66 |
|
|
|
27aa66 |
Please contact your system vendor for a BIOS/firmware update that contains
|
|
|
27aa66 |
the latest microcode version. For the information regarding microcode versions
|
|
|
27aa66 |
required for mitigating specific side-channel cache attacks, please refer
|
|
|
27aa66 |
to the following knowledge base articles:
|
|
|
27aa66 |
* CVE-2017-5715 ("Spectre"):
|
|
|
27aa66 |
https://access.redhat.com/articles/3436091
|
|
|
27aa66 |
* CVE-2018-3639 ("Speculative Store Bypass"):
|
|
|
27aa66 |
https://access.redhat.com/articles/3540901
|
|
|
27aa66 |
* CVE-2018-3620, CVE-2018-3646 ("L1 Terminal Fault Attack"):
|
|
|
27aa66 |
https://access.redhat.com/articles/3562741
|
|
|
27aa66 |
* CVE-2018-12130, CVE-2018-12126, CVE-2018-12127, and CVE-2019-11091
|
|
|
27aa66 |
("Microarchitectural Data Sampling"):
|
|
|
27aa66 |
https://access.redhat.com/articles/4138151
|
|
|
27aa66 |
* CVE-2019-0117 (Intel SGX Information Leak),
|
|
|
27aa66 |
CVE-2019-0123 (Intel SGX Privilege Escalation),
|
|
|
27aa66 |
CVE-2019-11135 (TSX Asynchronous Abort),
|
|
|
27aa66 |
CVE-2019-11139 (Voltage Setting Modulation):
|
|
|
27aa66 |
https://access.redhat.com/solutions/2019-microcode-nov
|
|
|
27aa66 |
* CVE-2020-0543 (Special Register Buffer Data Sampling),
|
|
|
27aa66 |
CVE-2020-0548 (Vector Register Data Sampling),
|
|
|
27aa66 |
CVE-2020-0549 (L1D Cache Eviction Sampling):
|
|
|
27aa66 |
https://access.redhat.com/solutions/5142751
|
|
|
3bf6c4 |
* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
|
|
|
3bf6c4 |
CVE-2020-8696 (Vector Register Leakage-Active),
|
|
|
3bf6c4 |
CVE-2020-8698 (Fast Forward Store Predictor):
|
|
|
3bf6c4 |
https://access.redhat.com/articles/5569051
|
|
|
b9f9de |
* CVE-2020-24489 (VT-d-related Privilege Escalation),
|
|
|
b9f9de |
CVE-2020-24511 (Improper Isolation of Shared Resources),
|
|
|
b9f9de |
CVE-2020-24512 (Observable Timing Discrepancy),
|
|
|
b9f9de |
CVE-2020-24513 (Information Disclosure on Some Intel Atom Processors):
|
|
|
b9f9de |
https://access.redhat.com/articles/6101171
|
|
|
79687e |
* CVE-2021-0127 (Intel Processor Breakpoint Control Flow):
|
|
|
79687e |
https://access.redhat.com/articles/6716541
|
|
|
d205e1 |
* CVE-2022-0005 (Informational disclosure via JTAG),
|
|
|
d205e1 |
CVE-2022-21123 (Shared Buffers Data Read),
|
|
|
d205e1 |
CVE-2022-21125 (Shared Buffers Data Sampling),
|
|
|
d205e1 |
CVE-2022-21127 (Update to Special Register Buffer Data Sampling),
|
|
|
d205e1 |
CVE-2022-21151 (Optimization Removal-Induced Informational Disclosure),
|
|
|
d205e1 |
CVE-2022-21166 (Device Register Partial Write):
|
|
|
d205e1 |
https://access.redhat.com/articles/6963124
|
|
|
27aa66 |
|
|
|
27aa66 |
The information regarding enforcing microcode update is provided below.
|
|
|
27aa66 |
|
|
|
27aa66 |
To enforce usage of the latest 06-4e-03 microcode revision for a specific kernel
|
|
|
27aa66 |
version, please create a file "force-intel-06-4e-03" inside
|
|
|
27aa66 |
/lib/firmware/<kernel_version> directory, run
|
|
|
27aa66 |
"/usr/libexec/microcode_ctl/update_ucode" to add it to firmware directory
|
|
|
27aa66 |
where microcode will be available for late microcode update, and run
|
|
|
27aa66 |
"dracut -f --kver <kernel_version>", so initramfs for this kernel version
|
|
|
27aa66 |
is regenerated and the microcode can be loaded early, for example:
|
|
|
27aa66 |
|
|
|
27aa66 |
touch /lib/firmware/3.10.0-862.9.1/force-intel-06-4e-03
|
|
|
27aa66 |
/usr/libexec/microcode_ctl/update_ucode
|
|
|
27aa66 |
dracut -f --kver 3.10.0-862.9.1
|
|
|
27aa66 |
|
|
|
27aa66 |
After that, it is possible to perform a late microcode update by executing
|
|
|
27aa66 |
"/usr/libexec/microcode_ctl/reload_microcode" or by writing value "1" to
|
|
|
27aa66 |
"/sys/devices/system/cpu/microcode/reload" directly.
|
|
|
27aa66 |
|
|
|
27aa66 |
To enforce addition of this microcode for all kernels, please create file
|
|
|
27aa66 |
"/etc/microcode_ctl/ucode_with_caveats/force-intel-06-4e-03", run
|
|
|
27aa66 |
"/usr/libexec/microcode_ctl/update_ucode" for enabling late microcode updates,
|
|
|
27aa66 |
and "dracut -f --regenerate-all" for enabling early microcode updates:
|
|
|
27aa66 |
|
|
|
27aa66 |
mkdir -p /etc/microcode_ctl/ucode_with_caveats
|
|
|
27aa66 |
touch /etc/microcode_ctl/ucode_with_caveats/force-intel-06-4e-03
|
|
|
27aa66 |
/usr/libexec/microcode_ctl/update_ucode
|
|
|
27aa66 |
dracut -f --regenerate-all
|
|
|
27aa66 |
|
|
|
27aa66 |
Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
|
|
|
27aa66 |
information.
|