|
 |
f3c512 |
Intel Sandy Bridge-E/EN/EP CPU models (SNB-EP, family 6, model 45, stepping 7)
|
|
|
f3c512 |
have issues with MDS-related microcode update that may lead to a system hang
|
|
|
f3c512 |
after a microcode update. In order to address this, microcode update
|
|
|
ee041c |
to the MDS-related revision 0x718 has been disabled, and the previously
|
|
|
ee041c |
published microcode revision 0x714 is used by default for the OS-driven
|
|
|
ee041c |
microcode update.
|
|
|
ee041c |
|
|
|
ee041c |
For the reference, SHA1 checksums of 06-2d-07 microcode files containing
|
|
|
ee041c |
microcode revisions in question are listed below:
|
|
|
ee041c |
* 06-2d-07, revision 0x714: bcf2173cd3dd499c37defbc2533703cfa6ec2430
|
|
|
ee041c |
* 06-2d-07, revision 0x718: 837cfebbfc09b911151dfd179082ad99cf87e85d
|
|
|
ee041c |
|
|
|
ee041c |
Please contact your system vendor for a BIOS/firmware update that contains
|
|
|
ee041c |
the latest microcode version. For the information regarding microcode versions
|
|
|
ee041c |
required for mitigating specific side-channel cache attacks, please refer
|
|
|
ee041c |
to the following knowledge base articles:
|
|
|
ee041c |
* CVE-2017-5715 ("Spectre"):
|
|
|
ee041c |
https://access.redhat.com/articles/3436091
|
|
|
ee041c |
* CVE-2018-3639 ("Speculative Store Bypass"):
|
|
|
ee041c |
https://access.redhat.com/articles/3540901
|
|
|
ee041c |
* CVE-2018-3620, CVE-2018-3646 ("L1 Terminal Fault Attack"):
|
|
|
ee041c |
https://access.redhat.com/articles/3562741
|
|
|
ee041c |
* CVE-2018-12130, CVE-2018-12126, CVE-2018-12127, and CVE-2019-11091
|
|
|
ee041c |
("Microarchitectural Data Sampling"):
|
|
|
ee041c |
https://access.redhat.com/articles/4138151
|
|
|
ee041c |
|
|
|
ee041c |
The information regarding enforcing microcode load is provided below.
|
|
|
ee041c |
|
|
|
f3c512 |
To enforce usage of the 0x718 microcode revision for a specific kernel version,
|
|
|
f3c512 |
please create file "force-intel-06-2d-07" inside /lib/firmware/<kernel_version>
|
|
|
f3c512 |
directory, run "/usr/libexec/microcode_ctl/update_ucode" to add it to firmware
|
|
|
ee041c |
directory where microcode will be available for late microcode update,
|
|
|
f3c512 |
and run "dracut -f --kver <kernel_version>", so initramfs for this kernel
|
|
|
f3c512 |
version is regenerated and the microcode can be loaded early, for example:
|
|
|
ee041c |
|
|
|
ee041c |
touch /lib/firmware/3.10.0-862.9.1/force-intel-06-2d-07
|
|
|
ee041c |
/usr/libexec/microcode_ctl/update_ucode
|
|
|
ee041c |
dracut -f --kver 3.10.0-862.9.1
|
|
|
ee041c |
|
|
|
ee041c |
After that, it is possible to perform a late microcode update by executing
|
|
|
ee041c |
"/usr/libexec/microcode_ctl/reload_microcode" or by writing value "1" to
|
|
|
ee041c |
"/sys/devices/system/cpu/microcode/reload" directly.
|
|
|
ee041c |
|
|
|
f3c512 |
To enforce addition of this microcode for all kernels, please create file
|
|
|
ee041c |
"/etc/microcode_ctl/ucode_with_caveats/force-intel-06-2d-07", run
|
|
|
ee041c |
"/usr/libexec/microcode_ctl/update_ucode" for enabling late microcode updates,
|
|
|
ee041c |
and "dracut -f --regenerate-all" for enabling early microcode updates:
|
|
|
ee041c |
|
|
|
ee041c |
mkdir -p /etc/microcode_ctl/ucode_with_caveats
|
|
|
ee041c |
touch /etc/microcode_ctl/ucode_with_caveats/force-intel-06-2d-07
|
|
|
ee041c |
/usr/libexec/microcode_ctl/update_ucode
|
|
|
ee041c |
dracut -f --regenerate-all
|
|
|
ee041c |
|
|
|
ee041c |
Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
|
|
|
ee041c |
information.
|