From ea7bf3941eeef8320c711a6f66b5e73077cc6e6b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 29 Jun 2020 07:40:13 +1000 Subject: [PATCH] gallivm/nir: fix const loading on big endian systems The code was expecting the lower 32-bits of the 64-bit to be what it wanted, don't be implicit, pull the value from the union. This should fix rendering on big endian systems since NIR was introduced. Fixes: 44a6b0107b37 ("gallivm: add nir->llvm translation (v2)") Reviewed-by: Timothy Arceri --- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index 9aa582a0e8a..f14475e839d 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -865,7 +865,7 @@ static void visit_load_const(struct lp_build_nir_context *bld_base, LLVMValueRef result[NIR_MAX_VEC_COMPONENTS]; struct lp_build_context *int_bld = get_int_bld(bld_base, true, instr->def.bit_size); for (unsigned i = 0; i < instr->def.num_components; i++) - result[i] = lp_build_const_int_vec(bld_base->base.gallivm, int_bld->type, instr->value[i].u64); + result[i] = lp_build_const_int_vec(bld_base->base.gallivm, int_bld->type, instr->def.bit_size == 32 ? instr->value[i].u32 : instr->value[i].u64); assign_ssa_dest(bld_base, &instr->def, result); } -- 2.26.2