diff --git a/SOURCES/0001-dri-add-another-get-shm-variant.patch b/SOURCES/0001-dri-add-another-get-shm-variant.patch new file mode 100644 index 0000000..2d3cc3b --- /dev/null +++ b/SOURCES/0001-dri-add-another-get-shm-variant.patch @@ -0,0 +1,77 @@ +From 7881d29f2c729e4a8a5af21a0abcf3db18e22918 Mon Sep 17 00:00:00 2001 +From: Dave Airlie +Date: Fri, 14 Feb 2020 15:00:13 +1000 +Subject: [PATCH 1/2] dri: add another get shm variant. + +When Brian in 02c3dad0f3b4d26e0faa5cc51d06bc50d693dcdc restricted +the shm permissions it means we hit the fallback paths in some +scenarios we hadn't before. + +When you use Xephyr to xdmcp from one user to another the new perms +stop the X server (running as user a) attaching to the SHM segments +from gnome-shell (running as user b). + +In this case however only the GLX side of the code had insight into this, +and the dri could was meant of fall back, and it worked for put image +fine but the get image path was broken, since there was no indication +in the broken case of the need to fallback. + +This adds a return type to a new interface member that lets the +caller know it has to fallback. + +Fixes: 02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777") +--- + include/GL/internal/dri_interface.h | 15 ++++++++++++++- + src/gallium/state_trackers/dri/drisw.c | 3 +++ + 2 files changed, 17 insertions(+), 1 deletion(-) + +diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h +index 09782c8baeb..e40106575c0 100644 +--- a/include/GL/internal/dri_interface.h ++++ b/include/GL/internal/dri_interface.h +@@ -634,7 +634,7 @@ struct __DRIdamageExtensionRec { + * SWRast Loader extension. + */ + #define __DRI_SWRAST_LOADER "DRI_SWRastLoader" +-#define __DRI_SWRAST_LOADER_VERSION 5 ++#define __DRI_SWRAST_LOADER_VERSION 6 + struct __DRIswrastLoaderExtensionRec { + __DRIextension base; + +@@ -711,6 +711,19 @@ struct __DRIswrastLoaderExtensionRec { + int width, int height, int stride, + int shmid, char *shmaddr, unsigned offset, + void *loaderPrivate); ++ ++ /** ++ * get shm image to drawable (v2) ++ * ++ * There are some cases where GLX can't use SHM, but DRI ++ * still tries, we need to get a return type for when to ++ * fallback to the non-shm path. ++ * ++ * \since 6 ++ */ ++ GLboolean (*getImageShm2)(__DRIdrawable *readable, ++ int x, int y, int width, int height, ++ int shmid, void *loaderPrivate); + }; + + /** +diff --git a/src/gallium/state_trackers/dri/drisw.c b/src/gallium/state_trackers/dri/drisw.c +index e3fb3f1b925..df364c47391 100644 +--- a/src/gallium/state_trackers/dri/drisw.c ++++ b/src/gallium/state_trackers/dri/drisw.c +@@ -138,6 +138,9 @@ get_image_shm(__DRIdrawable *dPriv, int x, int y, int width, int height, + if (!res->screen->resource_get_handle(res->screen, NULL, res, &whandle, PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE)) + return FALSE; + ++ if (loader->base.version > 5 && loader->getImageShm2) ++ return loader->getImageShm2(dPriv, x, y, width, height, whandle.handle, dPriv->loaderPrivate); ++ + loader->getImageShm(dPriv, x, y, width, height, whandle.handle, dPriv->loaderPrivate); + return TRUE; + } +-- +2.21.1 + diff --git a/SOURCES/0001-i965-initialize-bo_reuse-when-creating-brw_bufmgr.patch b/SOURCES/0001-i965-initialize-bo_reuse-when-creating-brw_bufmgr.patch new file mode 100644 index 0000000..d394037 --- /dev/null +++ b/SOURCES/0001-i965-initialize-bo_reuse-when-creating-brw_bufmgr.patch @@ -0,0 +1,154 @@ +From 453530d58df83fac6f7191f56e75ddb00ec855d7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Tapani=20P=C3=A4lli?= +Date: Wed, 28 Aug 2019 14:29:53 +0300 +Subject: [PATCH 1/3] i965: initialize bo_reuse when creating brw_bufmgr +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Fixes a possible data race spotted while debugging on other EGL +related failures where glFinish and eglCreateContext are going on at +the same time: + + ==11558== Possible data race during read of size 1 at 0x5E78CD0 by thread #23 + ==11558== Locks held: 1, at address 0x5E77CA8 + ==11558== at 0x61B71D4: bo_alloc_internal (brw_bufmgr.c:639) + ==11558== by 0x61B7328: brw_bo_alloc (brw_bufmgr.c:669) + ==11558== by 0x61EF975: recreate_growing_buffer (intel_batchbuffer.c:231) + ==11558== by 0x61EFAAE: intel_batchbuffer_reset (intel_batchbuffer.c:255) + ==11558== by 0x61EFB85: intel_batchbuffer_reset_and_clear_render_cache (intel_batchbuffer.c:280) + ==11558== by 0x61F0507: brw_new_batch (intel_batchbuffer.c:551) + ==11558== by 0x61F12C1: _intel_batchbuffer_flush_fence (intel_batchbuffer.c:888) + ==11558== by 0x61BDD6B: intel_glFlush (brw_context.c:296) + ==11558== by 0x61BDDB9: intel_finish (brw_context.c:307) + ==11558== by 0x623831B: _mesa_Finish (context.c:1906) + ==11558== by 0x46D556: deqp::egl::GLES2ThreadTest::Operation::execute(tcu::ThreadUtil::Thread&) + ==11558== by 0x721502: tcu::ThreadUtil::Thread::run() + ==11558== + ==11558== This conflicts with a previous write of size 1 by thread #26 + ==11558== Locks held: 1, at address 0x5D09878 + ==11558== at 0x61B98A9: brw_bufmgr_enable_reuse (brw_bufmgr.c:1541) + ==11558== by 0x61BF09D: brw_process_driconf_options (brw_context.c:854) + ==11558== by 0x61BF6CA: brwCreateContext (brw_context.c:993) + ==11558== by 0x621181F: driCreateContextAttribs (dri_util.c:473) + ==11558== by 0x53FE87B: dri2_create_context (egl_dri2.c:1388) + ==11558== by 0x53EE7BE: eglCreateContext (eglapi.c:807) + ==11558== by 0x5C8AB9: eglw::FuncPtrLibrary::createContext(void*, void*, void*, int const*) const + ==11558== by 0x46E027: deqp::egl::GLES2ThreadTest::CreateContext::exec(tcu::ThreadUtil::Thread&) + +Signed-off-by: Tapani Pälli +Reviewed-by: Lionel Landwerlin +Reviewed-by: Kenneth Graunke +(cherry picked from commit b65de51dcf7d5e6d1a6ccdb5121c385f5360de00) +--- + src/mesa/drivers/dri/i965/brw_bufmgr.c | 16 ++-------------- + src/mesa/drivers/dri/i965/brw_bufmgr.h | 4 ++-- + src/mesa/drivers/dri/i965/brw_context.c | 9 --------- + src/mesa/drivers/dri/i965/intel_screen.c | 12 +++++++++++- + 4 files changed, 15 insertions(+), 26 deletions(-) + +diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c +index f1675b191c1..e676fbd9d18 100644 +--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c ++++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c +@@ -1529,19 +1529,6 @@ brw_bo_flink(struct brw_bo *bo, uint32_t *name) + return 0; + } + +-/** +- * Enables unlimited caching of buffer objects for reuse. +- * +- * This is potentially very memory expensive, as the cache at each bucket +- * size is only bounded by how many buffers of that size we've managed to have +- * in flight at once. +- */ +-void +-brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr) +-{ +- bufmgr->bo_reuse = true; +-} +- + static void + add_bucket(struct brw_bufmgr *bufmgr, int size) + { +@@ -1684,7 +1671,7 @@ brw_using_softpin(struct brw_bufmgr *bufmgr) + * \param fd File descriptor of the opened DRM device. + */ + struct brw_bufmgr * +-brw_bufmgr_init(struct gen_device_info *devinfo, int fd) ++brw_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) + { + struct brw_bufmgr *bufmgr; + +@@ -1714,6 +1701,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd) + + bufmgr->has_llc = devinfo->has_llc; + bufmgr->has_mmap_wc = gem_param(fd, I915_PARAM_MMAP_VERSION) > 0; ++ bufmgr->bo_reuse = bo_reuse; + + const uint64_t _4GB = 4ull << 30; + +diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h +index 32fc7a553c9..a85c8f37bef 100644 +--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h ++++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h +@@ -343,11 +343,11 @@ int brw_bo_busy(struct brw_bo *bo); + int brw_bo_madvise(struct brw_bo *bo, int madv); + + /* drm_bacon_bufmgr_gem.c */ +-struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd); ++struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd, ++ bool bo_reuse); + struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr, + const char *name, + unsigned int handle); +-void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr); + + int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns); + +diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c +index 6ba64e4e06d..6d218e49754 100644 +--- a/src/mesa/drivers/dri/i965/brw_context.c ++++ b/src/mesa/drivers/dri/i965/brw_context.c +@@ -822,15 +822,6 @@ brw_process_driconf_options(struct brw_context *brw) + brw->driContext->driScreenPriv->myNum, + "i965", NULL); + +- int bo_reuse_mode = driQueryOptioni(options, "bo_reuse"); +- switch (bo_reuse_mode) { +- case DRI_CONF_BO_REUSE_DISABLED: +- break; +- case DRI_CONF_BO_REUSE_ALL: +- brw_bufmgr_enable_reuse(brw->bufmgr); +- break; +- } +- + if (INTEL_DEBUG & DEBUG_NO_HIZ) { + brw->has_hiz = false; + /* On gen6, you can only do separate stencil with HIZ. */ +diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c +index c3bd30f7837..1feaf18219c 100644 +--- a/src/mesa/drivers/dri/i965/intel_screen.c ++++ b/src/mesa/drivers/dri/i965/intel_screen.c +@@ -1870,7 +1870,17 @@ intel_init_bufmgr(struct intel_screen *screen) + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; + +- screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd); ++ bool bo_reuse = false; ++ int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse"); ++ switch (bo_reuse_mode) { ++ case DRI_CONF_BO_REUSE_DISABLED: ++ break; ++ case DRI_CONF_BO_REUSE_ALL: ++ bo_reuse = true; ++ break; ++ } ++ ++ screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd, bo_reuse); + if (screen->bufmgr == NULL) { + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); +-- +2.23.0 + diff --git a/SOURCES/0001-llvmpipe-use-ppc64le-ppc64-Large-code-model-for-JIT-.patch b/SOURCES/0001-llvmpipe-use-ppc64le-ppc64-Large-code-model-for-JIT-.patch new file mode 100644 index 0000000..fed6d53 --- /dev/null +++ b/SOURCES/0001-llvmpipe-use-ppc64le-ppc64-Large-code-model-for-JIT-.patch @@ -0,0 +1,71 @@ +From d0ff02e567541468309923fed2320da6cbd81779 Mon Sep 17 00:00:00 2001 +From: Ben Crocker +Date: Thu, 21 Nov 2019 17:33:31 -0500 +Subject: [PATCH] llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled + shaders + +Large programs, e.g. gnome-shell and firefox, may tax the +addressability of the Medium code model once a (potentially unbounded) +number of dynamically generated JIT-compiled shader programs are +linked in and relocated. Yet the default code model as of LLVM 8 is +Medium or even Small. + +The cost of changing from Medium to Large is negligible: +- an additional 8-byte pointer stored immediately before the shader entrypoint; +- change an add-immediate (addis) instruction to a load (ld). + +Testing with WebGL Conformance +(https://www.khronos.org/registry/webgl/sdk/tests/webgl-conformance-tests.html) +yields clean runs with this change (and crashes without it). + +Testing with glxgears shows no detectable performance difference. + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1753327, 1543572, 1747110, and 1582226 + +Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/223 + +Co-authored by: Nemanja Ivanovic , Tom Stellard + +CC: mesa-stable@lists.freedesktop.org + +Signed-off-by: Ben Crocker +Reviewed-by: Adam Jackson +--- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -686,7 +686,19 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + * when not using MCJIT so no instructions are generated which the old JIT + * can't handle. Not entirely sure if we really need to do anything yet. + */ +-#if defined(PIPE_ARCH_LITTLE_ENDIAN) && defined(PIPE_ARCH_PPC_64) ++#ifdef PIPE_ARCH_PPC_64 ++ /* ++ * Large programs, e.g. gnome-shell and firefox, may tax the addressability ++ * of the Medium code model once dynamically generated JIT-compiled shader ++ * programs are linked in and relocated. Yet the default code model as of ++ * LLVM 8 is Medium or even Small. ++ * The cost of changing from Medium to Large is negligible: ++ * - an additional 8-byte pointer stored immediately before the shader entrypoint; ++ * - change an add-immediate (addis) instruction to a load (ld). ++ */ ++ builder.setCodeModel(CodeModel::Large); ++ ++#ifdef PIPE_ARCH_LITTLE_ENDIAN + /* + * Versions of LLVM prior to 4.0 lacked a table entry for "POWER8NVL", + * resulting in (big-endian) "generic" being returned on +@@ -698,6 +710,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + */ + if (MCPU == "generic") + MCPU = "pwr8"; ++#endif + #endif + builder.setMCPU(MCPU); + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +-- +2.21.0 + diff --git a/SOURCES/0002-glx-add-getImageShm2-path.patch b/SOURCES/0002-glx-add-getImageShm2-path.patch new file mode 100644 index 0000000..d8062b3 --- /dev/null +++ b/SOURCES/0002-glx-add-getImageShm2-path.patch @@ -0,0 +1,77 @@ +From 74e4f90deeae466ed19d2a31d8f62f6fc5e1709b Mon Sep 17 00:00:00 2001 +From: Dave Airlie +Date: Fri, 14 Feb 2020 15:03:24 +1000 +Subject: [PATCH 2/2] glx: add getImageShm2 path + +If the glx side shmid is -1 (because the X server failed to attach) +then we should let the caller know to fallback. + +Fixes: 02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777") +--- + src/glx/drisw_glx.c | 25 +++++++++++++++++++------ + 1 file changed, 19 insertions(+), 6 deletions(-) + +diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c +index 069f64d5216..dfa3218d759 100644 +--- a/src/glx/drisw_glx.c ++++ b/src/glx/drisw_glx.c +@@ -288,10 +288,10 @@ swrastGetImage(__DRIdrawable * read, + swrastGetImage2(read, x, y, w, h, 0, data, loaderPrivate); + } + +-static void +-swrastGetImageShm(__DRIdrawable * read, +- int x, int y, int w, int h, +- int shmid, void *loaderPrivate) ++static GLboolean ++swrastGetImageShm2(__DRIdrawable * read, ++ int x, int y, int w, int h, ++ int shmid, void *loaderPrivate) + { + struct drisw_drawable *prp = loaderPrivate; + __GLXDRIdrawable *pread = &(prp->base); +@@ -301,8 +301,11 @@ swrastGetImageShm(__DRIdrawable * read, + + if (!prp->ximage || shmid != prp->shminfo.shmid) { + if (!XCreateDrawable(prp, shmid, dpy)) +- return; ++ return GL_FALSE; + } ++ ++ if (prp->shminfo.shmid == -1) ++ return GL_FALSE; + readable = pread->xDrawable; + + ximage = prp->ximage; +@@ -312,10 +315,19 @@ swrastGetImageShm(__DRIdrawable * read, + ximage->bytes_per_line = bytes_per_line(w * ximage->bits_per_pixel, 32); + + XShmGetImage(dpy, readable, ximage, x, y, ~0L); ++ return GL_TRUE; ++} ++ ++static void ++swrastGetImageShm(__DRIdrawable * read, ++ int x, int y, int w, int h, ++ int shmid, void *loaderPrivate) ++{ ++ swrastGetImageShm2(read, x, y, w, h, shmid, loaderPrivate); + } + + static const __DRIswrastLoaderExtension swrastLoaderExtension_shm = { +- .base = {__DRI_SWRAST_LOADER, 5 }, ++ .base = {__DRI_SWRAST_LOADER, 6 }, + + .getDrawableInfo = swrastGetDrawableInfo, + .putImage = swrastPutImage, +@@ -325,6 +337,7 @@ static const __DRIswrastLoaderExtension swrastLoaderExtension_shm = { + .putImageShm = swrastPutImageShm, + .getImageShm = swrastGetImageShm, + .putImageShm2 = swrastPutImageShm2, ++ .getImageShm2 = swrastGetImageShm2, + }; + + static const __DRIextension *loader_extensions_shm[] = { +-- +2.21.1 + diff --git a/SOURCES/0002-i965-store-DRM-fd-on-intel_screen.patch b/SOURCES/0002-i965-store-DRM-fd-on-intel_screen.patch new file mode 100644 index 0000000..dc78f7e --- /dev/null +++ b/SOURCES/0002-i965-store-DRM-fd-on-intel_screen.patch @@ -0,0 +1,307 @@ +From 649c8ed3f369aa11e3bdbb4784b61d2e6000cb6a Mon Sep 17 00:00:00 2001 +From: Lionel Landwerlin +Date: Fri, 6 Mar 2020 16:56:25 +0200 +Subject: [PATCH 2/3] i965: store DRM fd on intel_screen + +v2: Fix storing of drm fd (Ajax) + +[mustard: backport to 18.3.4 - ajax] + +Signed-off-by: Lionel Landwerlin +(cherry picked from commit b9d3d93769a96d973e379673e712a11b408f7712) +--- + .../drivers/dri/i965/brw_performance_query.c | 27 +++++++------------ + src/mesa/drivers/dri/i965/brw_reset.c | 6 ++--- + src/mesa/drivers/dri/i965/intel_batchbuffer.c | 6 ++--- + src/mesa/drivers/dri/i965/intel_screen.c | 14 +++++----- + src/mesa/drivers/dri/i965/intel_screen.h | 3 +++ + 5 files changed, 22 insertions(+), 34 deletions(-) + +diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c +index 10e3d024f17..703c79c4f97 100644 +--- a/src/mesa/drivers/dri/i965/brw_performance_query.c ++++ b/src/mesa/drivers/dri/i965/brw_performance_query.c +@@ -1103,7 +1103,6 @@ brw_begin_perf_query(struct gl_context *ctx, + + /* If the OA counters aren't already on, enable them. */ + if (brw->perfquery.oa_stream_fd == -1) { +- __DRIscreen *screen = brw->screen->driScrnPriv; + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + /* The period_exponent gives a sampling period as follows: +@@ -1163,7 +1162,7 @@ brw_begin_perf_query(struct gl_context *ctx, + metric_id, + query->oa_format, + period_exponent, +- screen->fd, /* drm fd */ ++ brw->screen->fd, /* drm fd */ + brw->hw_ctx)) + return false; + } else { +@@ -1847,8 +1846,6 @@ enumerate_sysfs_metrics(struct brw_context *brw) + static bool + kernel_has_dynamic_config_support(struct brw_context *brw) + { +- __DRIscreen *screen = brw->screen->driScrnPriv; +- + hash_table_foreach(brw->perfquery.oa_metrics_table, entry) { + struct brw_perf_query_info *query = entry->data; + char config_path[280]; +@@ -1859,7 +1856,7 @@ kernel_has_dynamic_config_support(struct brw_context *brw) + + /* Look for the test config, which we know we can't replace. */ + if (read_file_uint64(config_path, &config_id) && config_id == 1) { +- return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, ++ return drmIoctl(brw->screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, + &config_id) < 0 && errno == ENOENT; + } + } +@@ -1870,8 +1867,6 @@ kernel_has_dynamic_config_support(struct brw_context *brw) + static void + init_oa_configs(struct brw_context *brw) + { +- __DRIscreen *screen = brw->screen->driScrnPriv; +- + hash_table_foreach(brw->perfquery.oa_metrics_table, entry) { + const struct brw_perf_query_info *query = entry->data; + struct drm_i915_perf_oa_config config; +@@ -1902,7 +1897,7 @@ init_oa_configs(struct brw_context *brw) + config.n_flex_regs = query->n_flex_regs; + config.flex_regs_ptr = (uintptr_t) query->flex_regs; + +- ret = drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); ++ ret = drmIoctl(brw->screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &config); + if (ret < 0) { + DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n", + query->name, query->guid, strerror(errno)); +@@ -1917,7 +1912,6 @@ init_oa_configs(struct brw_context *brw) + static bool + query_topology(struct brw_context *brw) + { +- __DRIscreen *screen = brw->screen->driScrnPriv; + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_TOPOLOGY_INFO, + }; +@@ -1926,14 +1920,14 @@ query_topology(struct brw_context *brw) + .items_ptr = (uintptr_t) &item, + }; + +- if (drmIoctl(screen->fd, DRM_IOCTL_I915_QUERY, &query)) ++ if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_QUERY, &query)) + return false; + + struct drm_i915_query_topology_info *topo_info = + (struct drm_i915_query_topology_info *) calloc(1, item.length); + item.data_ptr = (uintptr_t) topo_info; + +- if (drmIoctl(screen->fd, DRM_IOCTL_I915_QUERY, &query) || ++ if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_QUERY, &query) || + item.length <= 0) + return false; + +@@ -1948,21 +1942,20 @@ query_topology(struct brw_context *brw) + static bool + getparam_topology(struct brw_context *brw) + { +- __DRIscreen *screen = brw->screen->driScrnPriv; + drm_i915_getparam_t gp; + int ret; + + int slice_mask = 0; + gp.param = I915_PARAM_SLICE_MASK; + gp.value = &slice_mask; +- ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp); ++ ret = drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) + return false; + + int subslice_mask = 0; + gp.param = I915_PARAM_SUBSLICE_MASK; + gp.value = &subslice_mask; +- ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp); ++ ret = drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) + return false; + +@@ -2013,7 +2006,6 @@ init_oa_sys_vars(struct brw_context *brw) + { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + uint64_t min_freq_mhz = 0, max_freq_mhz = 0; +- __DRIscreen *screen = brw->screen->driScrnPriv; + + if (!read_sysfs_drm_device_file_uint64(brw, "gt_min_freq_mhz", &min_freq_mhz)) + return false; +@@ -2041,7 +2033,7 @@ init_oa_sys_vars(struct brw_context *brw) + brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 1000000; + brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 1000000; + brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency; +- brw->perfquery.sys_vars.revision = intel_device_get_revision(screen->fd); ++ brw->perfquery.sys_vars.revision = intel_device_get_revision(brw->screen->fd); + compute_topology_builtins(brw); + + return true; +@@ -2050,7 +2042,6 @@ init_oa_sys_vars(struct brw_context *brw) + static bool + get_sysfs_dev_dir(struct brw_context *brw) + { +- __DRIscreen *screen = brw->screen->driScrnPriv; + struct stat sb; + int min, maj; + DIR *drmdir; +@@ -2059,7 +2050,7 @@ get_sysfs_dev_dir(struct brw_context *brw) + + brw->perfquery.sysfs_dev_dir[0] = '\0'; + +- if (fstat(screen->fd, &sb)) { ++ if (fstat(brw->screen->fd, &sb)) { + DBG("Failed to stat DRM fd\n"); + return false; + } +diff --git a/src/mesa/drivers/dri/i965/brw_reset.c b/src/mesa/drivers/dri/i965/brw_reset.c +index ad8c44f2d1c..90518780eb8 100644 +--- a/src/mesa/drivers/dri/i965/brw_reset.c ++++ b/src/mesa/drivers/dri/i965/brw_reset.c +@@ -35,7 +35,6 @@ GLenum + brw_get_graphics_reset_status(struct gl_context *ctx) + { + struct brw_context *brw = brw_context(ctx); +- __DRIscreen *dri_screen = brw->screen->driScrnPriv; + struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx }; + + /* If hardware contexts are not being used (or +@@ -51,7 +50,7 @@ brw_get_graphics_reset_status(struct gl_context *ctx) + if (brw->reset_count != 0) + return GL_NO_ERROR; + +- if (drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0) ++ if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0) + return GL_NO_ERROR; + + /* A reset was observed while a batch from this context was executing. +@@ -77,10 +76,9 @@ brw_get_graphics_reset_status(struct gl_context *ctx) + void + brw_check_for_reset(struct brw_context *brw) + { +- __DRIscreen *dri_screen = brw->screen->driScrnPriv; + struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx }; + +- if (drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0) ++ if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0) + return; + + if (stats.batch_active > 0 || stats.batch_pending > 0) +diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c +index 6207de5a06f..7237e51ab5a 100644 +--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c ++++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c +@@ -683,8 +683,7 @@ throttle(struct brw_context *brw) + } + + if (brw->need_flush_throttle) { +- __DRIscreen *dri_screen = brw->screen->driScrnPriv; +- drmCommandNone(dri_screen->fd, DRM_I915_GEM_THROTTLE); ++ drmCommandNone(brw->screen->fd, DRM_I915_GEM_THROTTLE); + brw->need_flush_throttle = false; + } + } +@@ -749,7 +748,6 @@ execbuffer(int fd, + static int + submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) + { +- __DRIscreen *dri_screen = brw->screen->driScrnPriv; + struct intel_batchbuffer *batch = &brw->batch; + int ret = 0; + +@@ -816,7 +814,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd) + batch->exec_bos[index] = tmp_bo; + } + +- ret = execbuffer(dri_screen->fd, batch, brw->hw_ctx, ++ ret = execbuffer(brw->screen->fd, batch, brw->hw_ctx, + 4 * USED_BATCH(*batch), + in_fence_fd, out_fence_fd, flags); + +diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c +index 1feaf18219c..3e02c11700c 100644 +--- a/src/mesa/drivers/dri/i965/intel_screen.c ++++ b/src/mesa/drivers/dri/i965/intel_screen.c +@@ -1636,7 +1636,7 @@ intel_get_param(struct intel_screen *screen, int param, int *value) + gp.param = param; + gp.value = value; + +- if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { ++ if (drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { + ret = -errno; + if (ret != -EINVAL) + _mesa_warning(NULL, "drm_i915_getparam: %d", ret); +@@ -1865,8 +1865,6 @@ err_out: + static bool + intel_init_bufmgr(struct intel_screen *screen) + { +- __DRIscreen *dri_screen = screen->driScrnPriv; +- + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; + +@@ -1880,7 +1878,7 @@ intel_init_bufmgr(struct intel_screen *screen) + break; + } + +- screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd, bo_reuse); ++ screen->bufmgr = brw_bufmgr_init(&screen->devinfo, screen->fd, bo_reuse); + if (screen->bufmgr == NULL) { + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); +@@ -2038,8 +2036,7 @@ intel_detect_pipelined_register(struct intel_screen *screen, + /* Don't bother with error checking - if the execbuf fails, the + * value won't be written and we'll just report that there's no access. + */ +- __DRIscreen *dri_screen = screen->driScrnPriv; +- drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); ++ drmIoctl(screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); + + /* Check whether the value got written. */ + void *results_map = brw_bo_map(NULL, results, MAP_READ); +@@ -2475,6 +2472,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) + screen->driScrnPriv = dri_screen; + dri_screen->driverPrivate = (void *) screen; + ++ screen->fd = dri_screen->fd; + screen->deviceID = gen_get_pci_device_id_override(); + if (screen->deviceID < 0) + screen->deviceID = intel_get_integer(screen, I915_PARAM_CHIPSET_ID); +@@ -2531,7 +2529,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) + screen->max_gtt_map_object_size = gtt_size / 4; + } + +- screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4; ++ screen->aperture_threshold = get_aperture_size(screen->fd) * 3 / 4; + + screen->hw_has_swizzling = intel_detect_swizzling(screen); + screen->hw_has_timestamp = intel_detect_timestamp(screen); +@@ -2720,7 +2718,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) + struct drm_i915_reset_stats stats; + memset(&stats, 0, sizeof(stats)); + +- const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); ++ const int ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); + + screen->has_context_reset_notification = + (ret != -1 || errno != EINVAL); +diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h +index 8d56fcd9e7a..6145afd56c5 100644 +--- a/src/mesa/drivers/dri/i965/intel_screen.h ++++ b/src/mesa/drivers/dri/i965/intel_screen.h +@@ -56,6 +56,9 @@ struct intel_screen + /** Bytes of aperture usage beyond which execbuf is likely to fail. */ + uint64_t aperture_threshold; + ++ /** DRM fd associated with this screen. Not owned by this object. Do not close. */ ++ int fd; ++ + bool no_hw; + bool hw_has_swizzling; + bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */ +-- +2.23.0 + diff --git a/SOURCES/0003-i965-share-buffer-managers-across-screens.patch b/SOURCES/0003-i965-share-buffer-managers-across-screens.patch new file mode 100644 index 0000000..5b3c074 --- /dev/null +++ b/SOURCES/0003-i965-share-buffer-managers-across-screens.patch @@ -0,0 +1,239 @@ +From f2ccb19e3e15a04fda47f8b0fcb08e32903031a1 Mon Sep 17 00:00:00 2001 +From: Lionel Landwerlin +Date: Fri, 6 Mar 2020 17:06:25 +0200 +Subject: [PATCH 3/3] i965: share buffer managers across screens + +Signed-off-by: Lionel Landwerlin +--- + src/mesa/drivers/dri/i965/brw_bufmgr.c | 84 ++++++++++++++++++++++-- + src/mesa/drivers/dri/i965/brw_bufmgr.h | 11 ++-- + src/mesa/drivers/dri/i965/intel_screen.c | 7 +- + 3 files changed, 92 insertions(+), 10 deletions(-) + +diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c +index e676fbd9d18..32758f2b9ff 100644 +--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c ++++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c +@@ -139,6 +139,10 @@ struct bo_cache_bucket { + }; + + struct brw_bufmgr { ++ uint32_t refcount; ++ ++ struct list_head link; ++ + int fd; + + mtx_t lock; +@@ -160,6 +164,12 @@ struct brw_bufmgr { + uint64_t initial_kflags; + }; + ++static mtx_t global_bufmgr_list_mutex = _MTX_INITIALIZER_NP; ++static struct list_head global_bufmgr_list = { ++ .next = &global_bufmgr_list, ++ .prev = &global_bufmgr_list, ++}; ++ + static int bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode, + uint32_t stride); + +@@ -1292,8 +1302,19 @@ brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns) + } + + void +-brw_bufmgr_destroy(struct brw_bufmgr *bufmgr) ++brw_bufmgr_unref(struct brw_bufmgr *bufmgr) + { ++ mtx_lock(&global_bufmgr_list_mutex); ++ if (p_atomic_dec_zero(&bufmgr->refcount)) { ++ list_del(&bufmgr->link); ++ } else { ++ bufmgr = NULL; ++ } ++ mtx_unlock(&global_bufmgr_list_mutex); ++ ++ if (!bufmgr) ++ return; ++ + mtx_destroy(&bufmgr->lock); + + /* Free any cached buffer objects we were going to reuse */ +@@ -1322,6 +1343,9 @@ brw_bufmgr_destroy(struct brw_bufmgr *bufmgr) + } + } + ++ close(bufmgr->fd); ++ bufmgr->fd = -1; ++ + free(bufmgr); + } + +@@ -1664,14 +1688,21 @@ brw_using_softpin(struct brw_bufmgr *bufmgr) + return bufmgr->initial_kflags & EXEC_OBJECT_PINNED; + } + ++static struct brw_bufmgr * ++brw_bufmgr_ref(struct brw_bufmgr *bufmgr) ++{ ++ p_atomic_inc(&bufmgr->refcount); ++ return bufmgr; ++} ++ + /** + * Initializes the GEM buffer manager, which uses the kernel to allocate, map, + * and manage map buffer objections. + * + * \param fd File descriptor of the opened DRM device. + */ +-struct brw_bufmgr * +-brw_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) ++static struct brw_bufmgr * ++brw_bufmgr_create(struct gen_device_info *devinfo, int fd, bool bo_reuse) + { + struct brw_bufmgr *bufmgr; + +@@ -1688,9 +1719,16 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) + * Don't do this! Ensure that each library/bufmgr has its own device + * fd so that its namespace does not clash with another. + */ +- bufmgr->fd = fd; ++ bufmgr->fd = dup(fd); ++ if (bufmgr->fd < 0) { ++ free(bufmgr); ++ return NULL; ++ } ++ ++ p_atomic_set(&bufmgr->refcount, 1); + + if (mtx_init(&bufmgr->lock, mtx_plain) != 0) { ++ close(bufmgr->fd); + free(bufmgr); + return NULL; + } +@@ -1725,6 +1763,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) + * might actually mean requiring 4.14. + */ + fprintf(stderr, "i965 requires softpin (Kernel 4.5) on Gen10+."); ++ close(bufmgr->fd); + free(bufmgr); + return NULL; + } +@@ -1739,3 +1778,40 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd, bool bo_reuse) + + return bufmgr; + } ++ ++struct brw_bufmgr * ++brw_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd, bool bo_reuse) ++{ ++ struct stat st; ++ ++ if (fstat(fd, &st)) ++ return NULL; ++ ++ struct brw_bufmgr *bufmgr = NULL; ++ ++ mtx_lock(&global_bufmgr_list_mutex); ++ list_for_each_entry(struct brw_bufmgr, iter_bufmgr, &global_bufmgr_list, link) { ++ struct stat iter_st; ++ if (fstat(iter_bufmgr->fd, &iter_st)) ++ continue; ++ ++ if (st.st_rdev == iter_st.st_rdev) { ++ bufmgr = brw_bufmgr_ref(iter_bufmgr); ++ goto unlock; ++ } ++ } ++ ++ bufmgr = brw_bufmgr_create(devinfo, fd, bo_reuse); ++ list_addtail(&bufmgr->link, &global_bufmgr_list); ++ ++ unlock: ++ mtx_unlock(&global_bufmgr_list_mutex); ++ ++ return bufmgr; ++} ++ ++int ++brw_bufmgr_get_fd(struct brw_bufmgr *bufmgr) ++{ ++ return bufmgr->fd; ++} +diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h +index a85c8f37bef..3d8729da487 100644 +--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h ++++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h +@@ -300,9 +300,9 @@ int brw_bo_subdata(struct brw_bo *bo, uint64_t offset, + void brw_bo_wait_rendering(struct brw_bo *bo); + + /** +- * Tears down the buffer manager instance. ++ * Unref a buffer manager instance. + */ +-void brw_bufmgr_destroy(struct brw_bufmgr *bufmgr); ++void brw_bufmgr_unref(struct brw_bufmgr *bufmgr); + + /** + * Get the current tiling (and resulting swizzling) mode for the bo. +@@ -343,8 +343,9 @@ int brw_bo_busy(struct brw_bo *bo); + int brw_bo_madvise(struct brw_bo *bo, int madv); + + /* drm_bacon_bufmgr_gem.c */ +-struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd, +- bool bo_reuse); ++struct brw_bufmgr *brw_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd, ++ bool bo_reuse); ++ + struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr, + const char *name, + unsigned int handle); +@@ -359,6 +360,8 @@ int brw_hw_context_set_priority(struct brw_bufmgr *bufmgr, + + void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id); + ++int brw_bufmgr_get_fd(struct brw_bufmgr *bufmgr); ++ + int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd); + struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, + int prime_fd); +diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c +index 3e02c11700c..c374837c4a1 100644 +--- a/src/mesa/drivers/dri/i965/intel_screen.c ++++ b/src/mesa/drivers/dri/i965/intel_screen.c +@@ -1668,7 +1668,7 @@ intelDestroyScreen(__DRIscreen * sPriv) + { + struct intel_screen *screen = sPriv->driverPrivate; + +- brw_bufmgr_destroy(screen->bufmgr); ++ brw_bufmgr_unref(screen->bufmgr); + driDestroyOptionInfo(&screen->optionCache); + + disk_cache_destroy(screen->disk_cache); +@@ -1865,6 +1865,8 @@ err_out: + static bool + intel_init_bufmgr(struct intel_screen *screen) + { ++ __DRIscreen *dri_screen = screen->driScrnPriv; ++ + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; + +@@ -1878,12 +1880,13 @@ intel_init_bufmgr(struct intel_screen *screen) + break; + } + +- screen->bufmgr = brw_bufmgr_init(&screen->devinfo, screen->fd, bo_reuse); ++ screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse); + if (screen->bufmgr == NULL) { + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); + return false; + } ++ screen->fd = brw_bufmgr_get_fd(screen->bufmgr); + + if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) { + fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__); +-- +2.23.0 + diff --git a/SOURCES/dri-shm-fix-put-image.patch b/SOURCES/dri-shm-fix-put-image.patch new file mode 100644 index 0000000..8d90146 --- /dev/null +++ b/SOURCES/dri-shm-fix-put-image.patch @@ -0,0 +1,12 @@ +diff -up mesa-18.3.4/src/glx/drisw_glx.c.dma mesa-18.3.4/src/glx/drisw_glx.c +--- mesa-18.3.4/src/glx/drisw_glx.c.dma 2020-03-13 09:53:49.347674709 +1000 ++++ mesa-18.3.4/src/glx/drisw_glx.c 2020-03-13 09:54:23.704608060 +1000 +@@ -241,7 +241,7 @@ swrastXPutImage(__DRIdrawable * draw, in + XShmPutImage(dpy, drawable, gc, ximage, srcx, srcy, x, y, w, h, False); + XSync(dpy, False); + } else { +- ximage->width = w; ++ ximage->width = ximage->bytes_per_line / ((ximage->bits_per_pixel + 7)/ 8); + ximage->height = h; + XPutImage(dpy, drawable, gc, ximage, srcx, srcy, x, y, w, h); + } diff --git a/SPECS/mesa.spec b/SPECS/mesa.spec index 104b3a5..6abd17f 100644 --- a/SPECS/mesa.spec +++ b/SPECS/mesa.spec @@ -61,7 +61,7 @@ Summary: Mesa graphics libraries Name: mesa Version: 18.3.4 -Release: 5%{?dist} +Release: 9%{?dist} License: MIT Group: System Environment/Libraries URL: http://www.mesa3d.org @@ -86,12 +86,22 @@ Patch3: fix-timeout-warnings.patch Patch4: 0001-glx-fix-shared-memory-leak-in-X11.patch # fix remove shm Patch5: fix-llvmpipe-remote-shm.patch +Patch6: dri-shm-fix-put-image.patch +Patch7: 0001-dri-add-another-get-shm-variant.patch +Patch8: 0002-glx-add-getImageShm2-path.patch Patch12: mesa-8.0.1-fix-16bpp.patch Patch15: mesa-9.2-hardware-float.patch Patch20: mesa-10.2-evergreen-big-endian.patch Patch21: 0001-pkgconfig-Fix-gl.pc-when-glvnd-is-enabled.patch +Patch31: 0001-llvmpipe-use-ppc64le-ppc64-Large-code-model-for-JIT-.patch + +# i965 multi-screen fix +Patch40: 0001-i965-initialize-bo_reuse-when-creating-brw_bufmgr.patch +Patch41: 0002-i965-store-DRM-fd-on-intel_screen.patch +Patch42: 0003-i965-share-buffer-managers-across-screens.patch + BuildRequires: pkgconfig autoconf automake libtool %if %{with_hardware} BuildRequires: kernel-headers @@ -342,12 +352,19 @@ grep -q ^/ src/gallium/auxiliary/vl/vl_decoder.c && exit 1 %patch3 -p1 -b .timeout %patch4 -p1 -b .shmleak %patch5 -p1 -b .shmremote +%patch6 -p1 -b .shmputfix +%patch7 -p1 -b .shmget1 +%patch8 -p1 -b .shmget2 #patch12 -p1 -b .16bpp %patch15 -p1 -b .hwfloat #patch20 -p1 -b .egbe #%patch21 -p1 -b .glpc +%patch31 -p1 -b .codemodel +%patch40 -p1 -b .multi965.1 +%patch41 -p1 -b .multi965.2 +%patch42 -p1 -b .multi965.3 %if 0%{with_private_llvm} sed -i 's/\[llvm-config\]/\[llvm-private-config-%{__isa_bits}\]/g' configure.ac @@ -664,6 +681,18 @@ rm -rf $RPM_BUILD_ROOT %endif %changelog +* Mon Apr 20 2020 Adam Jackson - 18.3.4-9 +- Fix context sharing with multiple screens for i965 + +* Fri Mar 13 2020 Dave Airlie - 18.3.4-8 +- Backport put/get shm fixes to EL7 (#1749699) + +* Thu Jan 23 2020 Tomas Pelka - 18.3.4-7 +- bump version and rebuild to avoind conflict with 7.7.z build (#1543572) + +* Mon Jan 06 2020 Ben Crocker - 18.3.4-6 +- Patch to require Large CodeModel for llvmpipe on ppc64/ppc64le (#1543572) + * Thu Apr 04 2019 Dave Airlie - 18.3.4-5 - fix remote shm patch