Blame SOURCES/mesa-20.3.3-stable-fixes.patch

0d69a5
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
0d69a5
index d49bc0f0564..90512d4f276 100644
0d69a5
--- a/src/amd/vulkan/radv_query.c
0d69a5
+++ b/src/amd/vulkan/radv_query.c
0d69a5
@@ -1679,13 +1679,14 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
0d69a5
 
0d69a5
 			va += 8 * idx;
0d69a5
 
0d69a5
-			si_cs_emit_write_event_eop(cs,
0d69a5
-						   cmd_buffer->device->physical_device->rad_info.chip_class,
0d69a5
-						   radv_cmd_buffer_uses_mec(cmd_buffer),
0d69a5
-						   V_028A90_PS_DONE, 0,
0d69a5
-						   EOP_DST_SEL_TC_L2,
0d69a5
-						   EOP_DATA_SEL_GDS,
0d69a5
-						   va, EOP_DATA_GDS(0, 1), 0);
0d69a5
+			radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
0d69a5
+			radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) |
0d69a5
+					COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
0d69a5
+					COPY_DATA_WR_CONFIRM);
0d69a5
+			radeon_emit(cs, 0);
0d69a5
+			radeon_emit(cs, 0);
0d69a5
+			radeon_emit(cs, va);
0d69a5
+			radeon_emit(cs, va >> 32);
0d69a5
 
0d69a5
 			/* Record that the command buffer needs GDS. */
0d69a5
 			cmd_buffer->gds_needed = true;
0d69a5
@@ -1769,13 +1770,14 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
0d69a5
 
0d69a5
 			va += 8 * idx;
0d69a5
 
0d69a5
-			si_cs_emit_write_event_eop(cs,
0d69a5
-						   cmd_buffer->device->physical_device->rad_info.chip_class,
0d69a5
-						   radv_cmd_buffer_uses_mec(cmd_buffer),
0d69a5
-						   V_028A90_PS_DONE, 0,
0d69a5
-						   EOP_DST_SEL_TC_L2,
0d69a5
-						   EOP_DATA_SEL_GDS,
0d69a5
-						   va, EOP_DATA_GDS(0, 1), 0);
0d69a5
+			radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
0d69a5
+			radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) |
0d69a5
+					COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
0d69a5
+					COPY_DATA_WR_CONFIRM);
0d69a5
+			radeon_emit(cs, 0);
0d69a5
+			radeon_emit(cs, 0);
0d69a5
+			radeon_emit(cs, va);
0d69a5
+			radeon_emit(cs, va >> 32);
0d69a5
 
0d69a5
 			cmd_buffer->state.active_pipeline_gds_queries--;
0d69a5
 		}
0d69a5
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
0d69a5
index 9d9491d4361..2eb3ba4e64e 100644
0d69a5
--- a/src/amd/vulkan/radv_shader.h
0d69a5
+++ b/src/amd/vulkan/radv_shader.h
0d69a5
@@ -573,9 +573,11 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices,
0d69a5
 	if (chip_class >= GFX7 && family != CHIP_STONEY)
0d69a5
 		hardware_lds_size = 65536;
0d69a5
 
0d69a5
-	num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
0d69a5
+	if (input_patch_size + output_patch_size)
0d69a5
+		num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
0d69a5
 	/* Make sure the output data fits in the offchip buffer */
0d69a5
-	num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
0d69a5
+	if (output_patch_size)
0d69a5
+		num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
0d69a5
 	/* Not necessary for correctness, but improves performance. The
0d69a5
 	 * specific value is taken from the proprietary driver.
0d69a5
 	 */
0d69a5
diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c b/src/gallium/auxiliary/cso_cache/cso_context.c
0d69a5
index 1eef6aac70c..a6a663d97a6 100644
0d69a5
--- a/src/gallium/auxiliary/cso_cache/cso_context.c
0d69a5
+++ b/src/gallium/auxiliary/cso_cache/cso_context.c
0d69a5
@@ -402,10 +402,13 @@ void cso_destroy_context( struct cso_context *ctx )
0d69a5
                                                 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS);
0d69a5
             int maxcb = scr->get_shader_param(scr, sh,
0d69a5
                                               PIPE_SHADER_CAP_MAX_CONST_BUFFERS);
0d69a5
+            int maximg = scr->get_shader_param(scr, sh,
0d69a5
+                                              PIPE_SHADER_CAP_MAX_SHADER_IMAGES);
0d69a5
             assert(maxsam <= PIPE_MAX_SAMPLERS);
0d69a5
             assert(maxview <= PIPE_MAX_SHADER_SAMPLER_VIEWS);
0d69a5
             assert(maxssbo <= PIPE_MAX_SHADER_BUFFERS);
0d69a5
             assert(maxcb <= PIPE_MAX_CONSTANT_BUFFERS);
0d69a5
+            assert(maximg <= PIPE_MAX_SHADER_IMAGES);
0d69a5
             if (maxsam > 0) {
0d69a5
                ctx->pipe->bind_sampler_states(ctx->pipe, sh, 0, maxsam, zeros);
0d69a5
             }
0d69a5
@@ -415,6 +418,9 @@ void cso_destroy_context( struct cso_context *ctx )
0d69a5
             if (maxssbo > 0) {
0d69a5
                ctx->pipe->set_shader_buffers(ctx->pipe, sh, 0, maxssbo, ssbos, 0);
0d69a5
             }
0d69a5
+            if (maximg > 0) {
0d69a5
+               ctx->pipe->set_shader_images(ctx->pipe, sh, 0, maximg, NULL);
0d69a5
+            }
0d69a5
             for (int i = 0; i < maxcb; i++) {
0d69a5
                ctx->pipe->set_constant_buffer(ctx->pipe, sh, i, NULL);
0d69a5
             }
0d69a5
diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
0d69a5
index 8157e921850..971fc80b5ac 100644
0d69a5
--- a/src/gallium/drivers/iris/iris_program.c
0d69a5
+++ b/src/gallium/drivers/iris/iris_program.c
0d69a5
@@ -2109,8 +2109,8 @@ iris_get_scratch_space(struct iris_context *ice,
0d69a5
     * in the base configuration.
0d69a5
     */
0d69a5
    unsigned subslice_total = screen->subslice_total;
0d69a5
-   if (devinfo->gen >= 12)
0d69a5
-      subslice_total = devinfo->num_subslices[0];
0d69a5
+   if (devinfo->gen == 12)
0d69a5
+      subslice_total = (devinfo->is_dg1 || devinfo->gt == 2 ? 6 : 2);
0d69a5
    else if (devinfo->gen == 11)
0d69a5
       subslice_total = 8;
0d69a5
    else if (devinfo->gen < 11)
0d69a5
diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
0d69a5
index 276ad62b1dd..045f43ed8c0 100644
0d69a5
--- a/src/gallium/drivers/iris/iris_resolve.c
0d69a5
+++ b/src/gallium/drivers/iris/iris_resolve.c
0d69a5
@@ -793,7 +793,9 @@ iris_resource_set_aux_state(struct iris_context *ice,
0d69a5
       if (res->aux.state[level][start_layer + a] != aux_state) {
0d69a5
          res->aux.state[level][start_layer + a] = aux_state;
0d69a5
          /* XXX: Need to track which bindings to make dirty */
0d69a5
-         ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
0d69a5
+         ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER |
0d69a5
+                             IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
0d69a5
+                             IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES;
0d69a5
          ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
0d69a5
       }
0d69a5
    }
0d69a5
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
0d69a5
index 8747ef4aa8a..3b34e32cd21 100644
0d69a5
--- a/src/gallium/drivers/iris/iris_resource.c
0d69a5
+++ b/src/gallium/drivers/iris/iris_resource.c
0d69a5
@@ -1125,6 +1125,20 @@ iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
0d69a5
                                 0, INTEL_REMAINING_LAYERS,
0d69a5
                                 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
0d69a5
                                 mod ? mod->supports_clear_color : false);
0d69a5
+
0d69a5
+   if (!res->mod_info && res->aux.usage != ISL_AUX_USAGE_NONE) {
0d69a5
+      /* flush_resource may be used to prepare an image for sharing external
0d69a5
+       * to the driver (e.g. via eglCreateImage). To account for this, make
0d69a5
+       * sure to get rid of any compression that a consumer wouldn't know how
0d69a5
+       * to handle.
0d69a5
+       */
0d69a5
+      for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
0d69a5
+         if (iris_batch_references(&ice->batches[i], res->bo))
0d69a5
+            iris_batch_flush(&ice->batches[i]);
0d69a5
+      }
0d69a5
+
0d69a5
+      iris_resource_disable_aux(res);
0d69a5
+   }
0d69a5
 }
0d69a5
 
0d69a5
 static void
0d69a5
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
0d69a5
index 59a63f7bbab..b9ddb863a16 100644
0d69a5
--- a/src/gallium/drivers/iris/iris_state.c
0d69a5
+++ b/src/gallium/drivers/iris/iris_state.c
0d69a5
@@ -1666,6 +1666,8 @@ struct iris_rasterizer_state {
0d69a5
    bool multisample;
0d69a5
    bool force_persample_interp;
0d69a5
    bool conservative_rasterization;
0d69a5
+   bool fill_mode_point;
0d69a5
+   bool fill_mode_line;
0d69a5
    bool fill_mode_point_or_line;
0d69a5
    enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
0d69a5
    uint16_t sprite_coord_enable;
0d69a5
@@ -1729,11 +1731,15 @@ iris_create_rasterizer_state(struct pipe_context *ctx,
0d69a5
    cso->conservative_rasterization =
0d69a5
       state->conservative_raster_mode == PIPE_CONSERVATIVE_RASTER_POST_SNAP;
0d69a5
 
0d69a5
-   cso->fill_mode_point_or_line =
0d69a5
-      state->fill_front == PIPE_POLYGON_MODE_LINE ||
0d69a5
+   cso->fill_mode_point =
0d69a5
       state->fill_front == PIPE_POLYGON_MODE_POINT ||
0d69a5
-      state->fill_back == PIPE_POLYGON_MODE_LINE ||
0d69a5
       state->fill_back == PIPE_POLYGON_MODE_POINT;
0d69a5
+   cso->fill_mode_line =
0d69a5
+      state->fill_front == PIPE_POLYGON_MODE_LINE ||
0d69a5
+      state->fill_back == PIPE_POLYGON_MODE_LINE;
0d69a5
+   cso->fill_mode_point_or_line =
0d69a5
+      cso->fill_mode_point ||
0d69a5
+      cso->fill_mode_line;
0d69a5
 
0d69a5
    if (state->clip_plane_enable != 0)
0d69a5
       cso->num_clip_plane_consts = util_logbase2(state->clip_plane_enable) + 1;
0d69a5
@@ -4059,6 +4065,28 @@ iris_emit_sbe_swiz(struct iris_batch *batch,
0d69a5
    }
0d69a5
 }
0d69a5
 
0d69a5
+static bool
0d69a5
+iris_is_drawing_points(const struct iris_context *ice)
0d69a5
+{
0d69a5
+   const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
0d69a5
+
0d69a5
+   if (cso_rast->fill_mode_point) {
0d69a5
+      return true;
0d69a5
+   }
0d69a5
+
0d69a5
+   if (ice->shaders.prog[MESA_SHADER_GEOMETRY]) {
0d69a5
+      const struct brw_gs_prog_data *gs_prog_data =
0d69a5
+         (void *) ice->shaders.prog[MESA_SHADER_GEOMETRY]->prog_data;
0d69a5
+      return gs_prog_data->output_topology == _3DPRIM_POINTLIST;
0d69a5
+   } else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL]) {
0d69a5
+      const struct brw_tes_prog_data *tes_data =
0d69a5
+         (void *) ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data;
0d69a5
+      return tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_POINT;
0d69a5
+   } else {
0d69a5
+      return ice->state.prim_mode == PIPE_PRIM_POINTS;
0d69a5
+   }
0d69a5
+}
0d69a5
+
0d69a5
 static unsigned
0d69a5
 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data *prog_data,
0d69a5
                                       const struct iris_rasterizer_state *cso)
0d69a5
@@ -4093,7 +4121,8 @@ iris_emit_sbe(struct iris_batch *batch, const struct iris_context *ice)
0d69a5
                                       &urb_read_offset, &urb_read_length);
0d69a5
 
0d69a5
    unsigned sprite_coord_overrides =
0d69a5
-      iris_calculate_point_sprite_overrides(wm_prog_data, cso_rast);
0d69a5
+      iris_is_drawing_points(ice) ?
0d69a5
+      iris_calculate_point_sprite_overrides(wm_prog_data, cso_rast) : 0;
0d69a5
 
0d69a5
    iris_emit_cmd(batch, GENX(3DSTATE_SBE), sbe) {
0d69a5
       sbe.AttributeSwizzleEnable = true;
0d69a5
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
0d69a5
index 8f688fa3650..ef35f86b05f 100644
0d69a5
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
0d69a5
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
0d69a5
@@ -1482,11 +1482,12 @@ void si_update_needs_color_decompress_masks(struct si_context *sctx)
0d69a5
 /* Reset descriptors of buffer resources after \p buf has been invalidated.
0d69a5
  * If buf == NULL, reset all descriptors.
0d69a5
  */
0d69a5
-static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
0d69a5
+static bool si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
0d69a5
                                       unsigned descriptors_idx, uint64_t slot_mask,
0d69a5
                                       struct pipe_resource *buf, enum radeon_bo_priority priority)
0d69a5
 {
0d69a5
    struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
0d69a5
+   bool noop = true;
0d69a5
    uint64_t mask = buffers->enabled_mask & slot_mask;
0d69a5
 
0d69a5
    while (mask) {
0d69a5
@@ -1501,8 +1502,10 @@ static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_
0d69a5
             sctx, si_resource(buffer),
0d69a5
             buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
0d69a5
             priority, true);
0d69a5
+         noop = false;
0d69a5
       }
0d69a5
    }
0d69a5
+   return !noop;
0d69a5
 }
0d69a5
 
0d69a5
 /* Update all buffer bindings where the buffer is bound, including
0d69a5
@@ -1577,11 +1580,15 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
0d69a5
    }
0d69a5
 
0d69a5
    if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
0d69a5
-      for (shader = 0; shader < SI_NUM_SHADERS; shader++)
0d69a5
-         si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
0d69a5
-                                   si_const_and_shader_buffer_descriptors_idx(shader),
0d69a5
-                                   u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
0d69a5
-                                   sctx->const_and_shader_buffers[shader].priority);
0d69a5
+      for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
0d69a5
+         if (si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
0d69a5
+                                       si_const_and_shader_buffer_descriptors_idx(shader),
0d69a5
+                                       u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
0d69a5
+                                       sctx->const_and_shader_buffers[shader].priority) &&
0d69a5
+             shader == PIPE_SHADER_COMPUTE) {
0d69a5
+            sctx->compute_shaderbuf_sgprs_dirty = true;
0d69a5
+         }
0d69a5
+      }
0d69a5
    }
0d69a5
 
0d69a5
    if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
0d69a5
@@ -1633,6 +1640,9 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
0d69a5
                radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
0d69a5
                                                        RADEON_USAGE_READWRITE,
0d69a5
                                                        RADEON_PRIO_SAMPLER_BUFFER, true);
0d69a5
+
0d69a5
+               if (shader == PIPE_SHADER_COMPUTE)
0d69a5
+                  sctx->compute_image_sgprs_dirty = true;
0d69a5
             }
0d69a5
          }
0d69a5
       }
0d69a5
diff --git a/src/gallium/frontends/dri/dri_helpers.c b/src/gallium/frontends/dri/dri_helpers.c
0d69a5
index 01a1fb3d96c..5e87df35a55 100644
0d69a5
--- a/src/gallium/frontends/dri/dri_helpers.c
0d69a5
+++ b/src/gallium/frontends/dri/dri_helpers.c
0d69a5
@@ -258,7 +258,9 @@ dri2_create_image_from_renderbuffer2(__DRIcontext *context,
0d69a5
 				     int renderbuffer, void *loaderPrivate,
0d69a5
                                      unsigned *error)
0d69a5
 {
0d69a5
-   struct gl_context *ctx = ((struct st_context *)dri_context(context)->st)->ctx;
0d69a5
+   struct st_context *st_ctx = (struct st_context *)dri_context(context)->st;
0d69a5
+   struct gl_context *ctx = st_ctx->ctx;
0d69a5
+   struct pipe_context *p_ctx = st_ctx->pipe;
0d69a5
    struct gl_renderbuffer *rb;
0d69a5
    struct pipe_resource *tex;
0d69a5
    __DRIimage *img;
0d69a5
@@ -299,6 +301,13 @@ dri2_create_image_from_renderbuffer2(__DRIcontext *context,
0d69a5
 
0d69a5
    pipe_resource_reference(&img->texture, tex);
0d69a5
 
0d69a5
+   /* If the resource supports EGL_MESA_image_dma_buf_export, make sure that
0d69a5
+    * it's in a shareable state. Do this now while we still have the access to
0d69a5
+    * the context.
0d69a5
+    */
0d69a5
+   if (dri2_get_mapping_by_format(img->dri_format))
0d69a5
+      p_ctx->flush_resource(p_ctx, tex);
0d69a5
+
0d69a5
    *error = __DRI_IMAGE_ERROR_SUCCESS;
0d69a5
    return img;
0d69a5
 }
0d69a5
@@ -326,7 +335,9 @@ dri2_create_from_texture(__DRIcontext *context, int target, unsigned texture,
0d69a5
                          void *loaderPrivate)
0d69a5
 {
0d69a5
    __DRIimage *img;
0d69a5
-   struct gl_context *ctx = ((struct st_context *)dri_context(context)->st)->ctx;
0d69a5
+   struct st_context *st_ctx = (struct st_context *)dri_context(context)->st;
0d69a5
+   struct gl_context *ctx = st_ctx->ctx;
0d69a5
+   struct pipe_context *p_ctx = st_ctx->pipe;
0d69a5
    struct gl_texture_object *obj;
0d69a5
    struct pipe_resource *tex;
0d69a5
    GLuint face = 0;
0d69a5
@@ -376,6 +387,13 @@ dri2_create_from_texture(__DRIcontext *context, int target, unsigned texture,
0d69a5
 
0d69a5
    pipe_resource_reference(&img->texture, tex);
0d69a5
 
0d69a5
+   /* If the resource supports EGL_MESA_image_dma_buf_export, make sure that
0d69a5
+    * it's in a shareable state. Do this now while we still have the access to
0d69a5
+    * the context.
0d69a5
+    */
0d69a5
+   if (dri2_get_mapping_by_format(img->dri_format))
0d69a5
+      p_ctx->flush_resource(p_ctx, tex);
0d69a5
+
0d69a5
    *error = __DRI_IMAGE_ERROR_SUCCESS;
0d69a5
    return img;
0d69a5
 }
0d69a5
@@ -547,6 +565,9 @@ dri2_get_mapping_by_fourcc(int fourcc)
0d69a5
 const struct dri2_format_mapping *
0d69a5
 dri2_get_mapping_by_format(int format)
0d69a5
 {
0d69a5
+   if (format == __DRI_IMAGE_FORMAT_NONE)
0d69a5
+      return NULL;
0d69a5
+
0d69a5
    for (unsigned i = 0; i < ARRAY_SIZE(dri2_format_table); i++) {
0d69a5
       if (dri2_format_table[i].dri_format == format)
0d69a5
          return &dri2_format_table[i];
0d69a5
diff --git a/src/gallium/frontends/lavapipe/lvp_device.c b/src/gallium/frontends/lavapipe/lvp_device.c
0d69a5
index 45734f95880..187aecde1f8 100644
0d69a5
--- a/src/gallium/frontends/lavapipe/lvp_device.c
0d69a5
+++ b/src/gallium/frontends/lavapipe/lvp_device.c
0d69a5
@@ -52,8 +52,6 @@ lvp_physical_device_init(struct lvp_physical_device *device,
0d69a5
    if (!device->pscreen)
0d69a5
       return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
0d69a5
 
0d69a5
-   fprintf(stderr, "WARNING: lavapipe is not a conformant vulkan implementation, testing use only.\n");
0d69a5
-
0d69a5
    device->max_images = device->pscreen->get_shader_param(device->pscreen, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_MAX_SHADER_IMAGES);
0d69a5
    lvp_physical_device_get_supported_extensions(device, &device->supported_extensions);
0d69a5
    result = lvp_init_wsi(device);
0d69a5
@@ -575,6 +573,19 @@ void lvp_GetPhysicalDeviceProperties2(
0d69a5
    }
0d69a5
 }
0d69a5
 
0d69a5
+static void lvp_get_physical_device_queue_family_properties(
0d69a5
+   VkQueueFamilyProperties*                    pQueueFamilyProperties)
0d69a5
+{
0d69a5
+   *pQueueFamilyProperties = (VkQueueFamilyProperties) {
0d69a5
+      .queueFlags = VK_QUEUE_GRAPHICS_BIT |
0d69a5
+      VK_QUEUE_COMPUTE_BIT |
0d69a5
+      VK_QUEUE_TRANSFER_BIT,
0d69a5
+      .queueCount = 1,
0d69a5
+      .timestampValidBits = 64,
0d69a5
+      .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
0d69a5
+   };
0d69a5
+}
0d69a5
+
0d69a5
 void lvp_GetPhysicalDeviceQueueFamilyProperties(
0d69a5
    VkPhysicalDevice                            physicalDevice,
0d69a5
    uint32_t*                                   pCount,
0d69a5
@@ -586,15 +597,21 @@ void lvp_GetPhysicalDeviceQueueFamilyProperties(
0d69a5
    }
0d69a5
 
0d69a5
    assert(*pCount >= 1);
0d69a5
+   lvp_get_physical_device_queue_family_properties(pQueueFamilyProperties);
0d69a5
+}
0d69a5
 
0d69a5
-   *pQueueFamilyProperties = (VkQueueFamilyProperties) {
0d69a5
-      .queueFlags = VK_QUEUE_GRAPHICS_BIT |
0d69a5
-      VK_QUEUE_COMPUTE_BIT |
0d69a5
-      VK_QUEUE_TRANSFER_BIT,
0d69a5
-      .queueCount = 1,
0d69a5
-      .timestampValidBits = 64,
0d69a5
-      .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
0d69a5
-   };
0d69a5
+void lvp_GetPhysicalDeviceQueueFamilyProperties2(
0d69a5
+   VkPhysicalDevice                            physicalDevice,
0d69a5
+   uint32_t*                                   pCount,
0d69a5
+   VkQueueFamilyProperties2                   *pQueueFamilyProperties)
0d69a5
+{
0d69a5
+   if (pQueueFamilyProperties == NULL) {
0d69a5
+      *pCount = 1;
0d69a5
+      return;
0d69a5
+   }
0d69a5
+
0d69a5
+   assert(*pCount >= 1);
0d69a5
+   lvp_get_physical_device_queue_family_properties(&pQueueFamilyProperties->queueFamilyProperties);
0d69a5
 }
0d69a5
 
0d69a5
 void lvp_GetPhysicalDeviceMemoryProperties(
0d69a5
@@ -617,6 +634,14 @@ void lvp_GetPhysicalDeviceMemoryProperties(
0d69a5
    };
0d69a5
 }
0d69a5
 
0d69a5
+void lvp_GetPhysicalDeviceMemoryProperties2(
0d69a5
+   VkPhysicalDevice                            physicalDevice,
0d69a5
+   VkPhysicalDeviceMemoryProperties2          *pMemoryProperties)
0d69a5
+{
0d69a5
+   lvp_GetPhysicalDeviceMemoryProperties(physicalDevice,
0d69a5
+                                         &pMemoryProperties->memoryProperties);
0d69a5
+}
0d69a5
+
0d69a5
 PFN_vkVoidFunction lvp_GetInstanceProcAddr(
0d69a5
    VkInstance                                  _instance,
0d69a5
    const char*                                 pName)
0d69a5
@@ -822,6 +847,8 @@ VkResult lvp_CreateDevice(
0d69a5
    const VkAllocationCallbacks*                pAllocator,
0d69a5
    VkDevice*                                   pDevice)
0d69a5
 {
0d69a5
+   fprintf(stderr, "WARNING: lavapipe is not a conformant vulkan implementation, testing use only.\n");
0d69a5
+
0d69a5
    LVP_FROM_HANDLE(lvp_physical_device, physical_device, physicalDevice);
0d69a5
    struct lvp_device *device;
0d69a5
 
0d69a5
diff --git a/src/glx/g_glxglvnddispatchfuncs.c b/src/glx/g_glxglvnddispatchfuncs.c
0d69a5
index 0f02ed2d321..e0ea27c0b18 100644
0d69a5
--- a/src/glx/g_glxglvnddispatchfuncs.c
0d69a5
+++ b/src/glx/g_glxglvnddispatchfuncs.c
0d69a5
@@ -87,6 +87,7 @@ const char * const __glXDispatchTableStrings[DI_LAST_INDEX] = {
0d69a5
     __ATTRIB(SelectEventSGIX),
0d69a5
     // glXSwapBuffers implemented by libglvnd
0d69a5
     __ATTRIB(SwapBuffersMscOML),
0d69a5
+    __ATTRIB(SwapIntervalEXT),
0d69a5
     __ATTRIB(SwapIntervalMESA),
0d69a5
     __ATTRIB(SwapIntervalSGI),
0d69a5
     // glXUseXFont implemented by libglvnd
0d69a5
@@ -893,6 +894,24 @@ static int dispatch_SwapIntervalMESA(unsigned int interval)
0d69a5
 
0d69a5
 
0d69a5
 
0d69a5
+static void dispatch_SwapIntervalEXT(Display *dpy, GLXDrawable drawable, int interval)
0d69a5
+{
0d69a5
+    PFNGLXSWAPINTERVALEXTPROC pSwapIntervalEXT;
0d69a5
+    __GLXvendorInfo *dd;
0d69a5
+
0d69a5
+    dd = GetDispatchFromDrawable(dpy, drawable);
0d69a5
+    if (dd == NULL)
0d69a5
+        return;
0d69a5
+
0d69a5
+    __FETCH_FUNCTION_PTR(SwapIntervalEXT);
0d69a5
+    if (pSwapIntervalEXT == NULL)
0d69a5
+        return;
0d69a5
+
0d69a5
+    pSwapIntervalEXT(dpy, drawable, interval);
0d69a5
+}
0d69a5
+
0d69a5
+
0d69a5
+
0d69a5
 static Bool dispatch_WaitForMscOML(Display *dpy, GLXDrawable drawable,
0d69a5
                                       int64_t target_msc, int64_t divisor,
0d69a5
                                       int64_t remainder, int64_t *ust,
0d69a5
@@ -974,6 +993,7 @@ const void * const __glXDispatchFunctions[DI_LAST_INDEX + 1] = {
0d69a5
     __ATTRIB(ReleaseTexImageEXT),
0d69a5
     __ATTRIB(SelectEventSGIX),
0d69a5
     __ATTRIB(SwapBuffersMscOML),
0d69a5
+    __ATTRIB(SwapIntervalEXT),
0d69a5
     __ATTRIB(SwapIntervalMESA),
0d69a5
     __ATTRIB(SwapIntervalSGI),
0d69a5
     __ATTRIB(WaitForMscOML),
0d69a5
diff --git a/src/glx/g_glxglvnddispatchindices.h b/src/glx/g_glxglvnddispatchindices.h
0d69a5
index 3ba50a74abb..b65d078098f 100644
0d69a5
--- a/src/glx/g_glxglvnddispatchindices.h
0d69a5
+++ b/src/glx/g_glxglvnddispatchindices.h
0d69a5
@@ -79,6 +79,7 @@ typedef enum __GLXdispatchIndex {
0d69a5
     DI_SelectEventSGIX,
0d69a5
     // SwapBuffers implemented by libglvnd
0d69a5
     DI_SwapBuffersMscOML,
0d69a5
+    DI_SwapIntervalEXT,
0d69a5
     DI_SwapIntervalMESA,
0d69a5
     DI_SwapIntervalSGI,
0d69a5
     // UseXFont implemented by libglvnd
0d69a5
diff --git a/src/intel/common/gen_mi_builder.h b/src/intel/common/gen_mi_builder.h
0d69a5
index ddd8459ef07..47fb98e99f7 100644
0d69a5
--- a/src/intel/common/gen_mi_builder.h
0d69a5
+++ b/src/intel/common/gen_mi_builder.h
0d69a5
@@ -932,6 +932,13 @@ gen_mi_store_address(struct gen_mi_builder *b,
0d69a5
 static inline void
0d69a5
 gen_mi_self_mod_barrier(struct gen_mi_builder *b)
0d69a5
 {
0d69a5
+   /* First make sure all the memory writes from previous modifying commands
0d69a5
+    * have landed. We want to do this before going through the CS cache,
0d69a5
+    * otherwise we could be fetching memory that hasn't been written to yet.
0d69a5
+    */
0d69a5
+   gen_mi_builder_emit(b, GENX(PIPE_CONTROL), pc) {
0d69a5
+      pc.CommandStreamerStallEnable = true;
0d69a5
+   }
0d69a5
    /* Documentation says Gen11+ should be able to invalidate the command cache
0d69a5
     * but experiment show it doesn't work properly, so for now just get over
0d69a5
     * the CS prefetch.
0d69a5
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
0d69a5
index 917c3abfe9e..6896987055f 100644
0d69a5
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
0d69a5
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
0d69a5
@@ -437,6 +437,7 @@ instruction_requires_packed_data(fs_inst *inst)
0d69a5
    case FS_OPCODE_DDX_COARSE:
0d69a5
    case FS_OPCODE_DDY_FINE:
0d69a5
    case FS_OPCODE_DDY_COARSE:
0d69a5
+   case SHADER_OPCODE_QUAD_SWIZZLE:
0d69a5
       return true;
0d69a5
    default:
0d69a5
       return false;
0d69a5
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
0d69a5
index 6ba3a6ca97e..3a4acc1834a 100644
0d69a5
--- a/src/intel/compiler/brw_ir_fs.h
0d69a5
+++ b/src/intel/compiler/brw_ir_fs.h
0d69a5
@@ -451,13 +451,15 @@ regs_written(const fs_inst *inst)
0d69a5
  * Return the number of dataflow registers read by the instruction (either
0d69a5
  * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
0d69a5
  * register_size)'.  The somewhat arbitrary register size unit is 4B for the
0d69a5
- * UNIFORM and IMM files and 32B for all other files.
0d69a5
+ * UNIFORM files and 32B for all other files.
0d69a5
  */
0d69a5
 inline unsigned
0d69a5
 regs_read(const fs_inst *inst, unsigned i)
0d69a5
 {
0d69a5
-   const unsigned reg_size =
0d69a5
-      inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 4 : REG_SIZE;
0d69a5
+   if (inst->src[i].file == IMM)
0d69a5
+      return 1;
0d69a5
+
0d69a5
+   const unsigned reg_size = inst->src[i].file == UNIFORM ? 4 : REG_SIZE;
0d69a5
    return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size +
0d69a5
                        inst->size_read(i) -
0d69a5
                        MIN2(inst->size_read(i), reg_padding(inst->src[i])),
0d69a5
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
0d69a5
index 9007cd00e85..48811912e95 100644
0d69a5
--- a/src/intel/vulkan/anv_allocator.c
0d69a5
+++ b/src/intel/vulkan/anv_allocator.c
0d69a5
@@ -1447,8 +1447,8 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
0d69a5
     * For, Gen11+, scratch space allocation is based on the number of threads
0d69a5
     * in the base configuration.
0d69a5
     */
0d69a5
-   if (devinfo->gen >= 12)
0d69a5
-      subslices = devinfo->num_subslices[0];
0d69a5
+   if (devinfo->gen == 12)
0d69a5
+      subslices = (devinfo->is_dg1 || devinfo->gt == 2 ? 6 : 2);
0d69a5
    else if (devinfo->gen == 11)
0d69a5
       subslices = 8;
0d69a5
    else if (devinfo->gen >= 9)
0d69a5
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
0d69a5
index 0290431f145..80307cd612f 100644
0d69a5
--- a/src/intel/vulkan/anv_image.c
0d69a5
+++ b/src/intel/vulkan/anv_image.c
0d69a5
@@ -684,6 +684,25 @@ choose_drm_format_mod(const struct anv_physical_device *device,
0d69a5
       return NULL;
0d69a5
 }
0d69a5
 
0d69a5
+static VkImageUsageFlags
0d69a5
+anv_image_create_usage(const VkImageCreateInfo *pCreateInfo,
0d69a5
+                       VkImageUsageFlags usage)
0d69a5
+{
0d69a5
+   /* Add TRANSFER_SRC usage for multisample attachment images. This is
0d69a5
+    * because we might internally use the TRANSFER_SRC layout on them for
0d69a5
+    * blorp operations associated with resolving those into other attachments
0d69a5
+    * at the end of a subpass.
0d69a5
+    *
0d69a5
+    * Without this additional usage, we compute an incorrect AUX state in
0d69a5
+    * anv_layout_to_aux_state().
0d69a5
+    */
0d69a5
+   if (pCreateInfo->samples > VK_SAMPLE_COUNT_1_BIT &&
0d69a5
+       (usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
0d69a5
+                 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)))
0d69a5
+      usage |= VK_IMAGE_USAGE_TRANSFER_SRC_BIT;
0d69a5
+   return usage;
0d69a5
+}
0d69a5
+
0d69a5
 VkResult
0d69a5
 anv_image_create(VkDevice _device,
0d69a5
                  const struct anv_image_create_info *create_info,
0d69a5
@@ -732,7 +751,7 @@ anv_image_create(VkDevice _device,
0d69a5
    image->levels = pCreateInfo->mipLevels;
0d69a5
    image->array_size = pCreateInfo->arrayLayers;
0d69a5
    image->samples = pCreateInfo->samples;
0d69a5
-   image->usage = pCreateInfo->usage;
0d69a5
+   image->usage = anv_image_create_usage(pCreateInfo, pCreateInfo->usage);
0d69a5
    image->create_flags = pCreateInfo->flags;
0d69a5
    image->tiling = pCreateInfo->tiling;
0d69a5
    image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT;
0d69a5
@@ -745,8 +764,11 @@ anv_image_create(VkDevice _device,
0d69a5
       const VkImageStencilUsageCreateInfoEXT *stencil_usage_info =
0d69a5
          vk_find_struct_const(pCreateInfo->pNext,
0d69a5
                               IMAGE_STENCIL_USAGE_CREATE_INFO_EXT);
0d69a5
-      if (stencil_usage_info)
0d69a5
-         image->stencil_usage = stencil_usage_info->stencilUsage;
0d69a5
+      if (stencil_usage_info) {
0d69a5
+         image->stencil_usage =
0d69a5
+            anv_image_create_usage(pCreateInfo,
0d69a5
+                                   stencil_usage_info->stencilUsage);
0d69a5
+      }
0d69a5
    }
0d69a5
 
0d69a5
    /* In case of external format, We don't know format yet,
0d69a5
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
0d69a5
index af23b87969d..1818f6c587b 100644
0d69a5
--- a/src/intel/vulkan/anv_pass.c
0d69a5
+++ b/src/intel/vulkan/anv_pass.c
0d69a5
@@ -23,6 +23,7 @@
0d69a5
 
0d69a5
 #include "anv_private.h"
0d69a5
 
0d69a5
+#include "vk_format_info.h"
0d69a5
 #include "vk_util.h"
0d69a5
 
0d69a5
 static void
0d69a5
@@ -406,6 +407,70 @@ num_subpass_attachments2(const VkSubpassDescription2KHR *desc)
0d69a5
           (ds_resolve && ds_resolve->pDepthStencilResolveAttachment);
0d69a5
 }
0d69a5
 
0d69a5
+static bool
0d69a5
+vk_image_layout_depth_only(VkImageLayout layout)
0d69a5
+{
0d69a5
+   switch (layout) {
0d69a5
+   case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL:
0d69a5
+   case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL:
0d69a5
+      return true;
0d69a5
+
0d69a5
+   default:
0d69a5
+      return false;
0d69a5
+   }
0d69a5
+}
0d69a5
+
0d69a5
+/* From the Vulkan Specification 1.2.166 - VkAttachmentReference2:
0d69a5
+ *
0d69a5
+ *   "If layout only specifies the layout of the depth aspect of the
0d69a5
+ *    attachment, the layout of the stencil aspect is specified by the
0d69a5
+ *    stencilLayout member of a VkAttachmentReferenceStencilLayout structure
0d69a5
+ *    included in the pNext chain. Otherwise, layout describes the layout for
0d69a5
+ *    all relevant image aspects."
0d69a5
+ */
0d69a5
+static VkImageLayout
0d69a5
+stencil_ref_layout(const VkAttachmentReference2KHR *att_ref)
0d69a5
+{
0d69a5
+   if (!vk_image_layout_depth_only(att_ref->layout))
0d69a5
+      return att_ref->layout;
0d69a5
+
0d69a5
+   const VkAttachmentReferenceStencilLayoutKHR *stencil_ref =
0d69a5
+      vk_find_struct_const(att_ref->pNext,
0d69a5
+                           ATTACHMENT_REFERENCE_STENCIL_LAYOUT_KHR);
0d69a5
+   if (!stencil_ref)
0d69a5
+      return VK_IMAGE_LAYOUT_UNDEFINED;
0d69a5
+   return stencil_ref->stencilLayout;
0d69a5
+}
0d69a5
+
0d69a5
+/* From the Vulkan Specification 1.2.166 - VkAttachmentDescription2:
0d69a5
+ *
0d69a5
+ *   "If format is a depth/stencil format, and initialLayout only specifies
0d69a5
+ *    the initial layout of the depth aspect of the attachment, the initial
0d69a5
+ *    layout of the stencil aspect is specified by the stencilInitialLayout
0d69a5
+ *    member of a VkAttachmentDescriptionStencilLayout structure included in
0d69a5
+ *    the pNext chain. Otherwise, initialLayout describes the initial layout
0d69a5
+ *    for all relevant image aspects."
0d69a5
+ */
0d69a5
+static VkImageLayout
0d69a5
+stencil_desc_layout(const VkAttachmentDescription2KHR *att_desc, bool final)
0d69a5
+{
0d69a5
+   if (!vk_format_has_stencil(att_desc->format))
0d69a5
+      return VK_IMAGE_LAYOUT_UNDEFINED;
0d69a5
+
0d69a5
+   const VkImageLayout main_layout =
0d69a5
+      final ? att_desc->finalLayout : att_desc->initialLayout;
0d69a5
+   if (!vk_image_layout_depth_only(main_layout))
0d69a5
+      return main_layout;
0d69a5
+
0d69a5
+   const VkAttachmentDescriptionStencilLayoutKHR *stencil_desc =
0d69a5
+      vk_find_struct_const(att_desc->pNext,
0d69a5
+                           ATTACHMENT_DESCRIPTION_STENCIL_LAYOUT_KHR);
0d69a5
+   assert(stencil_desc);
0d69a5
+   return final ?
0d69a5
+      stencil_desc->stencilFinalLayout :
0d69a5
+      stencil_desc->stencilInitialLayout;
0d69a5
+}
0d69a5
+
0d69a5
 VkResult anv_CreateRenderPass2(
0d69a5
     VkDevice                                    _device,
0d69a5
     const VkRenderPassCreateInfo2KHR*           pCreateInfo,
0d69a5
@@ -450,10 +515,6 @@ VkResult anv_CreateRenderPass2(
0d69a5
    pass->subpass_flushes = subpass_flushes;
0d69a5
 
0d69a5
    for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
0d69a5
-      const VkAttachmentDescriptionStencilLayoutKHR *stencil_layout =
0d69a5
-         vk_find_struct_const(pCreateInfo->pAttachments[i].pNext,
0d69a5
-                              ATTACHMENT_DESCRIPTION_STENCIL_LAYOUT_KHR);
0d69a5
-
0d69a5
       pass->attachments[i] = (struct anv_render_pass_attachment) {
0d69a5
          .format                 = pCreateInfo->pAttachments[i].format,
0d69a5
          .samples                = pCreateInfo->pAttachments[i].samples,
0d69a5
@@ -463,12 +524,10 @@ VkResult anv_CreateRenderPass2(
0d69a5
          .initial_layout         = pCreateInfo->pAttachments[i].initialLayout,
0d69a5
          .final_layout           = pCreateInfo->pAttachments[i].finalLayout,
0d69a5
 
0d69a5
-         .stencil_initial_layout = (stencil_layout ?
0d69a5
-                                    stencil_layout->stencilInitialLayout :
0d69a5
-                                    pCreateInfo->pAttachments[i].initialLayout),
0d69a5
-         .stencil_final_layout   = (stencil_layout ?
0d69a5
-                                    stencil_layout->stencilFinalLayout :
0d69a5
-                                    pCreateInfo->pAttachments[i].finalLayout),
0d69a5
+         .stencil_initial_layout = stencil_desc_layout(&pCreateInfo->pAttachments[i],
0d69a5
+                                                       false),
0d69a5
+         .stencil_final_layout   = stencil_desc_layout(&pCreateInfo->pAttachments[i],
0d69a5
+                                                       true),
0d69a5
       };
0d69a5
    }
0d69a5
 
0d69a5
@@ -487,17 +546,11 @@ VkResult anv_CreateRenderPass2(
0d69a5
          subpass_attachments += desc->inputAttachmentCount;
0d69a5
 
0d69a5
          for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
0d69a5
-            const VkAttachmentReferenceStencilLayoutKHR *stencil_layout =
0d69a5
-               vk_find_struct_const(desc->pInputAttachments[j].pNext,
0d69a5
-                                    ATTACHMENT_REFERENCE_STENCIL_LAYOUT_KHR);
0d69a5
-
0d69a5
             subpass->input_attachments[j] = (struct anv_subpass_attachment) {
0d69a5
                .usage =          VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
0d69a5
                .attachment =     desc->pInputAttachments[j].attachment,
0d69a5
                .layout =         desc->pInputAttachments[j].layout,
0d69a5
-               .stencil_layout = (stencil_layout ?
0d69a5
-                                  stencil_layout->stencilLayout :
0d69a5
-                                  desc->pInputAttachments[j].layout),
0d69a5
+               .stencil_layout = stencil_ref_layout(&desc->pInputAttachments[j]),
0d69a5
             };
0d69a5
          }
0d69a5
       }
0d69a5
@@ -531,17 +584,11 @@ VkResult anv_CreateRenderPass2(
0d69a5
       if (desc->pDepthStencilAttachment) {
0d69a5
          subpass->depth_stencil_attachment = subpass_attachments++;
0d69a5
 
0d69a5
-         const VkAttachmentReferenceStencilLayoutKHR *stencil_attachment =
0d69a5
-            vk_find_struct_const(desc->pDepthStencilAttachment->pNext,
0d69a5
-                                 ATTACHMENT_REFERENCE_STENCIL_LAYOUT_KHR);
0d69a5
-
0d69a5
          *subpass->depth_stencil_attachment = (struct anv_subpass_attachment) {
0d69a5
             .usage =          VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
0d69a5
             .attachment =     desc->pDepthStencilAttachment->attachment,
0d69a5
             .layout =         desc->pDepthStencilAttachment->layout,
0d69a5
-            .stencil_layout = stencil_attachment ?
0d69a5
-                              stencil_attachment->stencilLayout :
0d69a5
-                              desc->pDepthStencilAttachment->layout,
0d69a5
+            .stencil_layout = stencil_ref_layout(desc->pDepthStencilAttachment),
0d69a5
          };
0d69a5
       }
0d69a5
 
0d69a5
@@ -552,17 +599,11 @@ VkResult anv_CreateRenderPass2(
0d69a5
       if (ds_resolve && ds_resolve->pDepthStencilResolveAttachment) {
0d69a5
          subpass->ds_resolve_attachment = subpass_attachments++;
0d69a5
 
0d69a5
-         const VkAttachmentReferenceStencilLayoutKHR *stencil_resolve_attachment =
0d69a5
-            vk_find_struct_const(ds_resolve->pDepthStencilResolveAttachment->pNext,
0d69a5
-                                 ATTACHMENT_REFERENCE_STENCIL_LAYOUT_KHR);
0d69a5
-
0d69a5
          *subpass->ds_resolve_attachment = (struct anv_subpass_attachment) {
0d69a5
             .usage =          VK_IMAGE_USAGE_TRANSFER_DST_BIT,
0d69a5
             .attachment =     ds_resolve->pDepthStencilResolveAttachment->attachment,
0d69a5
             .layout =         ds_resolve->pDepthStencilResolveAttachment->layout,
0d69a5
-            .stencil_layout = stencil_resolve_attachment ?
0d69a5
-                              stencil_resolve_attachment->stencilLayout :
0d69a5
-                              ds_resolve->pDepthStencilResolveAttachment->layout,
0d69a5
+            .stencil_layout = stencil_ref_layout(ds_resolve->pDepthStencilResolveAttachment),
0d69a5
          };
0d69a5
          subpass->depth_resolve_mode = ds_resolve->depthResolveMode;
0d69a5
          subpass->stencil_resolve_mode = ds_resolve->stencilResolveMode;
0d69a5
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
0d69a5
index a9c49e0f592..e3eb376fa5a 100644
0d69a5
--- a/src/intel/vulkan/genX_cmd_buffer.c
0d69a5
+++ b/src/intel/vulkan/genX_cmd_buffer.c
0d69a5
@@ -462,8 +462,10 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
0d69a5
 {
0d69a5
    uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
0d69a5
 
0d69a5
+   const struct anv_surface *surface = &image->planes[plane].surface;
0d69a5
    uint64_t base_address =
0d69a5
-      anv_address_physical(image->planes[plane].address);
0d69a5
+      anv_address_physical(anv_address_add(image->planes[plane].address,
0d69a5
+                                           surface->offset));
0d69a5
 
0d69a5
    const struct isl_surf *isl_surf = &image->planes[plane].surface.isl;
0d69a5
    uint64_t format_bits = gen_aux_map_format_bits_for_isl_surf(isl_surf);
0d69a5
@@ -1231,6 +1233,17 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
0d69a5
             uint32_t level_layer_count =
0d69a5
                MIN2(layer_count, aux_layers - base_layer);
0d69a5
 
0d69a5
+            /* If will_full_fast_clear is set, the caller promises to
0d69a5
+             * fast-clear the largest portion of the specified range as it can.
0d69a5
+             * For color images, that means only the first LOD and array slice.
0d69a5
+             */
0d69a5
+            if (level == 0 && base_layer == 0 && will_full_fast_clear) {
0d69a5
+               base_layer++;
0d69a5
+               level_layer_count--;
0d69a5
+               if (level_layer_count == 0)
0d69a5
+                  continue;
0d69a5
+            }
0d69a5
+
0d69a5
             anv_image_ccs_op(cmd_buffer, image,
0d69a5
                              image->planes[plane].surface.isl.format,
0d69a5
                              ISL_SWIZZLE_IDENTITY,
0d69a5
@@ -1250,6 +1263,12 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
0d69a5
                           "define an MCS buffer.");
0d69a5
          }
0d69a5
 
0d69a5
+         /* If will_full_fast_clear is set, the caller promises to fast-clear
0d69a5
+          * the largest portion of the specified range as it can.
0d69a5
+          */
0d69a5
+         if (will_full_fast_clear)
0d69a5
+            return;
0d69a5
+
0d69a5
          assert(base_level == 0 && level_count == 1);
0d69a5
          anv_image_mcs_op(cmd_buffer, image,
0d69a5
                           image->planes[plane].surface.isl.format,
0d69a5
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
0d69a5
index 205e8677f19..33f071019b7 100644
0d69a5
--- a/src/intel/vulkan/genX_pipeline.c
0d69a5
+++ b/src/intel/vulkan/genX_pipeline.c
0d69a5
@@ -1180,7 +1180,22 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
0d69a5
 #endif
0d69a5
          .LogicOpEnable = info->logicOpEnable,
0d69a5
          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
0d69a5
-         .ColorBufferBlendEnable = a->blendEnable,
0d69a5
+         /* Vulkan specification 1.2.168, VkLogicOp:
0d69a5
+          *
0d69a5
+          *   "Logical operations are controlled by the logicOpEnable and
0d69a5
+          *    logicOp members of VkPipelineColorBlendStateCreateInfo. If
0d69a5
+          *    logicOpEnable is VK_TRUE, then a logical operation selected by
0d69a5
+          *    logicOp is applied between each color attachment and the
0d69a5
+          *    fragment’s corresponding output value, and blending of all
0d69a5
+          *    attachments is treated as if it were disabled."
0d69a5
+          *
0d69a5
+          * From the Broadwell PRM Volume 2d: Command Reference: Structures:
0d69a5
+          * BLEND_STATE_ENTRY:
0d69a5
+          *
0d69a5
+          *   "Enabling LogicOp and Color Buffer Blending at the same time is
0d69a5
+          *    UNDEFINED"
0d69a5
+          */
0d69a5
+         .ColorBufferBlendEnable = !info->logicOpEnable && a->blendEnable,
0d69a5
          .ColorClampRange = COLORCLAMP_RTFORMAT,
0d69a5
          .PreBlendColorClampEnable = true,
0d69a5
          .PostBlendColorClampEnable = true,
0d69a5
diff --git a/src/intel/vulkan/vk_format_info.h b/src/intel/vulkan/vk_format_info.h
0d69a5
index 006e1f4a6ad..4e72c244742 100644
0d69a5
--- a/src/intel/vulkan/vk_format_info.h
0d69a5
+++ b/src/intel/vulkan/vk_format_info.h
0d69a5
@@ -164,4 +164,11 @@ vk_format_has_depth(VkFormat format)
0d69a5
    return aspects & VK_IMAGE_ASPECT_DEPTH_BIT;
0d69a5
 }
0d69a5
 
0d69a5
+static inline bool
0d69a5
+vk_format_has_stencil(VkFormat format)
0d69a5
+{
0d69a5
+   const VkImageAspectFlags aspects = vk_format_aspects(format);
0d69a5
+   return aspects & VK_IMAGE_ASPECT_STENCIL_BIT;
0d69a5
+}
0d69a5
+
0d69a5
 #endif /* VK_FORMAT_INFO_H */
0d69a5
diff --git a/src/mesa/state_tracker/st_pbo.c b/src/mesa/state_tracker/st_pbo.c
0d69a5
index 65a1ce8862a..b03921c1be6 100644
0d69a5
--- a/src/mesa/state_tracker/st_pbo.c
0d69a5
+++ b/src/mesa/state_tracker/st_pbo.c
0d69a5
@@ -431,16 +431,21 @@ create_fs(struct st_context *st, bool download,
0d69a5
    nir_ssa_def *coord = nir_load_var(&b, fragcoord);
0d69a5
 
0d69a5
    nir_ssa_def *layer = NULL;
0d69a5
-   if (st->pbo.layers && need_layer && (!download || target == PIPE_TEXTURE_1D_ARRAY ||
0d69a5
-                                                     target == PIPE_TEXTURE_2D_ARRAY ||
0d69a5
-                                                     target == PIPE_TEXTURE_3D ||
0d69a5
-                                                     target == PIPE_TEXTURE_CUBE ||
0d69a5
-                                                     target == PIPE_TEXTURE_CUBE_ARRAY)) {
0d69a5
-      nir_variable *var = nir_variable_create(b.shader, nir_var_shader_in,
0d69a5
-                                              glsl_int_type(), "gl_Layer");
0d69a5
-      var->data.location = VARYING_SLOT_LAYER;
0d69a5
-      var->data.interpolation = INTERP_MODE_FLAT;
0d69a5
-      layer = nir_load_var(&b, var);
0d69a5
+   if (st->pbo.layers && (!download || target == PIPE_TEXTURE_1D_ARRAY ||
0d69a5
+                                       target == PIPE_TEXTURE_2D_ARRAY ||
0d69a5
+                                       target == PIPE_TEXTURE_3D ||
0d69a5
+                                       target == PIPE_TEXTURE_CUBE ||
0d69a5
+                                       target == PIPE_TEXTURE_CUBE_ARRAY)) {
0d69a5
+      if (need_layer) {
0d69a5
+         nir_variable *var = nir_variable_create(b.shader, nir_var_shader_in,
0d69a5
+                                                glsl_int_type(), "gl_Layer");
0d69a5
+         var->data.location = VARYING_SLOT_LAYER;
0d69a5
+         var->data.interpolation = INTERP_MODE_FLAT;
0d69a5
+         layer = nir_load_var(&b, var);
0d69a5
+      }
0d69a5
+      else {
0d69a5
+         layer = zero;
0d69a5
+      }
0d69a5
    }
0d69a5
 
0d69a5
    /* offset_pos = param.xy + f2i(coord.xy) */
0d69a5
diff --git a/src/util/format/u_format.csv b/src/util/format/u_format.csv
0d69a5
index 8acfb869bdb..237c4c95475 100644
0d69a5
--- a/src/util/format/u_format.csv
0d69a5
+++ b/src/util/format/u_format.csv
0d69a5
@@ -500,7 +500,7 @@ PIPE_FORMAT_R4G4B4A4_UINT           , plain, 1, 1, 1, up4 , up4 , up4 , up4 , xy
0d69a5
 PIPE_FORMAT_B4G4R4A4_UINT           , plain, 1, 1, 1, up4 , up4 , up4 , up4 , zyxw, rgb, up4 , up4 , up4 , up4 , yzwx
0d69a5
 PIPE_FORMAT_A4R4G4B4_UINT           , plain, 1, 1, 1, up4 , up4 , up4 , up4 , yzwx, rgb, up4 , up4 , up4 , up4 , zyxw
0d69a5
 PIPE_FORMAT_A4B4G4R4_UINT           , plain, 1, 1, 1, up4 , up4 , up4 , up4 , wzyx, rgb, up4 , up4 , up4 , up4 , xyzw
0d69a5
-PIPE_FORMAT_A1R5G5B5_UINT           , plain, 1, 1, 1, up1 , up5 , up5 , up5 , wzyx, rgb, up5 , up5 , up5 , up1 , zyxw
0d69a5
+PIPE_FORMAT_A1R5G5B5_UINT           , plain, 1, 1, 1, up1 , up5 , up5 , up5 , yzwx, rgb, up5 , up5 , up5 , up1 , zyxw
0d69a5
 PIPE_FORMAT_A1B5G5R5_UINT           , plain, 1, 1, 1, up1 , up5 , up5 , up5 , wzyx, rgb, up5 , up5 , up5 , up1 , xyzw
0d69a5
 PIPE_FORMAT_R5G5B5A1_UINT           , plain, 1, 1, 1, up5 , up5 , up5 , up1 , xyzw, rgb, up5 , up5 , up5 , up1 , wzyx
0d69a5
 PIPE_FORMAT_B5G5R5A1_UINT           , plain, 1, 1, 1, up5 , up5 , up5 , up1 , zyxw, rgb, up1 , up5 , up5 , up5 , yzwx
0d69a5
diff --git a/src/vulkan/device-select-layer/VkLayer_MESA_device_select.json b/src/vulkan/device-select-layer/VkLayer_MESA_device_select.json
0d69a5
index 1d5fffd0135..361ae9fe74e 100644
0d69a5
--- a/src/vulkan/device-select-layer/VkLayer_MESA_device_select.json
0d69a5
+++ b/src/vulkan/device-select-layer/VkLayer_MESA_device_select.json
0d69a5
@@ -4,7 +4,7 @@
0d69a5
     "name": "VK_LAYER_MESA_device_select",
0d69a5
     "type": "GLOBAL",
0d69a5
     "library_path": "libVkLayer_MESA_device_select.so",
0d69a5
-    "api_version": "1.1.73",
0d69a5
+    "api_version": "1.2.73",
0d69a5
     "implementation_version": "1",
0d69a5
     "description": "Linux device selection layer",
0d69a5
     "functions": {