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------------------------------------------------------------------------
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r244889 | uweigand | 2015-08-13 15:37:06 +0200 (Thu, 13 Aug 2015) | 22 lines
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[SystemZ] Support large LLVM IR struct return values
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Recent mesa/llvmpipe crashes on SystemZ due to a failed assertion when
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attempting to compile a routine with a return type of
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{ <4 x float>, <4 x float>, <4 x float>, <4 x float> }
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on a system without vector instruction support.
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This is because after legalizing the vector type, we get a return value
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consisting of 16 floats, which cannot all be returned in registers.
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Usually, what should happen in this case is that the target's CanLowerReturn
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routine rejects the return type, in which case SelectionDAG falls back to
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implementing a structure return in memory via implicit reference.
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However, the SystemZ target never actually implemented any CanLowerReturn
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routine, and thus would accept any struct return type.
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This patch fixes the crash by implementing CanLowerReturn. As a side effect,
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this also handles fp128 return values, fixing a todo that was noted in
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SystemZCallingConv.td.
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Index: llvm-36/lib/Target/SystemZ/SystemZCallingConv.td
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===================================================================
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--- llvm-36.orig/lib/Target/SystemZ/SystemZCallingConv.td
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+++ llvm-36/lib/Target/SystemZ/SystemZCallingConv.td
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@@ -53,10 +53,6 @@ def RetCC_SystemZ : CallingConv<[
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[V24, V26, V28, V30, V25, V27, V29, V31]>>>
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-
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- // ABI-compliant code returns long double by reference, but that conversion
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- // is left to higher-level code. Perhaps we could add an f128 definition
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- // here for code that doesn't care about the ABI?
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]>;
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//===----------------------------------------------------------------------===//
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Index: llvm-36/lib/Target/SystemZ/SystemZISelLowering.cpp
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===================================================================
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--- llvm-36.orig/lib/Target/SystemZ/SystemZISelLowering.cpp
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+++ llvm-36/lib/Target/SystemZ/SystemZISelLowering.cpp
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@@ -1169,6 +1169,20 @@ SystemZTargetLowering::LowerCall(CallLow
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return Chain;
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}
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+bool SystemZTargetLowering::
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+CanLowerReturn(CallingConv::ID CallConv,
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+ MachineFunction &MF, bool isVarArg,
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+ const SmallVectorImpl<ISD::OutputArg> &Outs,
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+ LLVMContext &Context) const {
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+ // Detect unsupported vector return types.
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+ if (Subtarget.hasVector())
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+ VerifyVectorTypes(Outs);
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+
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+ SmallVector<CCValAssign, 16> RetLocs;
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+ CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
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+ return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
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+}
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+
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SDValue
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SystemZTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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Index: llvm-36/lib/Target/SystemZ/SystemZISelLowering.h
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===================================================================
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--- llvm-36.orig/lib/Target/SystemZ/SystemZISelLowering.h
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+++ llvm-36/lib/Target/SystemZ/SystemZISelLowering.h
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@@ -401,6 +401,10 @@ public:
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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+ bool isVarArg,
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+ const SmallVectorImpl<ISD::OutputArg> &Outs,
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+ LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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Index: llvm-36/test/CodeGen/SystemZ/args-04.ll
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===================================================================
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--- llvm-36.orig/test/CodeGen/SystemZ/args-04.ll
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+++ llvm-36/test/CodeGen/SystemZ/args-04.ll
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@@ -124,3 +124,17 @@ define void @f13(fp128 *%r2, i16 %r3, i3
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store fp128 %y, fp128 *%r2
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ret void
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}
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+
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+; Explicit fp128 return values are likewise passed indirectly.
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+define fp128 @f14(fp128 %r3) {
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+; CHECK-LABEL: f14:
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+; CHECK: ld %f0, 0(%r3)
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+; CHECK: ld %f2, 8(%r3)
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+; CHECK: axbr %f0, %f0
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+; CHECK: std %f0, 0(%r2)
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+; CHECK: std %f2, 8(%r2)
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+; CHECK: br %r14
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+ %y = fadd fp128 %r3, %r3
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+ ret fp128 %y
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+}
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+
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Index: llvm-36/test/CodeGen/SystemZ/args-07.ll
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===================================================================
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--- /dev/null
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+++ llvm-36/test/CodeGen/SystemZ/args-07.ll
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@@ -0,0 +1,60 @@
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+; Test multiple return values (LLVM ABI extension)
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+;
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+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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+
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+; Up to four integer return values fit into GPRs.
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+define { i64, i64, i64, i64 } @f1() {
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+; CHECK-LABEL: f1:
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+; CHECK: lghi %r2, 0
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+; CHECK: lghi %r3, 1
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+; CHECK: lghi %r4, 2
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+; CHECK: lghi %r5, 3
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+; CHECK: br %r14
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+ ret { i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3 }
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+}
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+
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+; More than four integer return values use sret.
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+define { i64, i64, i64, i64, i64 } @f2() {
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+; CHECK-LABEL: f2:
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+; CHECK: mvghi 32(%r2), 4
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+; CHECK: mvghi 24(%r2), 3
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+; CHECK: mvghi 16(%r2), 2
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+; CHECK: mvghi 8(%r2), 1
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+; CHECK: mvghi 0(%r2), 0
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+; CHECK: br %r14
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+ ret { i64, i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3, i64 4 }
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+}
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+
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+; Up to four floating-point return values fit into FPRs.
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+define { double, double, double, double } @f3() {
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+; CHECK-LABEL: f3:
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: ldeb %f0, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: ldeb %f2, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: ldeb %f4, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: ldeb %f6, 0([[TMP]])
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+; CHECK: br %r14
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+ ret { double, double, double, double }
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+ { double 1.0, double 2.0, double 3.0, double 4.0 }
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+}
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+
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+; More than four floating-point return values use sret.
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+define { double, double, double, double, double } @f4() {
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+; CHECK-LABEL: f4:
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+; CHECK: llihh [[TMP:%r[0-5]]], 16404
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+; CHECK: stg [[TMP]], 32(%r2)
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+; CHECK: llihh [[TMP:%r[0-5]]], 16400
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+; CHECK: stg [[TMP]], 24(%r2)
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+; CHECK: llihh [[TMP:%r[0-5]]], 16392
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+; CHECK: stg [[TMP]], 16(%r2)
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+; CHECK: llihh [[TMP:%r[0-5]]], 16384
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+; CHECK: stg [[TMP]], 8(%r2)
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+; CHECK: llihh [[TMP:%r[0-5]]], 16368
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+; CHECK: stg [[TMP]], 0(%r2)
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+; CHECK: br %r14
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+ ret { double, double, double, double, double }
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+ { double 1.0, double 2.0, double 3.0, double 4.0, double 5.0 }
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+}
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Index: llvm-36/test/CodeGen/SystemZ/args-08.ll
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===================================================================
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--- /dev/null
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+++ llvm-36/test/CodeGen/SystemZ/args-08.ll
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@@ -0,0 +1,57 @@
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+; Test calling functions with multiple return values (LLVM ABI extension)
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+;
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+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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+
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+; Up to four integer return values fit into GPRs.
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+declare { i64, i64, i64, i64 } @bar1()
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+
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+define i64 @f1() {
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+; CHECK-LABEL: f1:
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+; CHECK: brasl %r14, bar1
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+; CHECK: lgr %r2, %r5
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+; CHECK: br %r14
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+ %mret = call { i64, i64, i64, i64 } @bar1()
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+ %ret = extractvalue { i64, i64, i64, i64 } %mret, 3
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+ ret i64 %ret
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+}
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+
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+; More than four integer return values use sret.
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+declare { i64, i64, i64, i64, i64 } @bar2()
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+
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+define i64 @f2() {
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+; CHECK-LABEL: f2:
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+; CHECK: la %r2, 160(%r15)
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+; CHECK: brasl %r14, bar2
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+; CHECK: lg %r2, 192(%r15)
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+; CHECK: br %r14
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+ %mret = call { i64, i64, i64, i64, i64 } @bar2()
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+ %ret = extractvalue { i64, i64, i64, i64, i64 } %mret, 4
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+ ret i64 %ret
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+}
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+
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+; Up to four floating-point return values fit into GPRs.
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+declare { double, double, double, double } @bar3()
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+
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+define double @f3() {
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+; CHECK-LABEL: f3:
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+; CHECK: brasl %r14, bar3
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+; CHECK: ldr %f0, %f6
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+; CHECK: br %r14
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+ %mret = call { double, double, double, double } @bar3()
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+ %ret = extractvalue { double, double, double, double } %mret, 3
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+ ret double %ret
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+}
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+
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+; More than four integer return values use sret.
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+declare { double, double, double, double, double } @bar4()
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+
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+define double @f4() {
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+; CHECK-LABEL: f4:
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+; CHECK: la %r2, 160(%r15)
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+; CHECK: brasl %r14, bar4
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+; CHECK: ld %f0, 192(%r15)
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+; CHECK: br %r14
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+ %mret = call { double, double, double, double, double } @bar4()
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+ %ret = extractvalue { double, double, double, double, double } %mret, 4
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+ ret double %ret
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+}
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Index: llvm-36/test/CodeGen/SystemZ/vec-args-06.ll
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===================================================================
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--- /dev/null
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+++ llvm-36/test/CodeGen/SystemZ/vec-args-06.ll
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@@ -0,0 +1,83 @@
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+; Test multiple return values (LLVM ABI extension)
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+;
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+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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+
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+; Up to eight vector return values fit into VRs.
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+define { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
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+ <2 x double>, <2 x double>, <2 x double>, <2 x double> } @f1() {
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+; CHECK-LABEL: f1:
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v24, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v26, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v28, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v30, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v25, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v27, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v29, 0([[TMP]])
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl %v31, 0([[TMP]])
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+; CHECK: br %r14
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+ ret { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
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+ <2 x double>, <2 x double>, <2 x double>, <2 x double> }
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+ { <2 x double> <double 1.0, double 1.1>,
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+ <2 x double> <double 2.0, double 2.1>,
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+ <2 x double> <double 3.0, double 3.1>,
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+ <2 x double> <double 4.0, double 4.1>,
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+ <2 x double> <double 5.0, double 5.1>,
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+ <2 x double> <double 6.0, double 6.1>,
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+ <2 x double> <double 7.0, double 7.1>,
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+ <2 x double> <double 8.0, double 8.1> }
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+}
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+
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+; More than eight vector return values use sret.
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+define { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
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+ <2 x double>, <2 x double>, <2 x double>, <2 x double>,
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+ <2 x double> } @f2() {
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+; CHECK-LABEL: f2:
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 128(%r2)
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 112(%r2)
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 96(%r2)
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+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 80(%r2)
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003ced |
+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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003ced |
+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 64(%r2)
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003ced |
+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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003ced |
+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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+; CHECK: vst [[VTMP]], 48(%r2)
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003ced |
+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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003ced |
+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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003ced |
+; CHECK: vst [[VTMP]], 32(%r2)
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003ced |
+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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|
003ced |
+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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|
003ced |
+; CHECK: vst [[VTMP]], 16(%r2)
|
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|
003ced |
+; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
|
|
003ced |
+; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
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|
003ced |
+; CHECK: vst [[VTMP]], 0(%r2)
|
|
|
003ced |
+; CHECK: br %r14
|
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003ced |
+ ret { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
|
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+ <2 x double>, <2 x double>, <2 x double>, <2 x double>,
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003ced |
+ <2 x double> }
|
|
|
003ced |
+ { <2 x double> <double 1.0, double 1.1>,
|
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|
003ced |
+ <2 x double> <double 2.0, double 2.1>,
|
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|
003ced |
+ <2 x double> <double 3.0, double 3.1>,
|
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|
003ced |
+ <2 x double> <double 4.0, double 4.1>,
|
|
|
003ced |
+ <2 x double> <double 5.0, double 5.1>,
|
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|
003ced |
+ <2 x double> <double 6.0, double 6.1>,
|
|
|
003ced |
+ <2 x double> <double 7.0, double 7.1>,
|
|
|
003ced |
+ <2 x double> <double 8.0, double 8.1>,
|
|
|
003ced |
+ <2 x double> <double 9.0, double 9.1> }
|
|
|
003ced |
+}
|
|
|
003ced |
Index: llvm-36/test/CodeGen/SystemZ/vec-args-07.ll
|
|
|
003ced |
===================================================================
|
|
|
003ced |
--- /dev/null
|
|
|
003ced |
+++ llvm-36/test/CodeGen/SystemZ/vec-args-07.ll
|
|
|
003ced |
@@ -0,0 +1,47 @@
|
|
|
003ced |
+; Test calling functions with multiple return values (LLVM ABI extension)
|
|
|
003ced |
+;
|
|
|
003ced |
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
|
|
|
003ced |
+
|
|
|
003ced |
+; Up to eight vector return values fit into VRs.
|
|
|
003ced |
+declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>, <2 x double>, <2 x double> } @bar1()
|
|
|
003ced |
+
|
|
|
003ced |
+define <2 x double> @f1() {
|
|
|
003ced |
+; CHECK-LABEL: f1:
|
|
|
003ced |
+; CHECK: brasl %r14, bar1
|
|
|
003ced |
+; CHECK: vlr %v24, %v31
|
|
|
003ced |
+; CHECK: br %r14
|
|
|
003ced |
+ %mret = call { <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double> } @bar1()
|
|
|
003ced |
+ %ret = extractvalue { <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double> } %mret, 7
|
|
|
003ced |
+ ret <2 x double> %ret
|
|
|
003ced |
+}
|
|
|
003ced |
+
|
|
|
003ced |
+; More than eight vector return values use sret.
|
|
|
003ced |
+declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>, <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double> } @bar2()
|
|
|
003ced |
+
|
|
|
003ced |
+define <2 x double> @f2() {
|
|
|
003ced |
+; CHECK-LABEL: f2:
|
|
|
003ced |
+; CHECK: la %r2, 160(%r15)
|
|
|
003ced |
+; CHECK: brasl %r14, bar2
|
|
|
003ced |
+; CHECK: vl %v24, 288(%r15)
|
|
|
003ced |
+; CHECK: br %r14
|
|
|
003ced |
+ %mret = call { <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double> } @bar2()
|
|
|
003ced |
+ %ret = extractvalue { <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double>, <2 x double>,
|
|
|
003ced |
+ <2 x double> } %mret, 8
|
|
|
003ced |
+ ret <2 x double> %ret
|
|
|
003ced |
+}
|