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From 29cf3bd00fe84ddab138c9311fe288bb9da8a273 Mon Sep 17 00:00:00 2001
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From: root <root@mammon-seattle-raw.austin.arm.com>
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Date: Thu, 9 Mar 2017 12:22:48 -0600
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Subject: [PATCH] Fix R_AARCH64_MOVW_UABS_G3 relocation
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Summary: The relocation is missing mask so an address that
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has non-zero bits in 47:43 may overwrite the register
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number. (Frequently shows up as target register changed
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to xzr....)
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Reviewers: t.p.northover, lhames
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Subscribers: davide, aemerson, rengolin, llvm-commits
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Differential Revision: https://reviews.llvm.org/D27609
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---
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llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h | 2 +-
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llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h | 1 +
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.../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 67 +++++++++-----
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.../RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s | 102 +++++++++++++++++++++
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.../RuntimeDyld/AArch64/ELF_ARM64_relocations.s | 99 ++++++++++++++++++++
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5 files changed, 249 insertions(+), 22 deletions(-)
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create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
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create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
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diff --git a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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index 07c6364..d3b83f9 100644
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--- a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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+++ b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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@@ -907,7 +907,7 @@ unsigned ELFObjectFile<ELFT>::getArch() const {
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case ELF::EM_X86_64:
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return Triple::x86_64;
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case ELF::EM_AARCH64:
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- return Triple::aarch64;
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+ return IsLittleEndian ? Triple::aarch64 : Triple::aarch64_be;
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case ELF::EM_ARM:
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return Triple::arm;
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case ELF::EM_AVR:
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diff --git a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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index 5e0df98..b59e8ec 100644
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--- a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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+++ b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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@@ -86,6 +86,7 @@ private:
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return RelocToApply();
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}
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case Triple::aarch64:
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+ case Triple::aarch64_be:
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switch (RelocType) {
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case llvm::ELF::R_AARCH64_ABS32:
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return visitELF_AARCH64_ABS32(R, Value);
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diff --git a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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index 9cbdb13..9e04b5d 100644
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--- a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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+++ b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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@@ -309,6 +309,8 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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uint32_t *TargetPtr =
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reinterpret_cast<uint32_t *>(Section.getAddressWithOffset(Offset));
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uint64_t FinalAddress = Section.getLoadAddressWithOffset(Offset);
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+ // Data should use target endian. Code should always use little endian.
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+ bool isBE = Arch == Triple::aarch64_be;
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DEBUG(dbgs() << "resolveAArch64Relocation, LocalAddress: 0x"
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<< format("%llx", Section.getAddressWithOffset(Offset))
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@@ -324,14 +326,22 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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case ELF::R_AARCH64_ABS64: {
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uint64_t *TargetPtr =
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reinterpret_cast<uint64_t *>(Section.getAddressWithOffset(Offset));
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- *TargetPtr = Value + Addend;
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+ if (isBE)
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+ support::ubig64_t::ref{TargetPtr} = Value + Addend;
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+ else
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+ support::ulittle64_t::ref{TargetPtr} = Value + Addend;
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break;
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}
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case ELF::R_AARCH64_PREL32: {
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uint64_t Result = Value + Addend - FinalAddress;
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assert(static_cast<int64_t>(Result) >= INT32_MIN &&
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static_cast<int64_t>(Result) <= UINT32_MAX);
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- *TargetPtr = static_cast<uint32_t>(Result & 0xffffffffU);
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+ if (isBE)
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+ support::ubig32_t::ref{TargetPtr} =
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+ static_cast<uint32_t>(Result & 0xffffffffU);
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+ else
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+ support::ulittle32_t::ref{TargetPtr} =
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+ static_cast<uint32_t>(Result & 0xffffffffU);
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break;
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}
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case ELF::R_AARCH64_CALL26: // fallthrough
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@@ -339,6 +349,7 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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// Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the
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// calculation.
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uint64_t BranchImm = Value + Addend - FinalAddress;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// "Check that -2^27 <= result < 2^27".
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assert(isInt<28>(BranchImm));
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@@ -352,91 +363,105 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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}
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case ELF::R_AARCH64_MOVW_UABS_G3: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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- *TargetPtr |= Result >> (48 - 5);
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+ TargetValue |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
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// Shift must be "lsl #48", in bits 22:21
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- assert((*TargetPtr >> 21 & 0x3) == 3 && "invalid shift for relocation");
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+ assert((TargetValue >> 21 & 0x3) == 3 && "invalid shift for relocation");
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G2_NC: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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- *TargetPtr |= ((Result & 0xffff00000000ULL) >> (32 - 5));
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+ TargetValue |= ((Result & 0xffff00000000ULL) >> (32 - 5));
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// Shift must be "lsl #32", in bits 22:21
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- assert((*TargetPtr >> 21 & 0x3) == 2 && "invalid shift for relocation");
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+ assert((TargetValue >> 21 & 0x3) == 2 && "invalid shift for relocation");
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G1_NC: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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- *TargetPtr |= ((Result & 0xffff0000U) >> (16 - 5));
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+ TargetValue |= ((Result & 0xffff0000U) >> (16 - 5));
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// Shift must be "lsl #16", in bits 22:2
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- assert((*TargetPtr >> 21 & 0x3) == 1 && "invalid shift for relocation");
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+ assert((TargetValue >> 21 & 0x3) == 1 && "invalid shift for relocation");
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G0_NC: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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- *TargetPtr |= ((Result & 0xffffU) << 5);
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+ TargetValue |= ((Result & 0xffffU) << 5);
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// Shift must be "lsl #0", in bits 22:21.
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- assert((*TargetPtr >> 21 & 0x3) == 0 && "invalid shift for relocation");
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+ assert((TargetValue >> 21 & 0x3) == 0 && "invalid shift for relocation");
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
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// Operation: Page(S+A) - Page(P)
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uint64_t Result =
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((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// Check that -2^32 <= X < 2^32
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assert(isInt<33>(Result) && "overflow check failed for relocation");
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0x9f00001fU;
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+ TargetValue &= 0x9f00001fU;
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// Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
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// from bits 32:12 of X.
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- *TargetPtr |= ((Result & 0x3000U) << (29 - 12));
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- *TargetPtr |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
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+ TargetValue |= ((Result & 0x3000U) << (29 - 12));
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+ TargetValue |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
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// Operation: S + A
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffc003ffU;
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+ TargetValue &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:2 of X
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- *TargetPtr |= ((Result & 0xffc) << (10 - 2));
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+ TargetValue |= ((Result & 0xffc) << (10 - 2));
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
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// Operation: S + A
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffc003ffU;
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+ TargetValue &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:3 of X
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- *TargetPtr |= ((Result & 0xff8) << (10 - 3));
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+ TargetValue |= ((Result & 0xff8) << (10 - 3));
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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}
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diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
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new file mode 100644
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index 0000000..01d01e5
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--- /dev/null
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+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
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@@ -0,0 +1,102 @@
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+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
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+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
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+
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+ .text
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+ .globl g
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+ .p2align 2
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+ .type g,@function
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+g:
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+# R_AARCH64_MOVW_UABS_G3
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+ movz x0, #:abs_g3:f
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+# R_AARCH64_MOVW_UABS_G2_NC
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+ movk x0, #:abs_g2_nc:f
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+# R_AARCH64_MOVW_UABS_G1_NC
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+ movk x0, #:abs_g1_nc:f
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+# R_AARCH64_MOVW_UABS_G0_NC
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+ movk x0, #:abs_g0_nc:f
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+ ret
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+ .Lfunc_end0:
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+ .size g, .Lfunc_end0-g
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+
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+ .type k,@object
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+ .data
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+ .globl k
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+ .p2align 3
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+k:
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+ .xword f
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+ .size k, 8
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|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# LE instructions read as BE
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
|
|
|
4cbaf7 |
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .text
|
|
|
4cbaf7 |
+ .globl g
|
|
|
4cbaf7 |
+ .p2align 2
|
|
|
4cbaf7 |
+ .type g,@function
|
|
|
4cbaf7 |
+g:
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G3
|
|
|
4cbaf7 |
+ movz x0, #:abs_g3:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G2_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g2_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G1_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g1_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G0_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g0_nc:f
|
|
|
4cbaf7 |
+ ret
|
|
|
4cbaf7 |
+ .Lfunc_end0:
|
|
|
4cbaf7 |
+ .size g, .Lfunc_end0-g
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .type k,@object
|
|
|
4cbaf7 |
+ .data
|
|
|
4cbaf7 |
+ .globl k
|
|
|
4cbaf7 |
+ .p2align 3
|
|
|
4cbaf7 |
+k:
|
|
|
4cbaf7 |
+ .xword f
|
|
|
4cbaf7 |
+ .size k, 8
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# LE instructions read as BE
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
|
|
|
4cbaf7 |
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .text
|
|
|
4cbaf7 |
+ .globl g
|
|
|
4cbaf7 |
+ .p2align 2
|
|
|
4cbaf7 |
+ .type g,@function
|
|
|
4cbaf7 |
+g:
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G3
|
|
|
4cbaf7 |
+ movz x0, #:abs_g3:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G2_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g2_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G1_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g1_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G0_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g0_nc:f
|
|
|
4cbaf7 |
+ ret
|
|
|
4cbaf7 |
+ .Lfunc_end0:
|
|
|
4cbaf7 |
+ .size g, .Lfunc_end0-g
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .type k,@object
|
|
|
4cbaf7 |
+ .data
|
|
|
4cbaf7 |
+ .globl k
|
|
|
4cbaf7 |
+ .p2align 3
|
|
|
4cbaf7 |
+k:
|
|
|
4cbaf7 |
+ .xword f
|
|
|
4cbaf7 |
+ .size k, 8
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# LE instructions read as BE
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
|
|
|
4cbaf7 |
new file mode 100644
|
|
|
4cbaf7 |
index 0000000..e07fa97
|
|
|
4cbaf7 |
--- /dev/null
|
|
|
4cbaf7 |
+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
|
|
|
4cbaf7 |
@@ -0,0 +1,99 @@
|
|
|
4cbaf7 |
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
|
|
4cbaf7 |
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .text
|
|
|
4cbaf7 |
+ .globl g
|
|
|
4cbaf7 |
+ .p2align 2
|
|
|
4cbaf7 |
+ .type g,@function
|
|
|
4cbaf7 |
+g:
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G3
|
|
|
4cbaf7 |
+ movz x0, #:abs_g3:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G2_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g2_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G1_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g1_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G0_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g0_nc:f
|
|
|
4cbaf7 |
+ ret
|
|
|
4cbaf7 |
+ .Lfunc_end0:
|
|
|
4cbaf7 |
+ .size g, .Lfunc_end0-g
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .type k,@object
|
|
|
4cbaf7 |
+ .data
|
|
|
4cbaf7 |
+ .globl k
|
|
|
4cbaf7 |
+ .p2align 3
|
|
|
4cbaf7 |
+k:
|
|
|
4cbaf7 |
+ .xword f
|
|
|
4cbaf7 |
+ .size k, 8
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
|
|
4cbaf7 |
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .text
|
|
|
4cbaf7 |
+ .globl g
|
|
|
4cbaf7 |
+ .p2align 2
|
|
|
4cbaf7 |
+ .type g,@function
|
|
|
4cbaf7 |
+g:
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G3
|
|
|
4cbaf7 |
+ movz x0, #:abs_g3:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G2_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g2_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G1_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g1_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G0_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g0_nc:f
|
|
|
4cbaf7 |
+ ret
|
|
|
4cbaf7 |
+ .Lfunc_end0:
|
|
|
4cbaf7 |
+ .size g, .Lfunc_end0-g
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .type k,@object
|
|
|
4cbaf7 |
+ .data
|
|
|
4cbaf7 |
+ .globl k
|
|
|
4cbaf7 |
+ .p2align 3
|
|
|
4cbaf7 |
+k:
|
|
|
4cbaf7 |
+ .xword f
|
|
|
4cbaf7 |
+ .size k, 8
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
|
|
4cbaf7 |
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .text
|
|
|
4cbaf7 |
+ .globl g
|
|
|
4cbaf7 |
+ .p2align 2
|
|
|
4cbaf7 |
+ .type g,@function
|
|
|
4cbaf7 |
+g:
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G3
|
|
|
4cbaf7 |
+ movz x0, #:abs_g3:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G2_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g2_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G1_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g1_nc:f
|
|
|
4cbaf7 |
+# R_AARCH64_MOVW_UABS_G0_NC
|
|
|
4cbaf7 |
+ movk x0, #:abs_g0_nc:f
|
|
|
4cbaf7 |
+ ret
|
|
|
4cbaf7 |
+ .Lfunc_end0:
|
|
|
4cbaf7 |
+ .size g, .Lfunc_end0-g
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+ .type k,@object
|
|
|
4cbaf7 |
+ .data
|
|
|
4cbaf7 |
+ .globl k
|
|
|
4cbaf7 |
+ .p2align 3
|
|
|
4cbaf7 |
+k:
|
|
|
4cbaf7 |
+ .xword f
|
|
|
4cbaf7 |
+ .size k, 8
|
|
|
4cbaf7 |
+
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
|
|
4cbaf7 |
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
|
|
4cbaf7 |
+# rtdyld-check: *{8}k = f
|
|
|
4cbaf7 |
--
|
|
|
4cbaf7 |
2.12.0
|
|
|
4cbaf7 |
|