Blame SOURCES/mcelog-patch-595a2dcfe.patch
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diff -urNp mcelog-d2e13bf0.orig/mcelog.c mcelog-d2e13bf0/mcelog.c
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--- mcelog-d2e13bf0.orig/mcelog.c 2018-06-28 11:53:15.907862669 -0400
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+++ mcelog-d2e13bf0/mcelog.c 2018-06-28 11:54:56.247852219 -0400
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@@ -446,6 +446,9 @@ static void dump_mce(struct mce *m, unsi
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if (recordlen >= offsetof(struct mce, ppin) && m->ppin)
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n += Wprintf("PPIN %llx\n", m->ppin);
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+ if (recordlen > offsetof(struct mce, microcode) && m->microcode)
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+ n += Wprintf("MICROCODE %x\n", m->microcode);
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+
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if (recordlen >= offsetof(struct mce, cpuid) && m->cpuid) {
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u32 fam, mod;
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parse_cpuid(m->cpuid, &fam, &mod);
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diff -urNp mcelog-d2e13bf0.orig/mcelog.h mcelog-d2e13bf0/mcelog.h
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--- mcelog-d2e13bf0.orig/mcelog.h 2018-06-28 11:53:15.908862699 -0400
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+++ mcelog-d2e13bf0/mcelog.h 2018-06-28 11:54:04.754318009 -0400
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@@ -34,6 +34,7 @@ struct mce {
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__u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */
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__u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */
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__u64 ppin; /* Protected Processor Inventory Number */
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+ __u32 microcode;/* Microcode revision */
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};
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#define X86_VENDOR_INTEL 0
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