From 489df948529168392fcf990c68724c03fb9164f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nikola=20Forr=C3=B3?= Date: Tue, 28 Jun 2016 11:10:13 +0200 Subject: [PATCH 02/17] libpaf-dsc.3, libpaf-ebb.3: fix formatting and examples --- paflib/man3/libpaf-dsc.3 | 18 ++++++------------ paflib/man3/libpaf-ebb.3 | 4 ++-- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/paflib/man3/libpaf-dsc.3 b/paflib/man3/libpaf-dsc.3 index 201441f..e1c4ae4 100644 --- a/paflib/man3/libpaf-dsc.3 +++ b/paflib/man3/libpaf-dsc.3 @@ -52,47 +52,40 @@ available on Power Architecture. This register follows the layout specified in the corresponding Power ISA, with the following defined flags. These are features supported by Power ISA 2.05: -.TP +.LP .IP \[bu] 2 .BR DSCR_SSE Store Stream Enable. -.PP +.LP These features were added on Power ISA 2.06: -.TP .IP \[bu] 2 .BR DSCR_SNSE Stride-N Stream Enable. -.PP + +.LP These features were added on Power ISA 2.06+: -.TP .IP \[bu] 2 .BR DSCR_LSD Load Stream Disable. -.PP +.LP These are supported only on Power ISA 2.07: -.TP .IP \[bu] 2 .BR DSCR_HWUE Hardware Unit count Enable. -.TP .IP \[bu] 2 .BR DSCR_SWUE Software Unit count Enable. -.TP .IP \[bu] .BR DSCR_LTE Load Transient Enable. -.TP .IP \[bu] .BR DSCR_STE Software Transient Enable. -.TP .IP \[bu] .BR DSCR_HTE Hardware Transient Enable. -.TP .IP \[bu] .BR DSCR_SWTE Software Transient Enable. @@ -201,6 +194,7 @@ if the system does not support DSCR facility. .nf #include #include +#include int main(void) { diff --git a/paflib/man3/libpaf-ebb.3 b/paflib/man3/libpaf-ebb.3 index eb6cd2e..87460a6 100644 --- a/paflib/man3/libpaf-ebb.3 +++ b/paflib/man3/libpaf-ebb.3 @@ -200,7 +200,7 @@ void do_work (void) } } -int _do_ebb(void) +int do_ebb(void) { ebbhandler_t handler; ebb_handler_triggered = 0; @@ -223,7 +223,7 @@ int _do_ebb(void) paf_ebb_disable_branches (); - printf ("Done; %d EBB interrupts handled\n", ebb_handler_triggered); + printf ("Done; %d EBB interrupts handled\\n", ebb_handler_triggered); close (ebb_fd); -- 2.7.4