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From 69bb97a917250d0d299c4aa3d03bde9513351159 Mon Sep 17 00:00:00 2001
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From: Tom Stellard <tstellar@redhat.com>
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Date: Mon, 9 Jul 2018 10:35:30 -0700
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Subject: [PATCH] Don't run BV DAG Combine before legalization if it assumes legal types
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---
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lib/Target/PowerPC/PPCISelLowering.cpp | 13 ++++++++++---
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1 file changed, 10 insertions(+), 3 deletions(-)
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diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
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index 4966e88..378e494 100644
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--- a/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -11923,10 +11923,15 @@ static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) {
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auto isSExtOfVecExtract = [&](SDValue Op) -> bool {
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if (!Op)
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return false;
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- if (Op.getOpcode() != ISD::SIGN_EXTEND)
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+ if (Op.getOpcode() != ISD::SIGN_EXTEND &&
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+ Op.getOpcode() != ISD::SIGN_EXTEND_INREG)
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return false;
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+ // A SIGN_EXTEND_INREG might be fed by an ANY_EXTEND to produce a value
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+ // of the right width.
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SDValue Extract = Op.getOperand(0);
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+ if (Extract.getOpcode() == ISD::ANY_EXTEND)
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+ Extract = Extract.getOperand(0);
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if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return false;
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@@ -12014,8 +12019,10 @@ SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
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return Reduced;
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// If we're building a vector out of extended elements from another vector
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- // we have P9 vector integer extend instructions.
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- if (Subtarget.hasP9Altivec()) {
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+ // we have P9 vector integer extend instructions. The code assumes legal
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+ // input types (i.e. it can't handle things like v4i16) so do not run before
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+ // legalization.
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+ if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) {
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Reduced = combineBVOfVecSExt(N, DAG);
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if (Reduced)
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return Reduced;
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--
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1.8.3.1
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