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From 0a192b453da043cfb3679a07b55c1628b56efdde Mon Sep 17 00:00:00 2001
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Message-Id: <0a192b453da043cfb3679a07b55c1628b56efdde@dist-git>
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From: Michal Privoznik <mprivozn@redhat.com>
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Date: Fri, 8 Jul 2022 14:29:32 +0200
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Subject: [PATCH] vircpi: Add PCIe 5.0 and 6.0 link speeds
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The PCIe 5.0 and PCIe 6.0 standards define new link speeds:
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32GT/s and 64GT/s, respectively. Update our internal enum to
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include these new speeds. Otherwise we format incorrect XML:
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<pci-express>
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<link validity='cap' port='0' speed='(null)' width='16'/>
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<link validity='sta' speed='16' width='16'/>
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</pci-express>
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Like all "good" specifications, these are also locked behind a
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login portal. But we can look at pciutils' source code: [1] and
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[2].
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1: https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/ls-caps.c?id=caca31a0eea41c7b051705704c1158fddc02fbd2
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2: https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/ls-caps.c?id=5bdf63b6b1bc35b59c4b3f47f7ca83ca1868155b
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Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2105231
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Signed-off-by: Michal Privoznik <mprivozn@redhat.com>
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Reviewed-by: Ján Tomko <jtomko@redhat.com>
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(cherry picked from commit d33c2a9e2f933b31f8e96e9938c237bdffe27f84)
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Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2168116
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Signed-off-by: Michal Privoznik <mprivozn@redhat.com>
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---
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src/util/virpci.c | 2 +-
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src/util/virpci.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/src/util/virpci.c b/src/util/virpci.c
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index 0d476cd8b4..4949d1a3d4 100644
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--- a/src/util/virpci.c
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+++ b/src/util/virpci.c
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@@ -46,7 +46,7 @@ VIR_LOG_INIT("util.pci");
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VIR_ENUM_IMPL(virPCIELinkSpeed,
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VIR_PCIE_LINK_SPEED_LAST,
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- "", "2.5", "5", "8", "16",
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+ "", "2.5", "5", "8", "16", "32", "64"
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);
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VIR_ENUM_IMPL(virPCIStubDriver,
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diff --git a/src/util/virpci.h b/src/util/virpci.h
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index b9b9cd7b34..4d9193f24e 100644
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--- a/src/util/virpci.h
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+++ b/src/util/virpci.h
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@@ -83,6 +83,8 @@ typedef enum {
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VIR_PCIE_LINK_SPEED_5,
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VIR_PCIE_LINK_SPEED_8,
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VIR_PCIE_LINK_SPEED_16,
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+ VIR_PCIE_LINK_SPEED_32,
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+ VIR_PCIE_LINK_SPEED_64,
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VIR_PCIE_LINK_SPEED_LAST
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} virPCIELinkSpeed;
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--
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2.39.1
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