diff --git a/SOURCES/libpfm-aarch64.patch b/SOURCES/libpfm-aarch64.patch new file mode 100644 index 0000000..0e23a86 --- /dev/null +++ b/SOURCES/libpfm-aarch64.patch @@ -0,0 +1,2283 @@ +commit b1a3bf942376a3eaddc6f089c74bf5e322295822 +Author: Stephane Eranian +Date: Tue May 6 14:42:23 2014 +0200 + + Add ARM Cortex A57 support + + This patch adds support for ARM Cortex A57 processor + for both 64 and 32 bit modes (armv8). + + Based on Table 11-24 from the "Cortex A57 Technical Reference Manual" + + The validation tests for A57 in 64-bit mode is also added. + + Signed-off-by: Stephane Eranian + +diff --git a/config.mk b/config.mk +index 457d943..9553cbe 100644 +--- a/config.mk ++++ b/config.mk +@@ -66,6 +66,15 @@ endif + ifeq (armv7,$(findstring armv7,$(ARCH))) + override ARCH=arm + endif ++ifeq (armv7,$(findstring armv7,$(ARCH))) ++override ARCH=arm ++endif ++ifeq (aarch32,$(findstring aarch32,$(ARCH))) ++override ARCH=arm ++endif ++ifeq (armv8l,$(findstring armv8l,$(ARCH))) ++override ARCH=arm ++endif + ifeq (mips64,$(findstring mips64,$(ARCH))) + override ARCH=mips + endif +@@ -152,6 +161,14 @@ ifeq ($(ARCH),arm) + CONFIG_PFMLIB_ARCH_ARM=y + endif + ++ifeq ($(ARCH),aarch64) ++CONFIG_PFMLIB_ARCH_ARM64=y ++endif ++ ++ifeq ($(ARCH),arm64) ++CONFIG_PFMLIB_ARCH_ARM64=y ++endif ++ + ifeq ($(ARCH),s390x) + CONFIG_PFMLIB_ARCH_S390X=y + endif +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index dfdd471..b08df66 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -237,6 +237,8 @@ typedef enum { + + PFM_PMU_INTEL_HSW_EP, /* Intel Haswell EP */ + ++ PFM_PMU_ARM_CORTEX_A57, /* ARM Cortex A57 (ARMv8) */ ++ + /* MUST ADD NEW PMU MODELS HERE */ + + PFM_PMU_MAX /* end marker */ +diff --git a/lib/Makefile b/lib/Makefile +index 531167e..6ca3287 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -139,10 +139,21 @@ SRCS += pfmlib_arm_perf_event.c + endif + + INCARCH = $(INC_ARM) +-SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c ++SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c pfmlib_arm_armv8.c + CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM + endif + ++ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) ++ ++ifeq ($(SYS),Linux) ++SRCS += pfmlib_arm_perf_event.c ++endif ++ ++INCARCH = $(INC_ARM64) ++SRCS += pfmlib_arm.c pfmlib_arm_armv8.c ++CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64 ++endif ++ + ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y) + + ifeq ($(SYS),Linux) +@@ -272,6 +283,8 @@ INC_ARM=pfmlib_arm_priv.h \ + events/arm_cortex_a9_events.h \ + events/arm_cortex_a15_events.h + ++INC_ARM64=events/arm_cortex_a57_events.h ++ + INCDEP=$(INC_COMMON) $(INCARCH) + + all: $(TARGETS) +diff --git a/lib/events/arm_cortex_a57_events.h b/lib/events/arm_cortex_a57_events.h +new file mode 100644 +index 0000000..9d1d407 +--- /dev/null ++++ b/lib/events/arm_cortex_a57_events.h +@@ -0,0 +1,440 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Cortex A57 r1p1 ++ * based on Table 11-24 from the "Cortex A57 Technical Reference Manual" ++ */ ++ ++static const arm_entry_t arm_cortex_a57_pe[]={ ++ {.name = "SW_INCR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x00, ++ .desc = "Instruction architecturally executed (condition check pass) Software increment" ++ }, ++ {.name = "L1I_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x01, ++ .desc = "Level 1 instruction cache refill" ++ }, ++ {.name = "L1I_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x02, ++ .desc = "Level 1 instruction TLB refill" ++ }, ++ {.name = "L1D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x03, ++ .desc = "Level 1 data cache refill" ++ }, ++ {.name = "L1D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x04, ++ .desc = "Level 1 data cache access" ++ }, ++ {.name = "L1D_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x05, ++ .desc = "Level 1 data TLB refill" ++ }, ++ ++ {.name = "INST_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x08, ++ .desc = "Instruction architecturally executed" ++ }, ++ {.name = "EXCEPTION_TAKEN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x09, ++ .desc = "Exception taken" ++ }, ++ {.name = "EXCEPTION_RETURN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0a, ++ .desc = "Instruction architecturally executed (condition check pass) Exception return" ++ }, ++ {.name = "CID_WRITE_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0b, ++ .desc = "Instruction architecturally executed (condition check pass) Write to CONTEXTIDR" ++ }, ++ ++ {.name = "BRANCH_MISPRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10, ++ .desc = "Mispredicted or not predicted branch speculatively executed" ++ }, ++ {.name = "CPU_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x11, ++ .desc = "Cycles" ++ }, ++ {.name = "BRANCH_PRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x12, ++ .desc = "Predictable branch speculatively executed" ++ }, ++ {.name = "DATA_MEM_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x13, ++ .desc = "Data memory access" ++ }, ++ {.name = "L1I_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x14, ++ .desc = "Level 1 instruction cache access" ++ }, ++ {.name = "L1D_CACHE_WB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x15, ++ .desc = "Level 1 data cache WriteBack" ++ }, ++ {.name = "L2D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x16, ++ .desc = "Level 2 data cache access" ++ }, ++ {.name = "L2D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x17, ++ .desc = "Level 2 data cache refill" ++ }, ++ {.name = "L2D_CACHE_WB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x18, ++ .desc = "Level 2 data cache WriteBack" ++ }, ++ {.name = "BUS_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x19, ++ .desc = "Bus access" ++ }, ++ {.name = "LOCAL_MEMORY_ERROR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1a, ++ .desc = "Local memory error" ++ }, ++ {.name = "INST_SPEC_EXEC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1b, ++ .desc = "Instruction speculatively executed" ++ }, ++ {.name = "TTBR_WRITE_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1c, ++ .desc = "Instruction architecturally executed (condition check pass) Write to translation table base" ++ }, ++ {.name = "BUS_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1d, ++ .desc = "Bus cycle" ++ }, ++ {.name = "L1D_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x40, ++ .desc = "Level 1 data cache read access" ++ }, ++ {.name = "L1D_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x41, ++ .desc = "Level 1 data cache write access" ++ }, ++ {.name = "L1D_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x42, ++ .desc = "Level 1 data cache read refill" ++ }, ++ {.name = "L1D_WRITE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x43, ++ .desc = "Level 1 data cache write refill" ++ }, ++ {.name = "L1D_WB_VICTIM", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x46, ++ .desc = "Level 1 data cache writeback victim" ++ }, ++ {.name = "L1D_WB_CLEAN_COHERENCY", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x47, ++ .desc = "Level 1 data cache writeback cleaning and coherency" ++ }, ++ {.name = "L1D_INVALIDATE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x48, ++ .desc = "Level 1 data cache invalidate" ++ }, ++ {.name = "L1D_TLB_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x4c, ++ .desc = "Level 1 data TLB read refill" ++ }, ++ {.name = "L1D_TLB_WRITE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x4d, ++ .desc = "Level 1 data TLB write refill" ++ }, ++ {.name = "L2D_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x50, ++ .desc = "Level 2 data cache read access" ++ }, ++ {.name = "L2D_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x51, ++ .desc = "Level 2 data cache write access" ++ }, ++ {.name = "L2D_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x52, ++ .desc = "Level 2 data cache read refill" ++ }, ++ {.name = "L2D_WRITE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x53, ++ .desc = "Level 2 data cache write refill" ++ }, ++ {.name = "L2D_WB_VICTIM", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x56, ++ .desc = "Level 2 data cache writeback victim" ++ }, ++ {.name = "L2D_WB_CLEAN_COHERENCY", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x57, ++ .desc = "Level 2 data cache writeback cleaning and coherency" ++ }, ++ {.name = "L2D_INVALIDATE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x58, ++ .desc = "Level 2 data cache invalidate" ++ }, ++ {.name = "BUS_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x60, ++ .desc = "Bus read access" ++ }, ++ {.name = "BUS_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x61, ++ .desc = "Bus write access" ++ }, ++ {.name = "BUS_NORMAL_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x62, ++ .desc = "Bus normal access" ++ }, ++ {.name = "BUS_NOT_NORMAL_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x63, ++ .desc = "Bus not normal access" ++ }, ++ {.name = "BUS_NORMAL_ACCESS_2", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x64, ++ .desc = "Bus normal access" ++ }, ++ {.name = "BUS_PERIPH_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x65, ++ .desc = "Bus peripheral access" ++ }, ++ {.name = "DATA_MEM_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x66, ++ .desc = "Data memory read access" ++ }, ++ {.name = "DATA_MEM_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x67, ++ .desc = "Data memory write access" ++ }, ++ {.name = "UNALIGNED_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x68, ++ .desc = "Unaligned read access" ++ }, ++ {.name = "UNALIGNED_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x69, ++ .desc = "Unaligned read access" ++ }, ++ {.name = "UNALIGNED_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6a, ++ .desc = "Unaligned access" ++ }, ++ {.name = "INST_SPEC_EXEC_LDREX", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6c, ++ .desc = "LDREX exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STREX_PASS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6d, ++ .desc = "STREX pass exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STREX_FAIL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6e, ++ .desc = "STREX fail exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_LOAD", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x70, ++ .desc = "Load instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STORE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x71, ++ .desc = "Store instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_LOAD_STORE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x72, ++ .desc = "Load or store instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_INTEGER_INST", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x73, ++ .desc = "Integer data processing instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_SIMD", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x74, ++ .desc = "Advanced SIMD instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_VFP", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x75, ++ .desc = "VFP instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_SOFT_PC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x76, ++ .desc = "Software of the PC instruction speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x78, ++ .desc = "Immediate branch speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_RET", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x79, ++ .desc = "Return branch speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_IND", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7a, ++ .desc = "Indirect branch speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_ISB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7c, ++ .desc = "ISB barrier speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_DSB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7d, ++ .desc = "DSB barrier speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_DMB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7e, ++ .desc = "DMB barrier speculatively executed" ++ }, ++ {.name = "EXCEPTION_UNDEF", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x81, ++ .desc = "Exception taken, other synchronous" ++ }, ++ {.name = "EXCEPTION_SVC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x82, ++ .desc = "Exception taken, supervisor call" ++ }, ++ {.name = "EXCEPTION_PABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x83, ++ .desc = "Exception taken, instruction abort" ++ }, ++ {.name = "EXCEPTION_DABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x84, ++ .desc = "Exception taken, data abort or SError" ++ }, ++ {.name = "EXCEPTION_IRQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x86, ++ .desc = "Exception taken, irq" ++ }, ++ {.name = "EXCEPTION_FIQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x87, ++ .desc = "Exception taken, irq" ++ }, ++ {.name = "EXCEPTION_SMC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x88, ++ .desc = "Exception taken, secure monitor call" ++ }, ++ {.name = "EXCEPTION_HVC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8a, ++ .desc = "Exception taken, hypervisor call" ++ }, ++ {.name = "EXCEPTION_TRAP_PABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8b, ++ .desc = "Exception taken, instruction abort not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_DABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8c, ++ .desc = "Exception taken, data abort or SError not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_OTHER", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8d, ++ .desc = "Exception taken, other traps not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_IRQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8e, ++ .desc = "Exception taken, irq not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_FIQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8f, ++ .desc = "Exception taken, fiq not taken locally" ++ }, ++ {.name = "RC_LD_SPEC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x90, ++ .desc = "Release consistency instruction speculatively executed (load-acquire)", ++ }, ++ {.name = "RC_ST_SPEC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x91, ++ .desc = "Release consistency instruction speculatively executed (store-release)", ++ }, ++ /* END Cortex A47 specific events */ ++}; +diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c +new file mode 100644 +index 0000000..880d566 +--- /dev/null ++++ b/lib/pfmlib_arm_armv8.c +@@ -0,0 +1,74 @@ ++/* ++ * pfmlib_arm_armv8.c : support for ARMv8 processors ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" /* library private */ ++#include "pfmlib_arm_priv.h" ++ ++#include "events/arm_cortex_a57_events.h" /* event tables */ ++ ++static int ++pfm_arm_detect_cortex_a57(void *this) ++{ ++ int ret; ++ ++ ret = pfm_arm_detect(this); ++ if (ret != PFM_SUCCESS) ++ return PFM_ERR_NOTSUPP; ++ ++ if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ ++ (pfm_arm_cfg.part == 0xc00)) { /* Cortex A57 */ ++ return PFM_SUCCESS; ++ } ++ return PFM_ERR_NOTSUPP; ++} ++ ++/* ARM Cortex A57 support */ ++pfmlib_pmu_t arm_cortex_a57_support={ ++ .desc = "ARM Cortex A57", ++ .name = "arm_ac57", ++ .pmu = PFM_PMU_ARM_CORTEX_A57, ++ .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a57_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .pe = arm_cortex_a57_pe, ++ ++ .pmu_detect = pfm_arm_detect_cortex_a57, ++ .max_encoding = 1, ++ .num_cntrs = 6, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), ++ .get_event_first = pfm_arm_get_event_first, ++ .get_event_next = pfm_arm_get_event_next, ++ .event_is_valid = pfm_arm_event_is_valid, ++ .validate_table = pfm_arm_validate_table, ++ .get_event_info = pfm_arm_get_event_info, ++ .get_event_attr_info = pfm_arm_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), ++ .get_event_nattrs = pfm_arm_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_arm_priv.h b/lib/pfmlib_arm_priv.h +index ef367b7..227508b 100644 +--- a/lib/pfmlib_arm_priv.h ++++ b/lib/pfmlib_arm_priv.h +@@ -86,6 +86,9 @@ extern int pfm_arm_get_perf_encoding(void *this, pfmlib_event_desc_t *e); + #define ARMV7_A15_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) + #define ARMV7_A15_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) + ++#define ARMV8_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV) ++#define ARMV8_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH) ++ + static inline int + arm_has_plm(void *this, pfmlib_event_desc_t *e) + { +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index 8e4b1a1..900d7de 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -199,7 +199,12 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &arm_cortex_a9_support, + &arm_cortex_a15_support, + &arm_1176_support, ++ &arm_cortex_a57_support, + #endif ++#ifdef CONFIG_PFMLIB_ARCH_ARM64 ++ &arm_cortex_a57_support, ++#endif ++ + #ifdef CONFIG_PFMLIB_ARCH_S390X + &s390x_cpum_cf_support, + #endif +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 715c4b0..3031d3b 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -332,6 +332,7 @@ extern pfmlib_pmu_t arm_cortex_a9_support; + extern pfmlib_pmu_t arm_cortex_a9_support; + extern pfmlib_pmu_t arm_cortex_a15_support; + extern pfmlib_pmu_t arm_1176_support; ++extern pfmlib_pmu_t arm_cortex_a57_support; + extern pfmlib_pmu_t mips_74k_support; + extern pfmlib_pmu_t s390x_cpum_cf_support; + +diff --git a/tests/Makefile b/tests/Makefile +index 7076fb7..7dd82c3 100644 +--- a/tests/Makefile ++++ b/tests/Makefile +@@ -39,6 +39,10 @@ ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) + SRCS += validate_arm.c + endif + ++ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) ++SRCS += validate_arm64.c ++endif ++ + ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y) + SRCS += validate_power.c + endif +diff --git a/tests/validate_arm.c b/tests/validate_arm.c +index fe97aa9..d6c0168 100644 +--- a/tests/validate_arm.c ++++ b/tests/validate_arm.c +@@ -159,6 +159,34 @@ static const test_event_t arm_test_events[]={ + .codes[0] = 0x07, + .fstr = "arm_1176::INSTR_EXEC", + }, ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES:k:u", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(arm_test_events)/sizeof(test_event_t)) + +diff --git a/tests/validate_arm64.c b/tests/validate_arm64.c +new file mode 100644 +index 0000000..0f0174c +--- /dev/null ++++ b/tests/validate_arm64.c +@@ -0,0 +1,138 @@ ++/* ++ * validate_arm64.c - validate ARM64 event tables + encodings ++ * ++ * Copyright (c) 2014 Google, Inc ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define MAX_ENCODING 1 ++#define SRC_LINE .line = __LINE__ ++ ++typedef struct { ++ const char *name; ++ const char *fstr; ++ uint64_t codes[MAX_ENCODING]; ++ int ret, count, line; ++} test_event_t; ++ ++static const test_event_t arm64_test_events[]={ ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::CPU_CYCLES:k:u", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac57::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", ++ }, ++}; ++#define NUM_TEST_EVENTS (int)(sizeof(arm64_test_events)/sizeof(test_event_t)) ++ ++static int check_test_events(FILE *fp) ++{ ++ const test_event_t *e; ++ char *fstr; ++ uint64_t *codes; ++ int count, i, j; ++ int ret, errors = 0; ++ ++ for (i = 0, e = arm64_test_events; i < NUM_TEST_EVENTS; i++, e++) { ++ codes = NULL; ++ count = 0; ++ fstr = NULL; ++ ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); ++ if (ret != e->ret) { ++ fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); ++ errors++; ++ } else { ++ if (ret != PFM_SUCCESS) { ++ if (fstr) { ++ fprintf(fp,"Line %d, Event%d %s, expected fstr NULL but it is not\n", e->line, i, e->name); ++ errors++; ++ } ++ if (count != 0) { ++ fprintf(fp,"Line %d, Event%d %s, expected count=0 instead of %d\n", e->line, i, e->name, count); ++ errors++; ++ } ++ if (codes) { ++ fprintf(fp,"Line %d, Event%d %s, expected codes[] NULL but it is not\n", e->line, i, e->name); ++ errors++; ++ } ++ } else { ++ if (count != e->count) { ++ fprintf(fp,"Line %d, Event%d %s, count=%d expected %d\n", e->line, i, e->name, count, e->count); ++ errors++; ++ } ++ for (j=0; j < count; j++) { ++ if (codes[j] != e->codes[j]) { ++ fprintf(fp,"Line %d, Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", e->line, i, e->name, j, codes[j], e->codes[j]); ++ errors++; ++ } ++ } ++ if (e->fstr && strcmp(fstr, e->fstr)) { ++ fprintf(fp,"Line %d, Event%d %s, fstr=%s expected %s\n", e->line, i, e->name, fstr, e->fstr); ++ errors++; ++ } ++ } ++ } ++ if (codes) ++ free(codes); ++ if (fstr) ++ free(fstr); ++ } ++ printf("\t %d ARM64 events: %d errors\n", i, errors); ++ return errors; ++} ++ ++int ++validate_arch(FILE *fp) ++{ ++ return check_test_events(fp); ++} +commit b95de18085dd74738752341e0004b3dd11f00a53 +Author: Stephane Eranian +Date: Mon May 12 14:15:57 2014 +0200 + + Add ARM Cortex A57 documentation + + Signed-off-by: Stephane Eranian + +diff --git a/docs/Makefile b/docs/Makefile +index ecf6769..9b79ec7 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -76,7 +76,11 @@ endif + endif + + ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) +-ARCH_MAN += libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 ++ARCH_MAN += libpfm_arm_ac57.3 libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 ++endif ++ ++ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) ++ARCH_MAN += libpfm_arm_ac57.3 + endif + + +diff --git a/docs/man3/libpfm_arm_ac57.3 b/docs/man3/libpfm_arm_ac57.3 +new file mode 100644 +index 0000000..c471ff1 +--- /dev/null ++++ b/docs/man3/libpfm_arm_ac57.3 +@@ -0,0 +1,36 @@ ++.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_arm_ac57 - support for Arm Cortex A57 PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: arm_ac57 ++.B PMU desc: ARM Cortex A57 ++.sp ++.SH DESCRIPTION ++The library supports the ARM Cortex A57 core PMU. ++ ++This PMU supports 6 counters and privilege levels filtering. ++It can operate in both 32 and 64 bit modes. ++ ++.SH MODIFIERS ++The following modifiers are supported on ARM Cortex A57: ++.TP ++.B u ++Measure at the user level. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B hv ++Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. ++This is a boolean modifier. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +commit 399aa947ca6f4c58acac8c6be52d2ad4e5268210 +Author: Stephane Eranian +Date: Fri May 16 15:42:40 2014 +0200 + + fix the ARM Cortex A57 detection + + This patch fixes the detection of ARM Cortex A57. + Was using the wrong part number. Correct number + is 0xD07. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c +index 880d566..4bc863b 100644 +--- a/lib/pfmlib_arm_armv8.c ++++ b/lib/pfmlib_arm_armv8.c +@@ -42,7 +42,7 @@ pfm_arm_detect_cortex_a57(void *this) + return PFM_ERR_NOTSUPP; + + if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ +- (pfm_arm_cfg.part == 0xc00)) { /* Cortex A57 */ ++ (pfm_arm_cfg.part == 0xd07)) { /* Cortex A57 */ + return PFM_SUCCESS; + } + return PFM_ERR_NOTSUPP; +commit 6d1faa5bd1c0564b24cf030f118cd9782e1b4e0c +Author: Stephane Eranian +Date: Thu May 22 18:44:47 2014 +0200 + + Add missing arm_cortex_a57.h header dependency + + Was missing. We compile A57 for 32-bit arm as well. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/Makefile b/lib/Makefile +index 6ca3287..585cc3e 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -281,7 +281,8 @@ INC_ARM=events/arm_cortex_a8_events.h \ + INC_ARM=pfmlib_arm_priv.h \ + events/arm_cortex_a8_events.h \ + events/arm_cortex_a9_events.h \ +- events/arm_cortex_a15_events.h ++ events/arm_cortex_a15_events.h \ ++ events/arm_cortex_a57_events.h + + INC_ARM64=events/arm_cortex_a57_events.h + +commit 6af79d5186b7593c4f7e41024b78453debceb45f +Author: Stephane Eranian +Date: Thu May 22 19:14:52 2014 +0200 + + Add ARM Cortex A53 support + + This patch adds support for the ARM Cortex A53 core PMU as + documented in r0p2 version f the Cortex-A53 MPCore processor + technical reference manual Table 12.28. + + Support is provided for both 32 and 64-bit modes. + + Includes man page, and validation tests. + + Signed-off-by: Stephane Eranian + +diff --git a/README b/README +index 334c78a..e74238f 100644 +--- a/README ++++ b/README +@@ -57,6 +57,7 @@ The library supports many PMUs. The current version can handle: + ARMV7 Cortex A8 + ARMV7 Cortex A9 + ARMV7 Cortex A15 ++ ARMV8 Cortex A57, A53 + + - For SPARC + Ultra I, II +diff --git a/docs/Makefile b/docs/Makefile +index 9b79ec7..c7d797e 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -76,11 +76,16 @@ endif + endif + + ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) +-ARCH_MAN += libpfm_arm_ac57.3 libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 ++ARCH_MAN += libpfm_arm_ac57.3 \ ++ libpfm_arm_ac53.3 \ ++ libpfm_arm_ac15.3 \ ++ libpfm_arm_ac8.3 \ ++ libpfm_arm_ac9.3 + endif + + ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) +-ARCH_MAN += libpfm_arm_ac57.3 ++ARCH_MAN += libpfm_arm_ac57.3 \ ++ libpfm_arm_ac53.3 + endif + + +diff --git a/docs/man3/libpfm_arm_ac53.3 b/docs/man3/libpfm_arm_ac53.3 +new file mode 100644 +index 0000000..319accc +--- /dev/null ++++ b/docs/man3/libpfm_arm_ac53.3 +@@ -0,0 +1,36 @@ ++.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_arm_ac53 - support for ARM Cortex A53 PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: arm_ac53 ++.B PMU desc: ARM Cortex A53 ++.sp ++.SH DESCRIPTION ++The library supports the ARM Cortex A53 core PMU. ++ ++This PMU supports 6 counters and privilege levels filtering. ++It can operate in both 32 and 64 bit modes. ++ ++.SH MODIFIERS ++The following modifiers are supported on ARM Cortex A53: ++.TP ++.B u ++Measure at the user level. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B hv ++Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. ++This is a boolean modifier. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index b08df66..a7ec026 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -238,6 +238,7 @@ typedef enum { + PFM_PMU_INTEL_HSW_EP, /* Intel Haswell EP */ + + PFM_PMU_ARM_CORTEX_A57, /* ARM Cortex A57 (ARMv8) */ ++ PFM_PMU_ARM_CORTEX_A53, /* ARM Cortex A53 (ARMv8) */ + + /* MUST ADD NEW PMU MODELS HERE */ + +diff --git a/lib/Makefile b/lib/Makefile +index 585cc3e..5aaf4b3 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -282,9 +282,11 @@ INC_ARM=pfmlib_arm_priv.h \ + events/arm_cortex_a8_events.h \ + events/arm_cortex_a9_events.h \ + events/arm_cortex_a15_events.h \ +- events/arm_cortex_a57_events.h ++ events/arm_cortex_a57_events.h \ ++ events/arm_cortex_a53_events.h + +-INC_ARM64=events/arm_cortex_a57_events.h ++INC_ARM64=events/arm_cortex_a57_events.h \ ++ events/arm_cortex_a53_events.h + + INCDEP=$(INC_COMMON) $(INCARCH) + +diff --git a/lib/events/arm_cortex_a53_events.h b/lib/events/arm_cortex_a53_events.h +new file mode 100644 +index 0000000..c0d2bb6 +--- /dev/null ++++ b/lib/events/arm_cortex_a53_events.h +@@ -0,0 +1,190 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Cortex A53 r0p2 ++ * based on Table 12.9 from the "Cortex A53 Technical Reference Manual" ++ */ ++ ++static const arm_entry_t arm_cortex_a53_pe[]={ ++ {.name = "SW_INCR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x00, ++ .desc = "Instruction architecturally executed (condition check pass) Software increment" ++ }, ++ {.name = "L1I_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x01, ++ .desc = "Level 1 instruction cache refill" ++ }, ++ {.name = "L1I_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x02, ++ .desc = "Level 1 instruction TLB refill" ++ }, ++ {.name = "L1D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x03, ++ .desc = "Level 1 data cache refill" ++ }, ++ {.name = "L1D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x04, ++ .desc = "Level 1 data cache access" ++ }, ++ {.name = "L1D_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x05, ++ .desc = "Level 1 data TLB refill" ++ }, ++ {.name = "LD_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x06, ++ .desc = "Load Instruction architecturally executed, condition check", ++ }, ++ {.name = "ST_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x07, ++ .desc = "Store Instruction architecturally executed, condition check", ++ }, ++ {.name = "INST_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x08, ++ .desc = "Instruction architecturally executed" ++ }, ++ {.name = "EXCEPTION_TAKEN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x09, ++ .desc = "Exception taken" ++ }, ++ {.name = "EXCEPTION_RETURN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0a, ++ .desc = "Instruction architecturally executed (condition check pass) Exception return" ++ }, ++ {.name = "CID_WRITE_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0b, ++ .desc = "Change to Context ID retired", ++ }, ++ {.name = "PC_WRITE_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0c, ++ .desc = "Write to CONTEXTIDR, instruction architecturally executed, condition check pass" ++ }, ++ {.name = "BR_IMMED_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0d, ++ .desc = "Software chnage of the PC, instruction architecturally executed, condition check pass" ++ }, ++ {.name = "UNALIGNED_LDST_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0f, ++ .desc = "Procedure return, instruction architecturally executed, condition check pass" ++ }, ++ {.name = "BRANCH_MISPRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10, ++ .desc = "Mispredicted or not predicted branch speculatively executed" ++ }, ++ {.name = "CPU_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x11, ++ .desc = "Cycles" ++ }, ++ {.name = "BRANCH_PRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x12, ++ .desc = "Predictable branch speculatively executed" ++ }, ++ {.name = "DATA_MEM_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x13, ++ .desc = "Data memory access" ++ }, ++ {.name = "L1I_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x14, ++ .desc = "Level 1 instruction cache access" ++ }, ++ {.name = "L1D_CACHE_WB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x15, ++ .desc = "Level 1 data cache WriteBack" ++ }, ++ {.name = "L2D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x16, ++ .desc = "Level 2 data cache access" ++ }, ++ {.name = "L2D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x17, ++ .desc = "Level 2 data cache refill" ++ }, ++ {.name = "L2D_CACHE_WB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x18, ++ .desc = "Level 2 data cache WriteBack" ++ }, ++ {.name = "BUS_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x19, ++ .desc = "Bus access" ++ }, ++ {.name = "LOCAL_MEMORY_ERROR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1a, ++ .desc = "Local memory error" ++ }, ++ {.name = "BUS_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1d, ++ .desc = "Bus cycle" ++ }, ++ ++ {.name = "BUS_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x60, ++ .desc = "Bus read access" ++ }, ++ {.name = "BUS_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x61, ++ .desc = "Bus write access" ++ }, ++ ++ {.name = "BRANCH_SPEC_EXEC_IND", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7a, ++ .desc = "Indirect branch speculatively executed" ++ }, ++ ++ {.name = "EXCEPTION_IRQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x86, ++ .desc = "Exception taken, irq" ++ }, ++ {.name = "EXCEPTION_FIQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x87, ++ .desc = "Exception taken, irq" ++ }, ++}; +diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c +index 4bc863b..c38bd9b 100644 +--- a/lib/pfmlib_arm_armv8.c ++++ b/lib/pfmlib_arm_armv8.c +@@ -30,7 +30,8 @@ + #include "pfmlib_priv.h" /* library private */ + #include "pfmlib_arm_priv.h" + +-#include "events/arm_cortex_a57_events.h" /* event tables */ ++#include "events/arm_cortex_a57_events.h" /* A57 event tables */ ++#include "events/arm_cortex_a53_events.h" /* A53 event tables */ + + static int + pfm_arm_detect_cortex_a57(void *this) +@@ -48,6 +49,22 @@ pfm_arm_detect_cortex_a57(void *this) + return PFM_ERR_NOTSUPP; + } + ++static int ++pfm_arm_detect_cortex_a53(void *this) ++{ ++ int ret; ++ ++ ret = pfm_arm_detect(this); ++ if (ret != PFM_SUCCESS) ++ return PFM_ERR_NOTSUPP; ++ ++ if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */ ++ (pfm_arm_cfg.part == 0xd03)) { /* Cortex A53 */ ++ return PFM_SUCCESS; ++ } ++ return PFM_ERR_NOTSUPP; ++} ++ + /* ARM Cortex A57 support */ + pfmlib_pmu_t arm_cortex_a57_support={ + .desc = "ARM Cortex A57", +@@ -72,3 +89,28 @@ pfmlib_pmu_t arm_cortex_a57_support={ + PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), + .get_event_nattrs = pfm_arm_get_event_nattrs, + }; ++ ++/* ARM Cortex A53 support */ ++pfmlib_pmu_t arm_cortex_a53_support={ ++ .desc = "ARM Cortex A53", ++ .name = "arm_ac53", ++ .pmu = PFM_PMU_ARM_CORTEX_A53, ++ .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a53_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .pe = arm_cortex_a53_pe, ++ ++ .pmu_detect = pfm_arm_detect_cortex_a53, ++ .max_encoding = 1, ++ .num_cntrs = 6, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), ++ .get_event_first = pfm_arm_get_event_first, ++ .get_event_next = pfm_arm_get_event_next, ++ .event_is_valid = pfm_arm_event_is_valid, ++ .validate_table = pfm_arm_validate_table, ++ .get_event_info = pfm_arm_get_event_info, ++ .get_event_attr_info = pfm_arm_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), ++ .get_event_nattrs = pfm_arm_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index 900d7de..ebe20da 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -200,9 +200,11 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &arm_cortex_a15_support, + &arm_1176_support, + &arm_cortex_a57_support, ++ &arm_cortex_a53_support, + #endif + #ifdef CONFIG_PFMLIB_ARCH_ARM64 + &arm_cortex_a57_support, ++ &arm_cortex_a53_support, + #endif + + #ifdef CONFIG_PFMLIB_ARCH_S390X +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 3031d3b..5678cc0 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -333,6 +333,7 @@ extern pfmlib_pmu_t arm_cortex_a15_support; + extern pfmlib_pmu_t arm_cortex_a15_support; + extern pfmlib_pmu_t arm_1176_support; + extern pfmlib_pmu_t arm_cortex_a57_support; ++extern pfmlib_pmu_t arm_cortex_a53_support; + extern pfmlib_pmu_t mips_74k_support; + extern pfmlib_pmu_t s390x_cpum_cf_support; + +diff --git a/tests/validate_arm.c b/tests/validate_arm.c +index d6c0168..44eefd4 100644 +--- a/tests/validate_arm.c ++++ b/tests/validate_arm.c +@@ -187,6 +187,48 @@ static const test_event_t arm_test_events[]={ + .codes[0] = 0x8000008, + .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", + }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES:k:u", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_ac53::INST_RETIRED:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::LD_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000006, ++ .fstr = "arm_ac53::LD_RETIRED:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::ST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000007, ++ .fstr = "arm_ac53::ST_RETIRED:k=1:u=1:hv=0", ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(arm_test_events)/sizeof(test_event_t)) + +diff --git a/tests/validate_arm64.c b/tests/validate_arm64.c +index 0f0174c..61400ac 100644 +--- a/tests/validate_arm64.c ++++ b/tests/validate_arm64.c +@@ -72,6 +72,48 @@ static const test_event_t arm64_test_events[]={ + .codes[0] = 0x8000008, + .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0", + }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::CPU_CYCLES:k:u", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_ac53::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_ac53::INST_RETIRED:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::LD_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000006, ++ .fstr = "arm_ac53::LD_RETIRED:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_ac53::ST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000007, ++ .fstr = "arm_ac53::ST_RETIRED:k=1:u=1:hv=0", ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(arm64_test_events)/sizeof(test_event_t)) + +Return-Path: wcohen@redhat.com +Received: from zmta06.collab.prod.int.phx2.redhat.com (LHLO + zmta06.collab.prod.int.phx2.redhat.com) (10.5.81.13) by + zmail12.collab.prod.int.phx2.redhat.com with LMTP; Wed, 4 Jun 2014 10:54:07 + -0400 (EDT) +Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) + by zmta06.collab.prod.int.phx2.redhat.com (Postfix) with ESMTP id 1EC57167B59 + for ; Wed, 4 Jun 2014 10:54:07 -0400 (EDT) +Received: from santana.rdu.redhat.com (dhcp129-21.rdu.redhat.com [10.13.129.21]) + by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s54Es62r009804; + Wed, 4 Jun 2014 10:54:06 -0400 +From: William Cohen +To: perfmon2-devel@lists.sourceforge.net +Cc: William Cohen +Subject: [PATCH] Add support for Applied Micro X-Gene processor +Date: Wed, 4 Jun 2014 10:54:04 -0400 +Message-Id: <1401893644-22326-1-git-send-email-wcohen@redhat.com> +X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 + +--- + README | 1 + + docs/Makefile | 6 +- + docs/man3/libpfm_arm_xgene.3 | 39 ++++ + include/perfmon/pfmlib.h | 1 + + lib/events/arm_xgene_events.h | 515 ++++++++++++++++++++++++++++++++++++++++++ + lib/pfmlib_arm_armv8.c | 42 ++++ + lib/pfmlib_common.c | 2 + + lib/pfmlib_priv.h | 1 + + tests/validate_arm64.c | 28 +++ + 9 files changed, 633 insertions(+), 2 deletions(-) + create mode 100644 docs/man3/libpfm_arm_xgene.3 + create mode 100644 lib/events/arm_xgene_events.h + +diff --git a/README b/README +index e74238f..f6f45c9 100644 +--- a/README ++++ b/README +@@ -58,6 +58,7 @@ The library supports many PMUs. The current version can handle: + ARMV7 Cortex A9 + ARMV7 Cortex A15 + ARMV8 Cortex A57, A53 ++ Applied Micro X-Gene + + - For SPARC + Ultra I, II +diff --git a/docs/Makefile b/docs/Makefile +index c7d797e..4ae4bae 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -76,7 +76,8 @@ endif + endif + + ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y) +-ARCH_MAN += libpfm_arm_ac57.3 \ ++ARCH_MAN += libpfm_arm_xgene.3 \ ++ libpfm_arm_ac57.3 \ + libpfm_arm_ac53.3 \ + libpfm_arm_ac15.3 \ + libpfm_arm_ac8.3 \ +@@ -85,7 +86,8 @@ ARCH_MAN += libpfm_arm_ac57.3 \ + endif + + ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y) +-ARCH_MAN += libpfm_arm_ac57.3 \ ++ARCH_MAN += libpfm_arm_xgene.3 \ ++ libpfm_arm_ac57.3 \ + libpfm_arm_ac53.3 + endif + +diff --git a/docs/man3/libpfm_arm_xgene.3 b/docs/man3/libpfm_arm_xgene.3 +new file mode 100644 +index 0000000..a0a84bc +--- /dev/null ++++ b/docs/man3/libpfm_arm_xgene.3 +@@ -0,0 +1,39 @@ ++.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_arm_ac57 - support for Applied Micro X-Gene PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: arm_xgene ++.B PMU desc: Applied Micro X-Gene ++.sp ++.SH DESCRIPTION ++The library supports the Applied Micro X-Gene PMU. ++ ++This PMU supports 6 counters and privilege levels filtering. ++It can operate in both 32 and 64 bit modes. ++ ++.SH MODIFIERS ++The following modifiers are supported on Applied Micro X-Gene: ++.TP ++.B u ++Measure at the user level. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B hv ++Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. ++This is a boolean modifier. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.nf ++William Cohen ++.if ++.PP +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index a7ec026..b7b312e 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -239,6 +239,7 @@ typedef enum { + + PFM_PMU_ARM_CORTEX_A57, /* ARM Cortex A57 (ARMv8) */ + PFM_PMU_ARM_CORTEX_A53, /* ARM Cortex A53 (ARMv8) */ ++ PFM_PMU_ARM_XGENE, /* Applied Micro X-Gene (ARMv8) */ + + /* MUST ADD NEW PMU MODELS HERE */ + +diff --git a/lib/events/arm_xgene_events.h b/lib/events/arm_xgene_events.h +new file mode 100644 +index 0000000..856dac1 +--- /dev/null ++++ b/lib/events/arm_xgene_events.h +@@ -0,0 +1,515 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Copyright (c) 2014 Red Hat Inc. All rights reserved ++ * Contributed by William Cohen ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Applied Micro X-Gene ++ * based on Mustang (X-Gene) Software User Guide 15.1.2 CPU PMU Event list ++ */ ++ ++static const arm_entry_t arm_xgene_pe[]={ ++ {.name = "SW_INCR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x00, ++ .desc = "Instruction architecturally executed (condition check pass) Software increment" ++ }, ++ {.name = "L1I_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x01, ++ .desc = "Level 1 instruction cache refill" ++ }, ++ {.name = "L1I_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x02, ++ .desc = "Level 1 instruction TLB refill" ++ }, ++ {.name = "L1D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x03, ++ .desc = "Level 1 data cache refill" ++ }, ++ {.name = "L1D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x04, ++ .desc = "Level 1 data cache access" ++ }, ++ {.name = "L1D_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x05, ++ .desc = "Level 1 data TLB refill" ++ }, ++ {.name = "INST_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x08, ++ .desc = "Instruction architecturally executed" ++ }, ++ {.name = "EXCEPTION_TAKEN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x09, ++ .desc = "Exception taken" ++ }, ++ {.name = "EXCEPTION_RETURN", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0a, ++ .desc = "Instruction architecturally executed (condition check pass) Exception return" ++ }, ++ {.name = "CID_WRITE_RETIRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x0b, ++ .desc = "Change to Context ID retired", ++ }, ++ {.name = "BRANCH_MISPRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10, ++ .desc = "Mispredicted or not predicted branch speculatively executed" ++ }, ++ {.name = "CPU_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x11, ++ .desc = "Cycles" ++ }, ++ {.name = "BRANCH_PRED", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x12, ++ .desc = "Predictable branch speculatively executed" ++ }, ++ {.name = "DATA_MEM_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x13, ++ .desc = "Data memory access" ++ }, ++ {.name = "L1I_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x14, ++ .desc = "Level 1 instruction cache access" ++ }, ++ {.name = "L2D_CACHE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x16, ++ .desc = "Level 2 data cache access" ++ }, ++ {.name = "L2D_CACHE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x17, ++ .desc = "Level 2 data cache refill" ++ }, ++ {.name = "L2D_CACHE_WB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x18, ++ .desc = "Level 2 data cache WriteBack" ++ }, ++ {.name = "BUS_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x19, ++ .desc = "Bus access" ++ }, ++ {.name = "LOCAL_MEMORY_ERROR", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x1a, ++ .desc = "Local memory error" ++ }, ++ ++ {.name = "L1D_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x40, ++ .desc = "Level 1 data cache read access" ++ }, ++ {.name = "L1D_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x41, ++ .desc = "Level 1 data cache write access" ++ }, ++ {.name = "L1D_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x42, ++ .desc = "Level 1 data cache read refill" ++ }, ++ {.name = "L1D_INVALIDATE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x48, ++ .desc = "Level 1 data cache invalidate" ++ }, ++ {.name = "L1D_TLB_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x4c, ++ .desc = "Level 1 data TLB read refill" ++ }, ++ {.name = "L1D_TLB_WRITE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x4d, ++ .desc = "Level 1 data TLB write refill" ++ }, ++ {.name = "L2D_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x50, ++ .desc = "Level 2 data cache read access" ++ }, ++ {.name = "L2D_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x51, ++ .desc = "Level 2 data cache write access" ++ }, ++ {.name = "L2D_READ_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x52, ++ .desc = "Level 2 data cache read refill" ++ }, ++ {.name = "L2D_WRITE_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x53, ++ .desc = "Level 2 data cache write refill" ++ }, ++ {.name = "L2D_WB_VICTIM", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x56, ++ .desc = "Level 2 data cache writeback victim" ++ }, ++ {.name = "L2D_WB_CLEAN_COHERENCY", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x57, ++ .desc = "Level 2 data cache writeback cleaning and coherency" ++ }, ++ {.name = "L2D_INVALIDATE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x58, ++ .desc = "Level 2 data cache invalidate" ++ }, ++ {.name = "BUS_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x60, ++ .desc = "Bus read access" ++ }, ++ {.name = "BUS_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x61, ++ .desc = "Bus write access" ++ }, ++ {.name = "BUS_NORMAL_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x62, ++ .desc = "Bus normal access" ++ }, ++ {.name = "BUS_NOT_NORMAL_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x63, ++ .desc = "Bus not normal access" ++ }, ++ {.name = "BUS_NORMAL_ACCESS_2", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x64, ++ .desc = "Bus normal access" ++ }, ++ {.name = "BUS_PERIPH_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x65, ++ .desc = "Bus peripheral access" ++ }, ++ {.name = "DATA_MEM_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x66, ++ .desc = "Data memory read access" ++ }, ++ {.name = "DATA_MEM_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x67, ++ .desc = "Data memory write access" ++ }, ++ {.name = "UNALIGNED_READ_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x68, ++ .desc = "Unaligned read access" ++ }, ++ {.name = "UNALIGNED_WRITE_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x69, ++ .desc = "Unaligned read access" ++ }, ++ {.name = "UNALIGNED_ACCESS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6a, ++ .desc = "Unaligned access" ++ }, ++ {.name = "INST_SPEC_EXEC_LDREX", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6c, ++ .desc = "LDREX exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STREX_PASS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6d, ++ .desc = "STREX pass exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STREX_FAIL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x6e, ++ .desc = "STREX fail exclusive instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_LOAD", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x70, ++ .desc = "Load instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_STORE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x71, ++ .desc = "Store instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_LOAD_STORE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x72, ++ .desc = "Load or store instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_INTEGER_INST", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x73, ++ .desc = "Integer data processing instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_SIMD", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x74, ++ .desc = "Advanced SIMD instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_VFP", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x75, ++ .desc = "VFP instruction speculatively executed" ++ }, ++ {.name = "INST_SPEC_EXEC_SOFT_PC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x76, ++ .desc = "Software of the PC instruction speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x78, ++ .desc = "Immediate branch speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_RET", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x79, ++ .desc = "Return branch speculatively executed" ++ }, ++ {.name = "BRANCH_SPEC_EXEC_IND", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7a, ++ .desc = "Indirect branch speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_ISB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7c, ++ .desc = "ISB barrier speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_DSB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7d, ++ .desc = "DSB barrier speculatively executed" ++ }, ++ {.name = "BARRIER_SPEC_EXEC_DMB", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x7e, ++ .desc = "DMB barrier speculatively executed" ++ }, ++ {.name = "EXCEPTION_UNDEF", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x81, ++ .desc = "Exception taken, other synchronous" ++ }, ++ {.name = "EXCEPTION_SVC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x82, ++ .desc = "Exception taken, supervisor call" ++ }, ++ {.name = "EXCEPTION_PABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x83, ++ .desc = "Exception taken, instruction abort" ++ }, ++ {.name = "EXCEPTION_DABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x84, ++ .desc = "Exception taken, data abort or SError" ++ }, ++ {.name = "EXCEPTION_IRQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x86, ++ .desc = "Exception taken, irq" ++ }, ++ {.name = "EXCEPTION_FIQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x87, ++ .desc = "Exception taken, irq" ++ }, ++ {.name = "EXCEPTION_HVC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8a, ++ .desc = "Exception taken, hypervisor call" ++ }, ++ {.name = "EXCEPTION_TRAP_PABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8b, ++ .desc = "Exception taken, instruction abort not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_DABORT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8c, ++ .desc = "Exception taken, data abort or SError not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_OTHER", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8d, ++ .desc = "Exception taken, other traps not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_IRQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8e, ++ .desc = "Exception taken, irq not taken locally" ++ }, ++ {.name = "EXCEPTION_TRAP_FIQ", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x8f, ++ .desc = "Exception taken, fiq not taken locally" ++ }, ++ {.name = "RC_LD_SPEC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x90, ++ .desc = "Release consistency instruction speculatively executed (load-acquire)", ++ }, ++ {.name = "RC_ST_SPEC", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x91, ++ .desc = "Release consistency instruction speculatively executed (store-release)", ++ }, ++ {.name = "INST_SPEC_EXEC_NOP", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x100, ++ .desc = "Operation speculatively executed - NOP", ++ }, ++ {.name = "FSU_CLOCK_OFF", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x101, ++ .desc = "FSU clocking gated off cycle", ++ }, ++ {.name = "BTB_MISPREDICT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x102, ++ .desc = "BTB misprediction", ++ }, ++ {.name = "ITB_MISS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x103, ++ .desc = "ITB miss", ++ }, ++ {.name = "DTB_MISS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x104, ++ .desc = "DTB miss", ++ }, ++ {.name = "L1D_CACHE_LATE_MISS", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x105, ++ .desc = "L1 data cache late miss", ++ }, ++ {.name = "L1D_CACHE_PREFETCH", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x106, ++ .desc = "L1 data cache prefetch request", ++ }, ++ {.name = "L2_CACHE_PREFETCH", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x107, ++ .desc = "L2 data prefetch request", ++ }, ++ {.name = "STALLED_CYCLES_FRONTEND", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x108, ++ .desc = "Decode starved for instruction cycle", ++ }, ++ {.name = "STALLED_CYCLES_BACKEND", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x109, ++ .desc = "Op dispatch stalled cycle", ++ }, ++ {.name = "IXA_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10A, ++ .desc = "IXA Op non-issue", ++ }, ++ {.name = "IXB_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10B, ++ .desc = "IXB Op non-issue", ++ }, ++ {.name = "BX_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10C, ++ .desc = "BX Op non-issue", ++ }, ++ {.name = "LX_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10D, ++ .desc = "LX Op non-issue", ++ }, ++ {.name = "SX_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10E, ++ .desc = "SX Op non-issue", ++ }, ++ {.name = "FX_NO_ISSUE", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x10F, ++ .desc = "FX Op non-issue", ++ }, ++ {.name = "WAIT_CYCLES", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x110, ++ .desc = "Wait state cycle", ++ }, ++ {.name = "L1_STAGE2_TLB_REFILL", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x111, ++ .desc = "L1 stage-2 TLB refill", ++ }, ++ {.name = "PAGE_WALK_L0_STAGE1_HIT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x112, ++ .desc = "Page Walk Cache level-0 stage-1 hit", ++ }, ++ {.name = "PAGE_WALK_L1_STAGE1_HIT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x113, ++ .desc = "Page Walk Cache level-1 stage-1 hit", ++ }, ++ {.name = "PAGE_WALK_L2_STAGE1_HIT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x114, ++ .desc = "Page Walk Cache level-2 stage-1 hit", ++ }, ++ {.name = "PAGE_WALK_L1_STAGE2_HIT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x115, ++ .desc = "Page Walk Cache level-1 stage-2 hit", ++ }, ++ {.name = "PAGE_WALK_L2_STAGE2_HIT", ++ .modmsk = ARMV8_ATTRS, ++ .code = 0x116, ++ .desc = "Page Walk Cache level-2 stage-2 hit", ++ }, ++ /* END Applied Micro X-Gene specific events */ ++}; +diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c +index c38bd9b..3619508 100644 +--- a/lib/pfmlib_arm_armv8.c ++++ b/lib/pfmlib_arm_armv8.c +@@ -32,6 +32,7 @@ + + #include "events/arm_cortex_a57_events.h" /* A57 event tables */ + #include "events/arm_cortex_a53_events.h" /* A53 event tables */ ++#include "events/arm_xgene_events.h" /* Applied Micro X-Gene tables */ + + static int + pfm_arm_detect_cortex_a57(void *this) +@@ -65,6 +66,22 @@ pfm_arm_detect_cortex_a53(void *this) + return PFM_ERR_NOTSUPP; + } + ++static int ++pfm_arm_detect_xgene(void *this) ++{ ++ int ret; ++ ++ ret = pfm_arm_detect(this); ++ if (ret != PFM_SUCCESS) ++ return PFM_ERR_NOTSUPP; ++ ++ if ((pfm_arm_cfg.implementer == 0x50) && /* Applied Micro */ ++ (pfm_arm_cfg.part == 0x000)) { /* Applied Micro X-Gene */ ++ return PFM_SUCCESS; ++ } ++ return PFM_ERR_NOTSUPP; ++} ++ + /* ARM Cortex A57 support */ + pfmlib_pmu_t arm_cortex_a57_support={ + .desc = "ARM Cortex A57", +@@ -114,3 +131,28 @@ pfmlib_pmu_t arm_cortex_a53_support={ + PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), + .get_event_nattrs = pfm_arm_get_event_nattrs, + }; ++ ++/* Applied Micro X-Gene support */ ++pfmlib_pmu_t arm_xgene_support={ ++ .desc = "Applied Micro X-Gene", ++ .name = "arm_xgene", ++ .pmu = PFM_PMU_ARM_XGENE, ++ .pme_count = LIBPFM_ARRAY_SIZE(arm_xgene_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .pe = arm_xgene_pe, ++ ++ .pmu_detect = pfm_arm_detect_xgene, ++ .max_encoding = 1, ++ .num_cntrs = 6, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), ++ .get_event_first = pfm_arm_get_event_first, ++ .get_event_next = pfm_arm_get_event_next, ++ .event_is_valid = pfm_arm_event_is_valid, ++ .validate_table = pfm_arm_validate_table, ++ .get_event_info = pfm_arm_get_event_info, ++ .get_event_attr_info = pfm_arm_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), ++ .get_event_nattrs = pfm_arm_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index ebe20da..569ce85 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -201,10 +201,12 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &arm_1176_support, + &arm_cortex_a57_support, + &arm_cortex_a53_support, ++ &arm_xgene_support, + #endif + #ifdef CONFIG_PFMLIB_ARCH_ARM64 + &arm_cortex_a57_support, + &arm_cortex_a53_support, ++ &arm_xgene_support, + #endif + + #ifdef CONFIG_PFMLIB_ARCH_S390X +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 5678cc0..1666bcb 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -334,6 +334,7 @@ extern pfmlib_pmu_t arm_1176_support; + extern pfmlib_pmu_t arm_1176_support; + extern pfmlib_pmu_t arm_cortex_a57_support; + extern pfmlib_pmu_t arm_cortex_a53_support; ++extern pfmlib_pmu_t arm_xgene_support; + extern pfmlib_pmu_t mips_74k_support; + extern pfmlib_pmu_t s390x_cpum_cf_support; + +diff --git a/tests/validate_arm64.c b/tests/validate_arm64.c +index 61400ac..f4593de 100644 +--- a/tests/validate_arm64.c ++++ b/tests/validate_arm64.c +@@ -114,6 +114,34 @@ static const test_event_t arm64_test_events[]={ + .codes[0] = 0x8000007, + .fstr = "arm_ac53::ST_RETIRED:k=1:u=1:hv=0", + }, ++ { SRC_LINE, ++ .name = "arm_xgene::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_xgene::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_xgene::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_xgene::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_xgene::CPU_CYCLES:k:u", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_xgene::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_xgene::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_xgene::INST_RETIRED:k=1:u=1:hv=0", ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(arm64_test_events)/sizeof(test_event_t)) + +-- +1.9.3 + diff --git a/SOURCES/libpfm-events.patch b/SOURCES/libpfm-events.patch index e1e5cce..506e257 100644 --- a/SOURCES/libpfm-events.patch +++ b/SOURCES/libpfm-events.patch @@ -1,14 +1,12 @@ -From 1f169c82d7e788f3a7096b212fa33d26c8155a85 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Wed, 19 Jun 2013 08:42:20 +0200 -Subject: [PATCH 01/14] fix event name typo for CPU_IO_REQUESTS_TO_MEMORY_IO +commit 1f169c82d7e788f3a7096b212fa33d26c8155a85 +Author: Stephane Eranian +Date: Wed Jun 19 08:42:20 2013 +0200 -Reported by Steve Kaufmann. - -Signed-off-by: Stephane Eranian ---- - lib/events/amd64_events_fam15h.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + fix event name typo for CPU_IO_REQUESTS_TO_MEMORY_IO + + Reported by Steve Kaufmann. + + Signed-off-by: Stephane Eranian diff --git a/lib/events/amd64_events_fam15h.h b/lib/events/amd64_events_fam15h.h index 7195f13..5738e4c 100644 @@ -23,20 +21,16 @@ index 7195f13..5738e4c 100644 .desc = "CPU/IO Requests to Memory/IO", .code = 0xe9, .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_io_requests_to_memory_io), --- -1.8.3.1 - -From 0f7cd3b77060def8a91218819493effe276350c8 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Mon, 1 Jul 2013 08:02:09 +0200 -Subject: [PATCH 02/14] fix event code for Intel Haswell LSD event -Was 0xa0 instead of 0xa8 +commit 0f7cd3b77060def8a91218819493effe276350c8 +Author: Stephane Eranian +Date: Mon Jul 1 08:02:09 2013 +0200 -Signed-off-by: Stephane Eranian ---- - lib/events/intel_hsw_events.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + fix event code for Intel Haswell LSD event + + Was 0xa0 instead of 0xa8 + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h index bc0549e..e00291e 100644 @@ -51,21 +45,16 @@ index bc0549e..e00291e 100644 .cntmsk = 0xff, .ngrp = 1, .modmsk = INTEL_V4_ATTRS, --- -1.8.3.1 -From 7d74c8db594447b7235daf3a54154b9a9f17da0d Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Mon, 1 Jul 2013 08:32:37 +0200 -Subject: [PATCH 03/14] remove unsupported umask combo for HSW BR_MISP_EXEC and - BR_INST_EXEC +commit 7d74c8db594447b7235daf3a54154b9a9f17da0d +Author: Stephane Eranian +Date: Mon Jul 1 08:32:37 2013 +0200 -Some umask combinations were not supported - -Signed-off-by: Stephane Eranian ---- - lib/events/intel_hsw_events.h | 19 ++----------------- - 1 file changed, 2 insertions(+), 17 deletions(-) + remove unsupported umask combo for HSW BR_MISP_EXEC and BR_INST_EXEC + + Some umask combinations were not supported + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h index e00291e..edcc6bc 100644 @@ -112,20 +101,16 @@ index e00291e..edcc6bc 100644 { .uname = "ALL_BRANCHES", .udesc = "Speculative and retired mispredicted macro conditional branches", .ucode = 0xff00, --- -1.8.3.1 - -From b52f161160dc0ddb9dfcdd51e61b4a9171a293ce Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Mon, 1 Jul 2013 09:34:12 +0200 -Subject: [PATCH 04/14] add Haswell UOPS_EXECUTED:STALL_CYCLES -Handy alias to UOPS_EXECUTED:CORE:c=1:i +commit b52f161160dc0ddb9dfcdd51e61b4a9171a293ce +Author: Stephane Eranian +Date: Mon Jul 1 09:34:12 2013 +0200 -Signed-off-by: Stephane Eranian ---- - lib/events/intel_hsw_events.h | 7 +++++++ - 1 file changed, 7 insertions(+) + add Haswell UOPS_EXECUTED:STALL_CYCLES + + Handy alias to UOPS_EXECUTED:CORE:c=1:i + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h index edcc6bc..d479862 100644 @@ -145,20 +130,238 @@ index edcc6bc..d479862 100644 }; static const intel_x86_umask_t hsw_uops_executed_port[]={ --- -1.8.3.1 -From 138ec47914922851256e1275e508d94d3ecf7956 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Wed, 31 Jul 2013 16:01:05 +0200 -Subject: [PATCH 05/14] fix modmsk for Intel Haswell CYCLE_ACTIVITY event +commit 55446fad9f3e2501ae5c249919870466faebb6d2 +Author: Stephane Eranian +Date: Wed Jul 31 10:32:33 2013 +0200 + + add os_detect() callback to pfmlib_pmu struct + + Add new callbacks to invoke an OS-specific callback + to detect the PMU. Even though a PMU can be detected + via a CPUID that does not mean that it is also supported + by the host kernel. So proivide an opportunity for PMU + support to invoke an OS specific detection routine. + + For instance, on Linux with perf_events, a PMU is + supported by the kernel if it has an entry in /sys/devices/ + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index 71bddd9..e810eca 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -171,6 +171,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + #define PFMLIB_NUM_PMUS (int)(sizeof(pfmlib_pmus)/sizeof(pfmlib_pmu_t *)) + + static pfmlib_os_t pfmlib_os_none; ++pfmlib_os_t *pfmlib_os = &pfmlib_os_none; + + static pfmlib_os_t *pfmlib_oses[]={ + &pfmlib_os_none, +@@ -611,6 +612,17 @@ pfmlib_init_pmus(void) + if (ret != PFM_SUCCESS) + continue; + ++ /* ++ * check if exported by OS if needed ++ */ ++ if (p->os_detect[pfmlib_os->id]) { ++ ret = p->os_detect[pfmlib_os->id](p); ++ if (ret != PFM_SUCCESS) { ++ DPRINT("%s PMU not exported by OS\n", p->name); ++ continue; ++ } ++ } ++ + ret = pfmlib_pmu_activate(p); + if (ret == PFM_SUCCESS) + nsuccess++; +@@ -642,9 +654,13 @@ pfmlib_init_os(void) + if (os->detect(os) != PFM_SUCCESS) + continue; + ++ if (os != &pfmlib_os_none && pfmlib_os == &pfmlib_os_none) ++ pfmlib_os = os; ++ + DPRINT("OS layer %s activated\n", os->name); + os->flags = PFMLIB_OS_FL_ACTIVATED; + } ++ DPRINT("default OS layer: %s\n", pfmlib_os->name); + } + + int +@@ -667,11 +683,13 @@ pfm_initialize(void) + + pfmlib_init_env(); + ++ /* must be done before pfmlib_init_pmus() */ ++ pfmlib_init_os(); ++ + ret = pfmlib_init_pmus(); + if (ret != PFM_SUCCESS) + return ret; + +- pfmlib_init_os(); + + pfm_cfg.initdone = 1; + +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 8e203d4..758b65d 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -128,6 +128,7 @@ typedef struct pfmlib_pmu { + int (*get_event_encoding[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); + + void (*validate_pattrs[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); ++ int (*os_detect[PFM_OS_MAX])(void *this); + int (*validate_table)(void *this, FILE *fp); + int (*get_num_events)(void *this); /* optional */ + void (*display_reg)(void *this, pfmlib_event_desc_t *e, void *val); /* optional */ +@@ -286,6 +287,7 @@ extern pfmlib_pmu_t arm_1176_support; + extern pfmlib_pmu_t mips_74k_support; + extern pfmlib_pmu_t s390x_cpum_cf_support; + ++extern pfmlib_os_t *pfmlib_os; + extern pfmlib_os_t pfmlib_os_perf; + extern pfmlib_os_t pfmlib_os_perf_ext; + +@@ -352,6 +354,10 @@ pfmlib_pidx2idx(pfmlib_pmu_t *pmu, int pidx) + #define PFMLIB_ENCODE_PERF(f) \ + .get_event_encoding[PFM_OS_PERF_EVENT] = f, \ + .get_event_encoding[PFM_OS_PERF_EVENT_EXT] = f ++ ++#define PFMLIB_OS_DETECT(f) \ ++ .os_detect[PFM_OS_PERF_EVENT] = f, \ ++ .os_detect[PFM_OS_PERF_EVENT_EXT] = f + #else + #define PFMLIB_VALID_PERF_PATTRS(f) \ + .validate_pattrs[PFM_OS_PERF_EVENT] = NULL, \ +@@ -360,6 +366,10 @@ pfmlib_pidx2idx(pfmlib_pmu_t *pmu, int pidx) + #define PFMLIB_ENCODE_PERF(f) \ + .get_event_encoding[PFM_OS_PERF_EVENT] = NULL, \ + .get_event_encoding[PFM_OS_PERF_EVENT_EXT] = NULL ++ ++#define PFMLIB_OS_DETECT(f) \ ++ .os_detect[PFM_OS_PERF_EVENT] = NULL, \ ++ .os_detect[PFM_OS_PERF_EVENT_EXT] = NULL + #endif + + #endif /* __PFMLIB_PRIV_H__ */ +commit bc8e5737e8e95354aee90edfa29f9c2944cf0a1c +Author: Stephane Eranian +Date: Wed Jul 31 10:35:09 2013 +0200 + + Add Intel x86 perf_events OS detection function for PMU + + To be used with os_detect() callback. Useful for uncore + PMUs because depending on the host hardware not all PMUs + may necessarily be there, e.g., desktop vs. laptop. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_x86_perf_event.c b/lib/pfmlib_intel_x86_perf_event.c +index 443a959..f29af94 100644 +--- a/lib/pfmlib_intel_x86_perf_event.c ++++ b/lib/pfmlib_intel_x86_perf_event.c +@@ -276,3 +276,13 @@ pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + } + } + } ++ ++int ++pfm_intel_x86_perf_detect(void *this) ++{ ++ pfmlib_pmu_t *pmu = this; ++ char file[64]; ++ ++ snprintf(file,sizeof(file), "/sys/devices/%s", pmu->perf_name); ++ return access(file, R_OK|X_OK) ? PFM_ERR_NOTSUPP : PFM_SUCCESS; ++} +diff --git a/lib/pfmlib_intel_x86_priv.h b/lib/pfmlib_intel_x86_priv.h +index ce369bc..a0810cd 100644 +--- a/lib/pfmlib_intel_x86_priv.h ++++ b/lib/pfmlib_intel_x86_priv.h +@@ -322,6 +322,7 @@ extern int pfm_intel_x86_get_event_attr_info(void *this, int idx, int attr_idx, + extern int pfm_intel_x86_get_event_info(void *this, int idx, pfm_event_info_t *info); + extern int pfm_intel_x86_valid_pebs(pfmlib_event_desc_t *e); + extern int pfm_intel_x86_perf_event_encoding(pfmlib_event_desc_t *e, void *data); ++extern int pfm_intel_x86_perf_detect(void *this); + extern unsigned int pfm_intel_x86_get_event_nattrs(void *this, int pidx); + extern int intel_x86_attr2mod(void *this, int pidx, int attr_idx); + + +commit 0912bb54b9e24b06141f34b1d7efe29b826863eb +Author: Stephane Eranian +Date: Wed Jul 31 10:36:18 2013 +0200 + + add Intel IvyBridge uncore PMU os_detect() callback + + Use the os_detect() callback to detect which of the + uncore PMUs are actually supported by host hardware. + Not all PMUs are necessarily available, e.g., laptop + vs. desktop. + + Signed-off-by: Stephane Eranian -Was marked as V3 when it is V4 +diff --git a/lib/pfmlib_intel_ivb_unc.c b/lib/pfmlib_intel_ivb_unc.c +index bc94807..c2f2165 100644 +--- a/lib/pfmlib_intel_ivb_unc.c ++++ b/lib/pfmlib_intel_ivb_unc.c +@@ -27,7 +27,7 @@ + #define INTEL_SNB_UNC_ATTRS \ + (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C) + +-/* same event table and SNB */ ++/* same event table as SNB */ + #include "events/intel_snb_unc_events.h" + + static int +@@ -68,6 +68,7 @@ pfmlib_pmu_t intel_ivb_unc_cbo##n##_support={ \ + .pmu_detect = pfm_ivb_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first, \ + .get_event_next = pfm_intel_x86_get_event_next, \ + .event_is_valid = pfm_intel_x86_event_is_valid, \ + +commit 4ddac8ecc7c6ebe283df8d45690735f76f17bf85 +Author: Stephane Eranian +Date: Wed Jul 31 10:39:03 2013 +0200 + + add Intel SandyBridge uncore PMU os_detect() callback + + Use the os_detect() callback to detect which of the + uncore PMUs are actually supported by host hardware. + Not all PMUs are necessarily available, e.g., laptop + vs. desktop. + + Signed-off-by: Stephane Eranian -Signed-off-by: Stephane Eranian ---- - lib/events/intel_hsw_events.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) +diff --git a/lib/pfmlib_intel_snb_unc.c b/lib/pfmlib_intel_snb_unc.c +index f4bfaba..b0be6e7 100644 +--- a/lib/pfmlib_intel_snb_unc.c ++++ b/lib/pfmlib_intel_snb_unc.c +@@ -68,6 +68,7 @@ pfmlib_pmu_t intel_snb_unc_cbo##n##_support={ \ + .pmu_detect = pfm_snb_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first, \ + .get_event_next = pfm_intel_x86_get_event_next, \ + .event_is_valid = pfm_intel_x86_event_is_valid, \ + +commit 138ec47914922851256e1275e508d94d3ecf7956 +Author: Stephane Eranian +Date: Wed Jul 31 16:01:05 2013 +0200 + + fix modmsk for Intel Haswell CYCLE_ACTIVITY event + + Was marked as V3 when it is V4 + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h index d479862..ccd4a2b 100644 @@ -173,20 +376,240 @@ index d479862..ccd4a2b 100644 .numasks = LIBPFM_ARRAY_SIZE(hsw_cycle_activity), .umasks = hsw_cycle_activity }, --- -1.8.3.1 -From a3e9c3ec4d87c0a82e5622c6421133493e7cc0a4 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Sat, 10 Aug 2013 15:35:25 +0200 -Subject: [PATCH 06/14] drop umask from snbep_unc_pcu:COREx_TRANSITION_CYCLES +commit e245899e77591e3dca793fd81c9f1add4eaebfd8 +Author: Stephane Eranian +Date: Wed Jul 31 16:02:02 2013 +0200 + + add Intel Haswell support for TSX event modifiers + + Add the following event modifiers on Intel Haswell: + + - intx: monitor only inside transactional memory region + - intxcp: do not monitor inside aborted transactional memory region + + Also update the validation test accordingly. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_x86.c b/lib/pfmlib_intel_x86.c +index f069317..435ce9e 100644 +--- a/lib/pfmlib_intel_x86.c ++++ b/lib/pfmlib_intel_x86.c +@@ -40,6 +40,8 @@ const pfmlib_attr_desc_t intel_x86_mods[]={ + PFM_ATTR_I("c", "counter-mask in range [0-255]"), /* counter-mask */ + PFM_ATTR_B("t", "measure any thread"), /* monitor on both threads */ + PFM_ATTR_I("ldlat", "load latency threshold (cycles, [3-65535])"), /* load latency threshold */ ++ PFM_ATTR_B("intx", "monitor only inside transactional memory region"), ++ PFM_ATTR_B("intxcp", "do not count occurrences inside aborted transactional memory region"), + PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ + }; + +@@ -490,7 +492,18 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) + return PFM_ERR_ATTR_VAL; + ldlat = ival; + break; +- ++ case INTEL_X86_ATTR_INTX: /* in_tx */ ++ if (modhw & _INTEL_X86_ATTR_INTX) ++ return PFM_ERR_ATTR_SET; ++ reg.sel_intx = !!ival; ++ umodmsk |= _INTEL_X86_ATTR_INTX; ++ break; ++ case INTEL_X86_ATTR_INTXCP: /* in_tx_cp */ ++ if (modhw & _INTEL_X86_ATTR_INTXCP) ++ return PFM_ERR_ATTR_SET; ++ reg.sel_intxcp = !!ival; ++ umodmsk |= _INTEL_X86_ATTR_INTXCP; ++ break; + } + } + } +@@ -627,6 +640,12 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) + case INTEL_X86_ATTR_LDLAT: + evt_strcat(e->fstr, ":%s=%d", intel_x86_mods[id].name, ldlat); + break; ++ case INTEL_X86_ATTR_INTX: ++ evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_intx); ++ break; ++ case INTEL_X86_ATTR_INTXCP: ++ evt_strcat(e->fstr, ":%s=%lu", intel_x86_mods[id].name, reg.sel_intxcp); ++ break; + } + } + return PFM_SUCCESS; +diff --git a/lib/pfmlib_intel_x86_priv.h b/lib/pfmlib_intel_x86_priv.h +index a0810cd..1671ca6 100644 +--- a/lib/pfmlib_intel_x86_priv.h ++++ b/lib/pfmlib_intel_x86_priv.h +@@ -101,7 +101,9 @@ typedef union pfm_intel_x86_reg { + unsigned long sel_en:1; /* enable */ + unsigned long sel_inv:1; /* invert counter mask */ + unsigned long sel_cnt_mask:8; /* counter mask */ +- unsigned long sel_res2:32; ++ unsigned long sel_intx:1; /* only in tx region */ ++ unsigned long sel_intxcp:1; /* excl. aborted tx region */ ++ unsigned long sel_res2:30; + } perfevtsel; + + struct { +@@ -149,14 +151,18 @@ typedef union pfm_intel_x86_reg { + #define INTEL_X86_ATTR_C 4 /* counter mask */ + #define INTEL_X86_ATTR_T 5 /* any thread */ + #define INTEL_X86_ATTR_LDLAT 6 /* load latency threshold */ +- +-#define _INTEL_X86_ATTR_U (1 << INTEL_X86_ATTR_U) +-#define _INTEL_X86_ATTR_K (1 << INTEL_X86_ATTR_K) +-#define _INTEL_X86_ATTR_I (1 << INTEL_X86_ATTR_I) +-#define _INTEL_X86_ATTR_E (1 << INTEL_X86_ATTR_E) +-#define _INTEL_X86_ATTR_C (1 << INTEL_X86_ATTR_C) +-#define _INTEL_X86_ATTR_T (1 << INTEL_X86_ATTR_T) +-#define _INTEL_X86_ATTR_LDLAT (1 << INTEL_X86_ATTR_LDLAT) ++#define INTEL_X86_ATTR_INTX 7 /* in transaction */ ++#define INTEL_X86_ATTR_INTXCP 8 /* not aborted transaction */ ++ ++#define _INTEL_X86_ATTR_U (1 << INTEL_X86_ATTR_U) ++#define _INTEL_X86_ATTR_K (1 << INTEL_X86_ATTR_K) ++#define _INTEL_X86_ATTR_I (1 << INTEL_X86_ATTR_I) ++#define _INTEL_X86_ATTR_E (1 << INTEL_X86_ATTR_E) ++#define _INTEL_X86_ATTR_C (1 << INTEL_X86_ATTR_C) ++#define _INTEL_X86_ATTR_T (1 << INTEL_X86_ATTR_T) ++#define _INTEL_X86_ATTR_INTX (1 << INTEL_X86_ATTR_INTX) ++#define _INTEL_X86_ATTR_INTXCP (1 << INTEL_X86_ATTR_INTXCP) ++#define _INTEL_X86_ATTR_LDLAT (1 << INTEL_X86_ATTR_LDLAT) + + #define INTEL_X86_ATTRS \ + (_INTEL_X86_ATTR_I|_INTEL_X86_ATTR_E|_INTEL_X86_ATTR_C|_INTEL_X86_ATTR_U|_INTEL_X86_ATTR_K) +@@ -166,7 +172,7 @@ typedef union pfm_intel_x86_reg { + #define INTEL_FIXED2_ATTRS (_INTEL_X86_ATTR_U|_INTEL_X86_ATTR_K) + #define INTEL_FIXED3_ATTRS (INTEL_FIXED2_ATTRS|_INTEL_X86_ATTR_T) + #define INTEL_V3_ATTRS (INTEL_V2_ATTRS|_INTEL_X86_ATTR_T) +-#define INTEL_V4_ATTRS (INTEL_V3_ATTRS) ++#define INTEL_V4_ATTRS (INTEL_V3_ATTRS | _INTEL_X86_ATTR_INTX | _INTEL_X86_ATTR_INTXCP) + + /* let's define some handy shortcuts! */ + #define sel_event_select perfevtsel.sel_event_select +@@ -180,6 +186,8 @@ typedef union pfm_intel_x86_reg { + #define sel_inv perfevtsel.sel_inv + #define sel_cnt_mask perfevtsel.sel_cnt_mask + #define sel_anythr perfevtsel.sel_anythr ++#define sel_intx perfevtsel.sel_intx ++#define sel_intxcp perfevtsel.sel_intxcp + + /* + * shift relative to start of register +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index e3e2866..f351bc0 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1891,7 +1891,7 @@ static const test_event_t x86_test_events[]={ + .count = 2, + .codes[0] = 0x5101cd, + .codes[1] = 3, +- .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3", ++ .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", + }, + { SRC_LINE, + .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=1000000", +@@ -1903,22 +1903,40 @@ static const test_event_t x86_test_events[]={ + .count = 2, + .codes[0] = 0x5301cd, + .codes[1] = 3, +- .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3", ++ .fstr = "hsw::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", + }, + { SRC_LINE, + .name = "hsw::mem_trans_retired:load_latency:ldlat=1000000", + .ret = PFM_ERR_ATTR_VAL, + }, + { SRC_LINE, +- .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=2", ++ .name = "hsw::mem_trans_retired:latency_above_threshold:ldlat=2:intx=0:intxcp=0", + .ret = PFM_ERR_ATTR_VAL, + }, + { SRC_LINE, ++ .name = "hsw::inst_Retired:any_p:intx", ++ .count = 1, ++ .codes[0] = 0x1005300c0, ++ .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw::inst_Retired:any_p:intx:intxcp", ++ .count = 1, ++ .codes[0] = 0x3005300c0, ++ .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=1", ++ }, ++ { SRC_LINE, ++ .name = "hsw::inst_Retired:any_p:intx=0:intxcp", ++ .count = 1, ++ .codes[0] = 0x2005300c0, ++ .fstr = "hsw::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=1", ++ }, ++ { SRC_LINE, + .name = "hsw::cycle_activity:cycles_l2_pending", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x15301a3, +- .fstr = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:t=0", ++ .fstr = "hsw::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:t=0:intx=0:intxcp=0", + }, + { SRC_LINE, + .name = "hsw::cycle_activity:cycles_l2_pending:c=8", +@@ -1929,14 +1947,14 @@ static const test_event_t x86_test_events[]={ + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x5304c8, +- .fstr = "hsw::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0", ++ .fstr = "hsw::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", + }, + { SRC_LINE, + .name = "hsw::rtm_retired:aborted", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x5304c9, +- .fstr = "hsw::RTM_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0", ++ .fstr = "hsw::RTM_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", + }, + { SRC_LINE, + .name = "ivb_unc_cbo0::unc_clockticks", + +commit f5cedb91ab060cc16f178e98a4432a17b010f2b6 +Author: Stephane Eranian +Date: Thu Aug 1 11:14:26 2013 +0200 + + add Intel Haswell intx, intxcp description + + Signed-off-by: Stephane Eranian + +diff --git a/docs/man3/libpfm_intel_hsw.3 b/docs/man3/libpfm_intel_hsw.3 +index 913577d..fb36acf 100644 +--- a/docs/man3/libpfm_intel_hsw.3 ++++ b/docs/man3/libpfm_intel_hsw.3 +@@ -50,6 +50,14 @@ Measure on both threads at the same time assuming hyper-threading is enabled. Th + Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event. + This is an integer attribute that must be in the range [3:65535]. It is required + for this event. Note that the event must be used with precise sampling (PEBS). ++.TP ++.B intx ++Monitor the event only when executing inside a transactional memory region (in tx). Event ++does not count otherwise. This is a boolean modifiers. Default value is 0. ++.TP ++.B intxcp ++Do not count occurrences of the event when they are inside an aborted transactional memory ++region. This is a boolean modifier. Default value is 0. + + .SH OFFCORE_RESPONSE events + Intel Haswell provides two offcore_response events. They are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1. -Because they do not use .occ_sel bitfield. +commit a3e9c3ec4d87c0a82e5622c6421133493e7cc0a4 +Author: Stephane Eranian +Date: Sat Aug 10 15:35:25 2013 +0200 -Signed-off-by: Stephane Eranian ---- - lib/events/intel_snbep_unc_pcu_events.h | 24 ------------------------ - 1 file changed, 24 deletions(-) + drop umask from snbep_unc_pcu:COREx_TRANSITION_CYCLES + + Because they do not use .occ_sel bitfield. + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_snbep_unc_pcu_events.h b/lib/events/intel_snbep_unc_pcu_events.h index dd4aa3e..10dc6b3 100644 @@ -266,39 +689,647 @@ index dd4aa3e..10dc6b3 100644 }, { .name = "UNC_P_DEMOTIONS_CORE0", .desc = "Core C State Demotions", --- -1.8.3.1 - -From 7af6bc46302812d29cfbc23d24430d31f09049da Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Mon, 4 Nov 2013 19:07:23 +0100 -Subject: [PATCH 07/14] add missing events/umasks for Intel Ivy Bridge - -ivb::FP_COMP_OPS_EXE:X87 -ivb::FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE -ivb::FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE -ivb::FP_COMP_OPS_EXE:SSE_PACKED_SINGLE -ivb::SIMD_FP_256:PACKED_SINGLE -ivb::SIMD_FP_256:PACKED_DOUBLE -ivb::LSD:UOPS -ivb::UOPS_EXECUTED:THREAD -ivb::ICACHE:IFETCH_STALLS -ivb::LD_BLOCKS:NO_SR -ivb::OTHER_ASSISTS:WB - -Added aliases: -ivb::DTLB_LOAD_ACCESS -> TLB_ACCESS -ivb::LONGEST_LAT_CACHE -> L3_LAT_CACHE - -Thanks to Vince Weaver for spotting those new updates in -the Sep 2013 SDM Vol3b edition. - -Also added a few more IVB validation tests. - -Signed-off-by: Stephane Eranian ---- - lib/events/intel_ivb_events.h | 132 ++++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 127 insertions(+), 5 deletions(-) +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index f351bc0..0b5decc 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1346,11 +1346,11 @@ static const test_event_t x86_test_events[]={ + .fstr = "snbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=1", + }, + { SRC_LINE, +- .name = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:C6", ++ .name = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", + .ret = PFM_SUCCESS, + .count = 1, +- .codes[0] = 0x200303, +- .fstr = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:C6:e=0:i=0:t=0", ++ .codes[0] = 0x200003, ++ .fstr = "snbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", + +commit 88c5411265da2525de1e2160a1fdd00356f0f2bd +Author: Stephane Eranian +Date: Wed Aug 14 15:22:17 2013 +0200 + + extend pfm_intel_x86_config_t with processor stepping info + + To be used in future patches where we need the stepping + to enable certain features (e.g., Intel Atom). + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_x86.c b/lib/pfmlib_intel_x86.c +index 435ce9e..34c843d 100644 +--- a/lib/pfmlib_intel_x86.c ++++ b/lib/pfmlib_intel_x86.c +@@ -160,6 +160,7 @@ pfm_intel_x86_detect(void) + + pfm_intel_x86_cfg.family = (a >> 8) & 0xf; // bits 11 - 8 + pfm_intel_x86_cfg.model = (a >> 4) & 0xf; // Bits 7 - 4 ++ pfm_intel_x86_cfg.stepping = a & 0xf; // Bits 0 - 3 + + /* extended family */ + if (pfm_intel_x86_cfg.family == 0xf) +diff --git a/lib/pfmlib_intel_x86_priv.h b/lib/pfmlib_intel_x86_priv.h +index 1671ca6..0f0c1f5 100644 +--- a/lib/pfmlib_intel_x86_priv.h ++++ b/lib/pfmlib_intel_x86_priv.h +@@ -242,6 +242,7 @@ typedef struct { + int model; + int family; /* 0 means nothing detected yet */ + int arch_version; ++ int stepping; + } pfm_intel_x86_config_t; + + extern pfm_intel_x86_config_t pfm_intel_x86_cfg; + +commit 62a92fbf78059ca6951059acbb86ff91b8f5eff9 +Author: Michael Werner +Date: Mon Aug 19 13:29:54 2013 +0200 + + Fix handling of edge, invert, threshold modifiers for Intel SNB-EP uncore PMU + + There was a bug in the handling of required modifiers for some SNB-EP + uncore PMU, such as PCU UNC_P_FREQ_BAND0_CYCLES. It was not possible + to use edge, invert or threshold modifiers. + + This patch fixes the problem and adds the necessary validation tests. + + Signed-off-by: Michael Werner + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_snbep_unc.c b/lib/pfmlib_intel_snbep_unc.c +index 94ec7de..9813e1c 100644 +--- a/lib/pfmlib_intel_snbep_unc.c ++++ b/lib/pfmlib_intel_snbep_unc.c +@@ -426,7 +426,7 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + return PFM_ERR_ATTR; + } + +- if (modmsk_r && (umodmsk ^ modmsk_r)) { ++ if (modmsk_r && !(umodmsk & modmsk_r)) { + DPRINT("required modifiers missing: 0x%x\n", modmsk_r); + return PFM_ERR_ATTR; + } +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 0b5decc..08c717a 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1401,6 +1401,38 @@ static const test_event_t x86_test_events[]={ + .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:i=0:t=0:ff=40", + }, + { SRC_LINE, ++ .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x4000b, ++ .codes[1] = 0x20, ++ .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=0:t=0:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:i", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x80000b, ++ .codes[1] = 0x20, ++ .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:i=1:t=0:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:i", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x84000b, ++ .codes[1] = 0x20, ++ .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=1:t=0:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:i:t=4", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x484000b, ++ .codes[1] = 0x20, ++ .fstr = "snbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:i=1:t=4:ff=32", ++ }, ++ { SRC_LINE, + .name = "SNBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", + .ret = PFM_SUCCESS, + .count = 1, + +commit 7b715b1255ad77b273cf3242aeb401c76b9c80b6 +Author: Stephane Eranian +Date: Mon Aug 26 20:57:53 2013 +0200 + + fix bug with PFM_OS_PERF_EVENT attributes + + There was a bug in the perf_event_mods[] attribute table + that would cause the fully qualified event string to miss + certain attributes such as mg, mh. This was due to the fact + that in a pfmlib_attr_desc_t table the entries must be ordered + by the values of the respective PERF_ATTR_XX because there is + direct indexing by attribute value. + + This patch adds a PERF_ATTR_SKIP pseudo attribute to pad the + entries and make the mg, mh aligned in the table with their + corresponding PERF_ATTR_XX macros. + + The perf_get_os_attr_info() and perf_get_os_nattrs() are modified + to skip entries. + + Note that PERF_SKIP_ENTRIES is ONLY supported for the + perf_event OS attributes for now. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_x86_perf_event.c b/lib/pfmlib_intel_x86_perf_event.c +index f29af94..cbb9cb3 100644 +--- a/lib/pfmlib_intel_x86_perf_event.c ++++ b/lib/pfmlib_intel_x86_perf_event.c +@@ -271,7 +271,9 @@ pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + } + + if (compact) { ++ /* e->npattrs modified by call */ + pfmlib_compact_pattrs(e, i); ++ /* compensate for i++ */ + i--; + } + } +diff --git a/lib/pfmlib_perf_event.c b/lib/pfmlib_perf_event.c +index 91465d4..1686140 100644 +--- a/lib/pfmlib_perf_event.c ++++ b/lib/pfmlib_perf_event.c +@@ -44,6 +44,10 @@ static const pfmlib_attr_desc_t perf_event_mods[]={ + PFM_ATTR_B("u", "monitor at user level"), /* monitor user level */ + PFM_ATTR_B("k", "monitor at kernel level"), /* monitor kernel level */ + PFM_ATTR_B("h", "monitor at hypervisor level"), /* monitor hypervisor level */ ++ PFM_ATTR_SKIP, ++ PFM_ATTR_SKIP, ++ PFM_ATTR_SKIP, ++ PFM_ATTR_SKIP, + PFM_ATTR_B("mg", "monitor guest execution"), /* monitor guest level */ + PFM_ATTR_B("mh", "monitor host execution"), /* monitor host level */ + PFM_ATTR_NULL /* end-marker to avoid exporting number of entries */ +@@ -312,11 +316,12 @@ static int + perf_get_os_nattrs(void *this, pfmlib_event_desc_t *e) + { + pfmlib_os_t *os = this; +- int i = 0; ++ int i, n = 0; + +- for (; os->atdesc[i].name; i++); +- +- return i; ++ for (i = 0; os->atdesc[i].name; i++) ++ if (!is_empty_attr(os->atdesc+i)) ++ n++; ++ return n; + } + + static int +@@ -324,10 +329,14 @@ perf_get_os_attr_info(void *this, pfmlib_event_desc_t *e) + { + pfmlib_os_t *os = this; + pfm_event_attr_info_t *info; +- int i, j = e->npattrs; ++ int i, k, j = e->npattrs; ++ ++ for (i = k = 0; os->atdesc[i].name; i++) { ++ /* skip padding entries */ ++ if (is_empty_attr(os->atdesc+i)) ++ continue; + +- for (i = 0; os->atdesc[i].name; i++, j++) { +- info = e->pattrs+j; ++ info = e->pattrs + j + k; + + info->name = os->atdesc[i].name; + info->desc = os->atdesc[i].desc; +@@ -337,8 +346,9 @@ perf_get_os_attr_info(void *this, pfmlib_event_desc_t *e) + info->type = os->atdesc[i].type; + info->is_dfl = 0; + info->ctrl = PFM_ATTR_CTRL_PERF_EVENT; ++ k++; + } +- e->npattrs += i; ++ e->npattrs += k; + + return PFM_SUCCESS; + } +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 758b65d..38d8110 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -25,6 +25,7 @@ + #ifndef __PFMLIB_PRIV_H__ + #define __PFMLIB_PRIV_H__ + #include ++#include + + #define PFM_PLM_ALL (PFM_PLM0|PFM_PLM1|PFM_PLM2|PFM_PLM3|PFM_PLMH) + +@@ -34,6 +35,7 @@ + + #define PFM_ATTR_I(y, d) { .name = (y), .type = PFM_ATTR_MOD_INTEGER, .desc = (d) } + #define PFM_ATTR_B(y, d) { .name = (y), .type = PFM_ATTR_MOD_BOOL, .desc = (d) } ++#define PFM_ATTR_SKIP { .name = "" } /* entry not populated (skipped) */ + #define PFM_ATTR_NULL { .name = NULL } + + #define PFMLIB_EVT_MAX_NAME_LEN 256 +@@ -372,4 +374,10 @@ pfmlib_pidx2idx(pfmlib_pmu_t *pmu, int pidx) + .os_detect[PFM_OS_PERF_EVENT_EXT] = NULL + #endif + ++static inline int ++is_empty_attr(const pfmlib_attr_desc_t *a) ++{ ++ return !a || !a->name || strlen(a->name) == 0 ? 1 : 0; ++} ++ + #endif /* __PFMLIB_PRIV_H__ */ + +commit 59c86f89471a5a0f02c4d020eac83e6a6306810e +Author: Stephane Eranian +Date: Thu Oct 3 13:51:49 2013 +0200 + + add PFMLIB_PMU_FL_NO_SMPL pmu flag + + Add PFMLIB_PMU_FL_NO_SMPL as a generic PMU flag + (pmu->flags) to indicate that the PMU does not + support sampling. + + This flag can be used to prohibit using sampling + related modifiers in the OS layer, for instance. + + The patch updates the SNB-EP uncore PMUs to use this + flag because they do not support sampling. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_ivb_unc.c b/lib/pfmlib_intel_ivb_unc.c +index c2f2165..d3160d2 100644 +--- a/lib/pfmlib_intel_ivb_unc.c ++++ b/lib/pfmlib_intel_ivb_unc.c +@@ -64,7 +64,8 @@ pfmlib_pmu_t intel_ivb_unc_cbo##n##_support={ \ + .max_encoding = 1,\ + .pe = intel_snb_unc_##p##_pe, \ + .atdesc = intel_x86_mods, \ +- .flags = PFMLIB_PMU_FL_RAW_UMASK, \ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_ivb_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ +diff --git a/lib/pfmlib_intel_snb_unc.c b/lib/pfmlib_intel_snb_unc.c +index b0be6e7..b76c5c0 100644 +--- a/lib/pfmlib_intel_snb_unc.c ++++ b/lib/pfmlib_intel_snb_unc.c +@@ -64,7 +64,8 @@ pfmlib_pmu_t intel_snb_unc_cbo##n##_support={ \ + .max_encoding = 1,\ + .pe = intel_snb_unc_##p##_pe, \ + .atdesc = intel_x86_mods, \ +- .flags = PFMLIB_PMU_FL_RAW_UMASK, \ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_snb_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_nhm_unc_get_perf_encoding), \ +diff --git a/lib/pfmlib_intel_snbep_unc_cbo.c b/lib/pfmlib_intel_snbep_unc_cbo.c +index 8ebd13e..b1dd1d0 100644 +--- a/lib/pfmlib_intel_snbep_unc_cbo.c ++++ b/lib/pfmlib_intel_snbep_unc_cbo.c +@@ -80,7 +80,8 @@ pfmlib_pmu_t intel_snbep_unc_cb##n##_support = {\ + .max_encoding = 2,\ + .pe = intel_snbep_unc_c_pe,\ + .atdesc = snbep_unc_mods,\ +- .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ +diff --git a/lib/pfmlib_intel_snbep_unc_ha.c b/lib/pfmlib_intel_snbep_unc_ha.c +index e50ce0d..28e6b71 100644 +--- a/lib/pfmlib_intel_snbep_unc_ha.c ++++ b/lib/pfmlib_intel_snbep_unc_ha.c +@@ -76,7 +76,8 @@ pfmlib_pmu_t intel_snbep_unc_ha_support = { + .max_encoding = 3, /* address matchers */ + .pe = intel_snbep_unc_h_pe, + .atdesc = snbep_unc_mods, +- .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK ++ | PFMLIB_PMU_FL_NO_SMPL, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), +diff --git a/lib/pfmlib_intel_snbep_unc_imc.c b/lib/pfmlib_intel_snbep_unc_imc.c +index 35bfa69..c0cc0e1 100644 +--- a/lib/pfmlib_intel_snbep_unc_imc.c ++++ b/lib/pfmlib_intel_snbep_unc_imc.c +@@ -46,7 +46,8 @@ pfmlib_pmu_t intel_snbep_unc_imc##n##_support = { \ + .max_encoding = 1, \ + .pe = intel_snbep_unc_m_pe, \ + .atdesc = snbep_unc_mods, \ +- .flags = PFMLIB_PMU_FL_RAW_UMASK, \ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_intel_snbep_unc_detect, \ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ +diff --git a/lib/pfmlib_intel_snbep_unc_pcu.c b/lib/pfmlib_intel_snbep_unc_pcu.c +index fb4499f..5d4dd47 100644 +--- a/lib/pfmlib_intel_snbep_unc_pcu.c ++++ b/lib/pfmlib_intel_snbep_unc_pcu.c +@@ -78,7 +78,8 @@ pfmlib_pmu_t intel_snbep_unc_pcu_support = { + .max_encoding = 2, + .pe = intel_snbep_unc_p_pe, + .atdesc = snbep_unc_mods, +- .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_PMU_FL_UNC_OCC, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_PMU_FL_UNC_OCC ++ | PFMLIB_PMU_FL_NO_SMPL, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), +diff --git a/lib/pfmlib_intel_snbep_unc_perf_event.c b/lib/pfmlib_intel_snbep_unc_perf_event.c +index 601806f..e6cc625 100644 +--- a/lib/pfmlib_intel_snbep_unc_perf_event.c ++++ b/lib/pfmlib_intel_snbep_unc_perf_event.c +@@ -110,6 +110,8 @@ pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) + void + pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + { ++ pfmlib_pmu_t *pmu = this; ++ int no_smpl = pmu->flags & PFMLIB_PMU_FL_NO_SMPL; + int i, compact; + + for (i = 0; i < e->npattrs; i++) { +@@ -130,11 +132,20 @@ pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + if (e->pattrs[i].idx == PERF_ATTR_H) + compact = 1; + ++ if (no_smpl ++ && ( e->pattrs[i].idx == PERF_ATTR_FR ++ || e->pattrs[i].idx == PERF_ATTR_PR ++ || e->pattrs[i].idx == PERF_ATTR_PE)) ++ compact = 1; ++ + /* + * uncore has no priv level support + */ +- if ( e->pattrs[i].idx == PERF_ATTR_U +- || e->pattrs[i].idx == PERF_ATTR_K) ++ if (pmu->supported_plm == 0 ++ && ( e->pattrs[i].idx == PERF_ATTR_U ++ || e->pattrs[i].idx == PERF_ATTR_K ++ || e->pattrs[i].idx == PERF_ATTR_MG ++ || e->pattrs[i].idx == PERF_ATTR_MH)) + compact = 1; + } + +diff --git a/lib/pfmlib_intel_snbep_unc_qpi.c b/lib/pfmlib_intel_snbep_unc_qpi.c +index 985a494..9cc4bac 100644 +--- a/lib/pfmlib_intel_snbep_unc_qpi.c ++++ b/lib/pfmlib_intel_snbep_unc_qpi.c +@@ -65,7 +65,8 @@ pfmlib_pmu_t intel_snbep_unc_qpi##n##_support = {\ + .max_encoding = 3,\ + .pe = intel_snbep_unc_q_pe,\ + .atdesc = snbep_unc_mods,\ +- .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ +diff --git a/lib/pfmlib_intel_snbep_unc_r2pcie.c b/lib/pfmlib_intel_snbep_unc_r2pcie.c +index 1fd3ca8..c6a64b9 100644 +--- a/lib/pfmlib_intel_snbep_unc_r2pcie.c ++++ b/lib/pfmlib_intel_snbep_unc_r2pcie.c +@@ -45,7 +45,8 @@ pfmlib_pmu_t intel_snbep_unc_r2pcie_support = { + .max_encoding = 1, + .pe = intel_snbep_unc_r2_pe, + .atdesc = snbep_unc_mods, +- .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK ++ | PFMLIB_PMU_FL_NO_SMPL, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), +diff --git a/lib/pfmlib_intel_snbep_unc_r3qpi.c b/lib/pfmlib_intel_snbep_unc_r3qpi.c +index 288abb1..28bb83a 100644 +--- a/lib/pfmlib_intel_snbep_unc_r3qpi.c ++++ b/lib/pfmlib_intel_snbep_unc_r3qpi.c +@@ -46,7 +46,8 @@ pfmlib_pmu_t intel_snbep_unc_r3qpi##n##_support = {\ + .max_encoding = 1,\ + .pe = intel_snbep_unc_r3_pe,\ + .atdesc = snbep_unc_mods,\ +- .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK\ ++ | PFMLIB_PMU_FL_NO_SMPL,\ + .pmu_detect = pfm_intel_snbep_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ +diff --git a/lib/pfmlib_intel_snbep_unc_ubo.c b/lib/pfmlib_intel_snbep_unc_ubo.c +index b9b4585..3b8abff 100644 +--- a/lib/pfmlib_intel_snbep_unc_ubo.c ++++ b/lib/pfmlib_intel_snbep_unc_ubo.c +@@ -45,7 +45,8 @@ pfmlib_pmu_t intel_snbep_unc_ubo_support = { + .max_encoding = 1, + .pe = intel_snbep_unc_u_pe, + .atdesc = snbep_unc_mods, +- .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK ++ | PFMLIB_PMU_FL_NO_SMPL, + .pmu_detect = pfm_intel_snbep_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), +diff --git a/lib/pfmlib_intel_x86_perf_event.c b/lib/pfmlib_intel_x86_perf_event.c +index cbb9cb3..a7a2d4d 100644 +--- a/lib/pfmlib_intel_x86_perf_event.c ++++ b/lib/pfmlib_intel_x86_perf_event.c +@@ -233,6 +233,7 @@ pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + pfmlib_pmu_t *pmu = this; + int i, compact; + int has_pebs = intel_x86_event_has_pebs(this, e); ++ int no_smpl = pmu->flags & PFMLIB_PMU_FL_NO_SMPL; + + for (i = 0; i < e->npattrs; i++) { + compact = 0; +@@ -261,12 +262,19 @@ pfm_intel_x86_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + if (e->pattrs[i].idx == PERF_ATTR_H) + compact = 1; + ++ if (no_smpl ++ && ( e->pattrs[i].idx == PERF_ATTR_FR ++ || e->pattrs[i].idx == PERF_ATTR_PR ++ || e->pattrs[i].idx == PERF_ATTR_PE)) ++ compact = 1; + /* +- * uncore has no priv level support ++ * no priv level support + */ +- if (pmu->type == PFM_PMU_TYPE_UNCORE +- && (e->pattrs[i].idx == PERF_ATTR_U +- || e->pattrs[i].idx == PERF_ATTR_K)) ++ if (pmu->supported_plm == 0 ++ && ( e->pattrs[i].idx == PERF_ATTR_U ++ || e->pattrs[i].idx == PERF_ATTR_K ++ || e->pattrs[i].idx == PERF_ATTR_MG ++ || e->pattrs[i].idx == PERF_ATTR_MH)) + compact = 1; + } + +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 38d8110..d3ed361 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -156,6 +156,7 @@ typedef struct { + #define PFMLIB_PMU_FL_ACTIVE 0x2 /* PMU is initialized + detected on host */ + #define PFMLIB_PMU_FL_RAW_UMASK 0x4 /* PMU supports PFM_ATTR_RAW_UMASKS */ + #define PFMLIB_PMU_FL_ARCH_DFL 0x8 /* PMU is arch default */ ++#define PFMLIB_PMU_FL_NO_SMPL 0x10 /* PMU does not support sampling */ + + typedef struct { + int initdone; + +commit 31a7d65a8f61a45fad197d1394d8cce12f7652f3 +Author: Stephane Eranian +Date: Thu Oct 3 13:58:01 2013 +0200 + + grab PMU perf_event type from sysfs + + This patch enables grabbing the attr->type from sysfs for + PMU models which provide the pmu->perf_name value. Otherwise, + the type default to PERF_TYPE_RAW (which works only for core PMU). + + this is useful for uncore PMUs as their type is usually assigned + dynamically. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_x86_perf_event.c b/lib/pfmlib_intel_x86_perf_event.c +index a7a2d4d..460a2c8 100644 +--- a/lib/pfmlib_intel_x86_perf_event.c ++++ b/lib/pfmlib_intel_x86_perf_event.c +@@ -99,8 +99,24 @@ pfm_intel_x86_get_perf_encoding(void *this, pfmlib_event_desc_t *e) + DPRINT("%s: unsupported count=%d\n", e->count); + return PFM_ERR_NOTSUPP; + } +- ++ /* default PMU type */ + attr->type = PERF_TYPE_RAW; ++ ++ /* ++ * if PMU specifies a perf PMU name, then grab the type ++ * from sysfs as it is most likely dynamically assigned. ++ * This allows this function to use used by some uncore PMUs ++ */ ++ if (pmu->perf_name) { ++ int type = find_pmu_type_by_name(pmu->perf_name); ++ if (type == PFM_ERR_NOTSUPP) { ++ DPRINT("perf PMU %s, not supported by OS\n", pmu->perf_name); ++ } else { ++ DPRINT("PMU %s perf type=%d\n", pmu->name, type); ++ attr->type = type; ++ } ++ } ++ + attr->config = e->codes[0]; + + if (e->count > 1) { + +commit 9fb795c7f4142bddf9d66fa577290bf4e42953d7 +Author: Stephane Eranian +Date: Fri Oct 11 13:35:19 2013 +0200 + + validate : check if PMU is supported by library + + On some configurations, it may be that support for a particular + PMU is disabled at compile time. Yet, the x86 validation suite + ignores that fact, so we may get errors because of unsupported + PMU. Catch those and don't consider them as errors, just print + a warning. + + Signed-off-by: Stephane Eranian + +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 08c717a..7e93533 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -2002,6 +2002,34 @@ static const test_event_t x86_test_events[]={ + }; + #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) + ++static int ++check_pmu_supported(const char *evt) ++{ ++ pfm_pmu_info_t info; ++ char *p; ++ int i, ret; ++ ++ memset(&info, 0, sizeof(info)); ++ info.size = sizeof(info); ++ ++ /* look for pmu_name::.... */ ++ p = strchr(evt, ':'); ++ if (!p) ++ return 1; ++ if (*(p+1) != ':') ++ return 1; ++ ++ pfm_for_all_pmus(i) { ++ ret = pfm_get_pmu_info(i, &info); ++ if (ret != PFM_SUCCESS) ++ continue; ++ if (!strncmp(info.name, evt, p - evt)) ++ return 1; ++ } ++ /* PMU not there */ ++ return 0; ++} ++ + static int check_test_events(FILE *fp) + { + const test_event_t *e; +@@ -2016,6 +2044,10 @@ static int check_test_events(FILE *fp) + fstr = NULL; + ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count); + if (ret != e->ret) { ++ if (ret == PFM_ERR_NOTFOUND && !check_pmu_supported(e->name)) { ++ fprintf(fp,"Line %d, Event%d %s, skipped because no PMU support\n", e->line, i, e->name); ++ continue; ++ } + fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret); + errors++; + } else { +commit 7af6bc46302812d29cfbc23d24430d31f09049da +Author: Stephane Eranian +Date: Mon Nov 4 19:07:23 2013 +0100 + + add missing events/umasks for Intel Ivy Bridge + + ivb::FP_COMP_OPS_EXE:X87 + ivb::FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE + ivb::FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE + ivb::FP_COMP_OPS_EXE:SSE_PACKED_SINGLE + ivb::SIMD_FP_256:PACKED_SINGLE + ivb::SIMD_FP_256:PACKED_DOUBLE + ivb::LSD:UOPS + ivb::UOPS_EXECUTED:THREAD + ivb::ICACHE:IFETCH_STALLS + ivb::LD_BLOCKS:NO_SR + ivb::OTHER_ASSISTS:WB + + Added aliases: + ivb::DTLB_LOAD_ACCESS -> TLB_ACCESS + ivb::LONGEST_LAT_CACHE -> L3_LAT_CACHE + + Thanks to Vince Weaver for spotting those new updates in + the Sep 2013 SDM Vol3b edition. + + Also added a few more IVB validation tests. + + Signed-off-by: Stephane Eranian diff --git a/lib/events/intel_ivb_events.h b/lib/events/intel_ivb_events.h index e473756..3c5583e 100644 @@ -509,27 +1540,81 @@ index e473756..3c5583e 100644 { .name = "OFFCORE_RESPONSE_0", .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", .modmsk = INTEL_V3_ATTRS, --- -1.8.3.1 - -From fe3e6e865e98cd7f1743a26896e777873ae8b682 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Mon, 11 Nov 2013 17:58:19 +0100 -Subject: [PATCH 08/14] add missing Core select umasks to AMD Fam15h event - table - -As documented in BKDG Fam15 rev 3.08. - -As per encoding, the core_select umasks cannot be combined. -User has to select either ANY_CORE or one specific core, e.g., -CORE_1. Default is ANY_CORE for all relevant events. +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 7e93533..955df41 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1062,7 +1062,21 @@ static const test_event_t x86_test_events[]={ + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x53045f, +- .fstr = "ivb::TLB_ACCESS:LOAD_STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", ++ .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivb::TLB_ACCESS:STLB_HIT", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x53045f, ++ .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivb::DTLB_LOAD_ACCESS:STLB_HIT", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x53045f, ++ .fstr = "ivb::DTLB_LOAD_ACCESS:STLB_HIT:k=1:u=1:e=0:i=0:c=0:t=0", + }, + { SRC_LINE, + .name = "ivb::MOVE_ELIMINATION:INT_NOT_ELIMINATED", +@@ -1086,6 +1100,31 @@ static const test_event_t x86_test_events[]={ + .fstr = "ivb::RESOURCE_STALLS:RS:ROB:k=1:u=1:e=0:i=0:c=0:t=0", + }, + { SRC_LINE, ++ .name = "ivb::UOPS_EXECUTED:THREAD", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x5301b1, ++ .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=0:i=0:c=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivb::UOPS_EXECUTED:THREAD:e:c=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x15701b1, ++ .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=1:i=0:c=1:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivb::UOPS_EXECUTED:THREAD:e", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivb::UOPS_EXECUTED:THREAD:c=1:i", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1d301b1, ++ .fstr = "ivb::UOPS_EXECUTED:THREAD:k=1:u=1:e=0:i=1:c=1:t=0", ++ }, ++ { SRC_LINE, + .name = "ivb::CPU_CLK_UNHALTED:REF_P", + .ret = PFM_SUCCESS, + .count = 1, -Patch adds corresponding tests to validation test suite. +commit fe3e6e865e98cd7f1743a26896e777873ae8b682 +Author: Stephane Eranian +Date: Mon Nov 11 17:58:19 2013 +0100 -Signed-off-by: Stephane Eranian ---- - lib/events/amd64_events_fam15h.h | 84 ++++++++++++++++++++++++++++++++++------ - 1 file changed, 72 insertions(+), 12 deletions(-) + add missing Core select umasks to AMD Fam15h event table + + As documented in BKDG Fam15 rev 3.08. + + As per encoding, the core_select umasks cannot be combined. + User has to select either ANY_CORE or one specific core, e.g., + CORE_1. Default is ANY_CORE for all relevant events. + + Patch adds corresponding tests to validation test suite. + + Signed-off-by: Stephane Eranian diff --git a/lib/events/amd64_events_fam15h.h b/lib/events/amd64_events_fam15h.h index 5738e4c..ac2b111 100644 @@ -665,22 +1750,372 @@ index 5738e4c..ac2b111 100644 .umasks = amd64_fam15h_read_request_to_l3_cache, }, { .name = "L3_LATENCY", --- -1.8.3.1 +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 955df41..0fc36c7 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1917,6 +1917,42 @@ static const test_event_t x86_test_events[]={ + .fstr = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0xff:k=0:u=1:e=0:i=0:c=0:h=0:g=0" + }, + { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_modify:core_3", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x4005334e0ull, ++ .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_MODIFY:CORE_3", ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x40053f7e0ull, ++ .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_ANY:ANY_CORE", ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:PREFETCH:READ_BLOCK_MODIFY:core_4", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x400534de0ull, ++ .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:READ_BLOCK_MODIFY:PREFETCH:CORE_4", ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1", ++ .ret = PFM_ERR_FEATCOMB, /* must use individual umasks to combine with prefetch */ ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1:core_3", ++ .ret = PFM_ERR_FEATCOMB, /* core umasks cannot be combined */ ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:prefetch:core_0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x4005308e0ull, ++ .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:PREFETCH:CORE_0", ++ }, ++ { SRC_LINE, + .name = "ivb_ep::mem_load_uops_llc_miss_retired:local_dram", + .ret = PFM_SUCCESS, + .count = 1, -From 59bc6b3c586561137d9c1172a34deac3f8887999 Mon Sep 17 00:00:00 2001 -From: Andreas Beckmann -Date: Thu, 28 Nov 2013 10:39:45 +0100 -Subject: [PATCH 09/14] fix typos in event description for Cortex A9 and P4 +commit 751acd759e6185d2a378afa5203189011f108afb +Author: Stephane Eranian +Date: Tue Oct 8 14:12:32 2013 +0200 + + add Intel RAPL PMU support + + This patch adds support for the Intel RAPL energy consumption + counters present on Intel SandyBridge, IvyBridge and Haswell + processors. + + The PMU is detected based on OS-support, i.e., the + /sys/devices/power directory must exist. + + The following RAPL events are defined: + - RAPL_ENERGY_CORES + - RAPL_ENERGY_PKG + - RAPL_EENRGY_DRAM (servers only) + + The new PMU is called rapl. + + The library does not provide any unit conversion for the + RAW count. The kernel exports the raw count as increments + of 1/(2^32) Joules or about 0.23 nano-Joules. + + Signed-off-by: Stephane Eranian + +diff --git a/docs/man3/libpfm_intel_rapl.3 b/docs/man3/libpfm_intel_rapl.3 +new file mode 100644 +index 0000000..cf7835c +--- /dev/null ++++ b/docs/man3/libpfm_intel_rapl.3 +@@ -0,0 +1,39 @@ ++.TH LIBPFM 3 "November, 2013" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_rapl - support for Intel RAPL PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: rapl ++.B PMU desc: Intel RAPL (Intel SandyBridge, IvyBridge, Haswell) ++.sp ++.SH DESCRIPTION ++The library supports the Intel Running Average Power Limit (RAPL) ++energy consomption counters. This is a socket-level set of counters ++which reports energy consumption in Joules. There are up to 3 counters ++each measuring only one event. The following events are defined: ++.TP ++.B RAPL_ENERGY_CORES ++On all processors, the event reports the number of Joules consumed by all cores. ++ On all processors, ++.TP ++.B RAPL_ENERGYC_PKG ++On all processors, th event reports the number of Joules consumed by all ++the cores and Last Level cache (L3). ++.TP ++.B RAPL_ENERGY_DRAM ++On server processors, the event reports the number of Joules consumed ++n by the DRAM controller. ++ ++By construction, the events are socket-level and can only be measured in ++system-wide mode. It is necessary and sufficient to measure only one CPU ++per socket to get meaningful results. ++ ++.SH MODIFIERS ++The PMU does not support any modifiers. ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index 89b9fd8..85c0022 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -191,6 +191,7 @@ typedef enum { + PFM_PMU_INTEL_IVB_UNC_CB3, /* Intel IvyBridge C-box 3 uncore PMU */ + + PFM_PMU_POWER8, /* IBM POWER8 */ ++ PFM_PMU_INTEL_RAPL, /* Intel RAPL */ + + /* MUST ADD NEW PMU MODELS HERE */ + +diff --git a/lib/Makefile b/lib/Makefile +index 98411b8..e5f5d5f 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -60,6 +60,7 @@ SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ + pfmlib_intel_snb.c pfmlib_intel_snb_unc.c \ + pfmlib_intel_ivb.c pfmlib_intel_ivb_unc.c \ + pfmlib_intel_hsw.c \ ++ pfmlib_intel_rapl.c \ + pfmlib_intel_snbep_unc.c \ + pfmlib_intel_snbep_unc_cbo.c \ + pfmlib_intel_snbep_unc_ha.c \ +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index e810eca..bf28291 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -97,6 +97,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &intel_ivb_unc_cbo3_support, + &intel_ivb_ep_support, + &intel_hsw_support, ++ &intel_rapl_support, + &intel_snbep_unc_cb0_support, + &intel_snbep_unc_cb1_support, + &intel_snbep_unc_cb2_support, +diff --git a/lib/pfmlib_intel_rapl.c b/lib/pfmlib_intel_rapl.c +new file mode 100644 +index 0000000..25c51f6 +--- /dev/null ++++ b/lib/pfmlib_intel_rapl.c +@@ -0,0 +1,154 @@ ++/* ++ * pfmlib_intel_rapl.c : Intel RAPL PMU ++ * ++ * Copyright (c) 2013 Google, Inc ++ * Contributed by Stephane Eranian ++ * ++ * Based on: ++ * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * RAPL PMU (SNB, IVB, HSW) ++ */ ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++/* ++ * for now, we reuse the x86 table entry format and callback to avoid duplicating ++ * code. We may revisit this later on ++ */ ++#include "pfmlib_intel_x86_priv.h" ++ ++extern pfmlib_pmu_t intel_rapl_support; ++ ++#define RAPL_COMMON_EVENTS \ ++ { .name = "RAPL_ENERGY_CORES",\ ++ .desc = "Number of Joules consumed by all cores on the package. Unit is 2^-32 Joules",\ ++ .cntmsk = 0x1,\ ++ .code = 0x1,\ ++ },\ ++ { .name = "RAPL_ENERGY_PKG",\ ++ .desc = "Number of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 Joules",\ ++ .cntmsk = 0x2,\ ++ .code = 0x2,\ ++ } ++ ++static const intel_x86_entry_t intel_rapl_cln_pe[]={ ++ RAPL_COMMON_EVENTS ++}; ++ ++static const intel_x86_entry_t intel_rapl_srv_pe[]={ ++ RAPL_COMMON_EVENTS, ++ { .name = "RAPL_ENERGY_DRAM", ++ .desc = "Number of Joules consumed by the DRAM. Unit is 2^-32 Joules", ++ .cntmsk = 0x4, ++ .code = 0x3, ++ }, ++}; ++ ++static int ++pfm_rapl_detect(void *this) ++{ ++ int ret; ++ ++ ret = pfm_intel_x86_detect(); ++ if (ret != PFM_SUCCESS) ++ return ret; ++ ++ if (pfm_intel_x86_cfg.family != 6) ++ return PFM_ERR_NOTSUPP; ++ ++ switch(pfm_intel_x86_cfg.model) { ++ case 42: /* Sandy Bridge */ ++ case 58: /* Ivy Bridge */ ++ case 70: /* Haswell */ ++ /* already setup by default */ ++ break; ++ case 45: /* Sandy Bridg-EP */ ++ case 62: /* Ivy Bridge-EP */ ++ intel_rapl_support.pe = intel_rapl_srv_pe; ++ intel_rapl_support.pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_srv_pe); ++ break; ++ default: ++ return PFM_ERR_NOTSUPP; ++ } ++ return PFM_SUCCESS; ++} ++ ++static int ++pfm_intel_rapl_get_encoding(void *this, pfmlib_event_desc_t *e) ++ ++{ ++ pfmlib_pmu_t *pmu = this; ++ const intel_x86_entry_t *pe; ++ ++ /* shut up the compiler */ ++ pmu = pmu; ++ ++ pe = this_pe(this); ++ ++ e->fstr[0] = '\0'; ++ ++ e->codes[0] = pe[e->event].code; ++ e->count = 1; ++ evt_strcat(e->fstr, "%s", pe[e->event].name); ++ ++ __pfm_vbprintf("[0x%"PRIx64" event=0x%x] %s\n", ++ e->codes[0], ++ e->codes[0], e->fstr); ++ ++ return PFM_SUCCESS; ++} ++ ++/* ++ * number modifiers for RAPL ++ * define an empty modifier to avoid firing the ++ * sanity pfm_intel_x86_validate_table(). We are ++ * using this function to avoid duplicating code. ++ */ ++static const pfmlib_attr_desc_t rapl_mods[]= ++{}; ++ ++pfmlib_pmu_t intel_rapl_support={ ++ .desc = "Intel RAPL", ++ .name = "rapl", ++ .perf_name = "power", ++ .pmu = PFM_PMU_INTEL_RAPL, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_rapl_cln_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .num_cntrs = 0, ++ .num_fixed_cntrs = 3, ++ .max_encoding = 1, ++ .pe = intel_rapl_cln_pe, /* default, maybe updated */ ++ .pmu_detect = pfm_rapl_detect, ++ .atdesc = rapl_mods, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_rapl_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index d3ed361..59e4235 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -240,6 +240,7 @@ extern pfmlib_pmu_t intel_ivb_unc_cbo2_support; + extern pfmlib_pmu_t intel_ivb_unc_cbo3_support; + extern pfmlib_pmu_t intel_ivb_ep_support; + extern pfmlib_pmu_t intel_hsw_support; ++extern pfmlib_pmu_t intel_rapl_support; + extern pfmlib_pmu_t intel_snbep_unc_cb0_support; + extern pfmlib_pmu_t intel_snbep_unc_cb1_support; + extern pfmlib_pmu_t intel_snbep_unc_cb2_support; +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 0fc36c7..6690a96 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -2074,6 +2074,24 @@ static const test_event_t x86_test_events[]={ + .name = "ivb_unc_cbo1::unc_clockticks", + .ret = PFM_ERR_NOTFOUND + }, ++ { SRC_LINE, ++ .name = "rapl::rapl_energy_cores", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1, ++ .fstr = "rapl::RAPL_ENERGY_CORES", ++ }, ++ { SRC_LINE, ++ .name = "rapl::rapl_energy_pkg", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x2, ++ .fstr = "rapl::RAPL_ENERGY_PKG", ++ }, ++ { SRC_LINE, ++ .name = "rapl::rapl_energy_cores:u", ++ .ret = PFM_ERR_ATTR, ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) + -Event description typos fixes. +commit 59bc6b3c586561137d9c1172a34deac3f8887999 +Author: Andreas Beckmann +Date: Thu Nov 28 10:39:45 2013 +0100 -Signed-off-by: Andreas Beckmann ---- - lib/events/arm_cortex_a8_events.h | 2 +- - lib/events/arm_cortex_a9_events.h | 2 +- - lib/events/intel_netburst_events.h | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) + fix typos in event description for Cortex A9 and P4 + + Event description typos fixes. + + Signed-off-by: Andreas Beckmann diff --git a/lib/events/arm_cortex_a8_events.h b/lib/events/arm_cortex_a8_events.h index 467813e..2b61dda 100644 @@ -721,27 +2156,81 @@ index 73f58da..e24f22f 100644 "together are treated as a single 5-bit value", .event_select = 0x1A, .escr_select = 0x6, --- -1.8.3.1 - -From e4ced34f7558780ebb204f4fede45f9eeebfacb7 Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Sun, 22 Sep 2013 22:16:12 +0200 -Subject: [PATCH 10/14] add Intel Silvermont core PMU support - -Add support for Intel Silvermont Atom processors. -Note that there is not support for the Average Latency measurement -in this patch. +commit e4ced34f7558780ebb204f4fede45f9eeebfacb7 +Author: Stephane Eranian +Date: Sun Sep 22 22:16:12 2013 +0200 -Based on the Software Optimization Guide, Chapter 15. - -Signed-off-by: Stephane Eranian ---- - lib/events/intel_slm_events.h | 896 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 896 insertions(+) - create mode 100644 lib/events/intel_slm_events.h + add Intel Silvermont core PMU support + + Add support for Intel Silvermont Atom processors. + + Note that there is not support for the Average Latency measurement + in this patch. + + Based on the Software Optimization Guide, Chapter 15. + + Signed-off-by: Stephane Eranian +diff --git a/README b/README +index 905b768..6f83e2b 100644 +--- a/README ++++ b/README +@@ -48,6 +48,7 @@ The library supports many PMUs. The current version can handle: + Intel Sandy Bridge + Intel Ivy Bridge + Intel Haswell ++ Intel Silvermont + Intel Knights Corner + Intel architectural perfmon v1, v2, v3 + +diff --git a/docs/Makefile b/docs/Makefile +index 59678f4..23cd70d 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -46,6 +46,7 @@ ARCH_MAN=libpfm_intel_core.3 \ + libpfm_intel_ivb.3 \ + libpfm_intel_ivb_unc.3 \ + libpfm_intel_hsw.3 \ ++ libpfm_intel_slm.3 \ + libpfm_intel_snbep_unc_cbo.3 \ + libpfm_intel_snbep_unc_ha.3 \ + libpfm_intel_snbep_unc_imc.3 \ +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index 85c0022..b89e661 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -193,6 +193,8 @@ typedef enum { + PFM_PMU_POWER8, /* IBM POWER8 */ + PFM_PMU_INTEL_RAPL, /* Intel RAPL */ + ++ PFM_PMU_INTEL_SLM, /* Intel Silvermont */ ++ + /* MUST ADD NEW PMU MODELS HERE */ + + PFM_PMU_MAX /* end marker */ +diff --git a/lib/Makefile b/lib/Makefile +index e5f5d5f..02dcfbb 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -71,6 +71,7 @@ SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ + pfmlib_intel_snbep_unc_r2pcie.c \ + pfmlib_intel_snbep_unc_r3qpi.c \ + pfmlib_intel_knc.c \ ++ pfmlib_intel_slm.c \ + pfmlib_intel_netburst.c \ + pfmlib_amd64_k7.c pfmlib_amd64_k8.c pfmlib_amd64_fam10h.c \ + pfmlib_amd64_fam11h.c pfmlib_amd64_fam12h.c \ +@@ -217,7 +218,8 @@ INC_X86= pfmlib_intel_x86_priv.h \ + events/intel_snbep_unc_ubo_events.h \ + events/intel_snbep_unc_r2pcie_events.h \ + events/intel_snbep_unc_r3qpi_events.h \ +- events/intel_knc_events.h ++ events/intel_knc_events.h \ ++ events/intel_slm_events.h + + INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h + diff --git a/lib/events/intel_slm_events.h b/lib/events/intel_slm_events.h new file mode 100644 index 0000000..c540e64 @@ -1644,35 +3133,280 @@ index 0000000..c540e64 + .umasks = slm_offcore_response, /* identical to actual umasks list for this event */ +}, +}; --- -1.8.3.1 - -From 93f4b19b49ee849cd3f822e87be12238305c40ba Mon Sep 17 00:00:00 2001 -From: Stephane Eranian -Date: Sun, 1 Dec 2013 10:27:53 +0100 -Subject: [PATCH 11/14] add AMD Fam15h Norhtbridge PMU support - -This patch adds proper support for AMD Fam15h uncore PMU -(Northbridge). - -The Northbridge (NB) events were in the core PMU event -list before. But on Fam15h, the NB PMU is completely -distinct and thus must be implemented in a separate -table. - -Furthermore, the NB perf_event support is also independent -from core PMU and uses dynamic PMU registration. This patch -handles this correctly too. +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index bf28291..0ed9441 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -119,6 +119,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &intel_snbep_unc_r3qpi0_support, + &intel_snbep_unc_r3qpi1_support, + &intel_knc_support, ++ &intel_slm_support, + &intel_x86_arch_support, /* must always be last for x86 */ + #endif + +@@ -826,6 +827,7 @@ pfmlib_parse_event_attr(char *str, pfmlib_event_desc_t *d) + goto found_attr; + } + } ++ DPRINT("cannot find attribute %s\n", s); + return PFM_ERR_ATTR; + found_attr: + type = ainfo->type; +diff --git a/lib/pfmlib_intel_slm.c b/lib/pfmlib_intel_slm.c +new file mode 100644 +index 0000000..ba61450 +--- /dev/null ++++ b/lib/pfmlib_intel_slm.c +@@ -0,0 +1,89 @@ ++/* ++ * pfmlib_intel_slm.c : Intel Silvermont core PMU ++ * ++ * Copyright (c) 2013 Google, Inc ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Based on Intel Software Optimization Guide June 2013 ++ */ ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "events/intel_slm_events.h" ++ ++static int ++pfm_intel_slm_detect(void *this) ++{ ++ int ret; ++ ++ ret = pfm_intel_x86_detect(); ++ if (ret != PFM_SUCCESS) ++ return ret; ++ if (pfm_intel_x86_cfg.family != 6) ++ return PFM_ERR_NOTSUPP; ++ ++ switch(pfm_intel_x86_cfg.model) { ++ case 55: /* Silvermont */ ++ case 77: /* Silvermont Avoton */ ++ break; ++ default: ++ return PFM_ERR_NOTSUPP; ++ } ++ return PFM_SUCCESS; ++} ++ ++static int ++pfm_intel_slm_init(void *this) ++{ ++ pfm_intel_x86_cfg.arch_version = 2; ++ return PFM_SUCCESS; ++} ++ ++pfmlib_pmu_t intel_slm_support={ ++ .desc = "Intel Silvermont", ++ .name = "slm", ++ .pmu = PFM_PMU_INTEL_SLM, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_slm_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .num_cntrs = 4, ++ .num_fixed_cntrs = 3, ++ .max_encoding = 2, ++ .pe = intel_slm_pe, ++ .atdesc = intel_x86_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK ++ | INTEL_X86_PMU_FL_ECMASK, ++ .supported_plm = INTEL_X86_PLM, ++ ++ .pmu_detect = pfm_intel_slm_detect, ++ .pmu_init = pfm_intel_slm_init, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), ++ ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_intel_x86.c b/lib/pfmlib_intel_x86.c +index 34c843d..baa9f63 100644 +--- a/lib/pfmlib_intel_x86.c ++++ b/lib/pfmlib_intel_x86.c +@@ -599,6 +599,7 @@ pfm_intel_x86_encode_gen(void *this, pfmlib_event_desc_t *e) + + e->codes[0] = reg.val; + ++DPRINT("sel_edge=%d cnt=%d\n", reg.sel_edge, reg.sel_cnt_mask); + /* + * on recent processors (except Atom), edge requires cmask >=1 + */ +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 59e4235..75a2d30 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -262,6 +262,7 @@ extern pfmlib_pmu_t intel_snbep_unc_r2pcie_support; + extern pfmlib_pmu_t intel_snbep_unc_r3qpi0_support; + extern pfmlib_pmu_t intel_snbep_unc_r3qpi1_support; + extern pfmlib_pmu_t intel_knc_support; ++extern pfmlib_pmu_t intel_slm_support; + extern pfmlib_pmu_t power4_support; + extern pfmlib_pmu_t ppc970_support; + extern pfmlib_pmu_t ppc970mp_support; +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 6690a96..cb781b9 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -2092,6 +2092,95 @@ static const test_event_t x86_test_events[]={ + .name = "rapl::rapl_energy_cores:u", + .ret = PFM_ERR_ATTR, + }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_0:snp_hitm", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1]=0x100001ffffull, ++ .fstr = "slm::OFFCORE_RESPONSE_0:ANY_REQUEST:ANY_RESPONSE:SNP_HITM:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_0:any_data", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1]=0x12011, ++ .fstr = "slm::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_L2_DATA_RD:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_0:uc_ifetch", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1]=0x10200, ++ .fstr = "slm::OFFCORE_RESPONSE_0:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_0:any_ifetch", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1]=0x10244, ++ .fstr = "slm::OFFCORE_RESPONSE_0:DMND_IFETCH:PF_IFETCH:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_1:snp_hitm", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5302b7, ++ .codes[1]=0x100001ffffull, ++ .fstr = "slm::OFFCORE_RESPONSE_1:ANY_REQUEST:ANY_RESPONSE:SNP_HITM:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_1:any_data", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5302b7, ++ .codes[1]=0x12011, ++ .fstr = "slm::OFFCORE_RESPONSE_1:DMND_DATA_RD:PF_L2_DATA_RD:PF_L1_DATA_RD:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_1:uc_ifetch", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5302b7, ++ .codes[1]=0x10200, ++ .fstr = "slm::OFFCORE_RESPONSE_1:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::offcore_response_1:any_ifetch", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5302b7, ++ .codes[1]=0x10244, ++ .fstr = "slm::OFFCORE_RESPONSE_1:DMND_IFETCH:PF_IFETCH:UC_IFETCH:ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::decode_restriction:predecode_wrong", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x5301e9, ++ .fstr = "slm::DECODE_RESTRICTION:PREDECODE_WRONG:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::rs_full_stall:fpc_port0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x5308cb, ++ .fstr = "slm::RS_FULL_STALL:FPC_PORT0:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::no_alloc_cycles:any", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x533fca, ++ .fstr = "slm::NO_ALLOC_CYCLES:ANY:k=1:u=1:e=0:i=0:c=0", ++ }, ++ { SRC_LINE, ++ .name = "slm::no_alloc_cycles:any:t=1", ++ .ret = PFM_ERR_ATTR ++ }, + }; + #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) + -The test suite is updated to take those changes into consideration. +commit 93f4b19b49ee849cd3f822e87be12238305c40ba +Author: Stephane Eranian +Date: Sun Dec 1 10:27:53 2013 +0100 -Signed-off-by: Stephane Eranian ---- - lib/events/amd64_events_fam15h.h | 224 ---- - lib/events/amd64_events_fam15h_nb.h | 2022 +++++++++++++++++++++++++++++++++++ - 2 files changed, 2022 insertions(+), 224 deletions(-) - create mode 100644 lib/events/amd64_events_fam15h_nb.h + add AMD Fam15h Norhtbridge PMU support + + This patch adds proper support for AMD Fam15h uncore PMU + (Northbridge). + + The Northbridge (NB) events were in the core PMU event + list before. But on Fam15h, the NB PMU is completely + distinct and thus must be implemented in a separate + table. + + Furthermore, the NB perf_event support is also independent + from core PMU and uses dynamic PMU registration. This patch + handles this correctly too. + + The test suite is updated to take those changes into consideration. + + Signed-off-by: Stephane Eranian +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index b89e661..ac9ed03 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -194,6 +194,7 @@ typedef enum { + PFM_PMU_INTEL_RAPL, /* Intel RAPL */ + + PFM_PMU_INTEL_SLM, /* Intel Silvermont */ ++ PFM_PMU_AMD64_FAM15H_NB, /* AMD AMD64 Fam15h NorthBridge */ + + /* MUST ADD NEW PMU MODELS HERE */ + diff --git a/lib/events/amd64_events_fam15h.h b/lib/events/amd64_events_fam15h.h index ac2b111..7872468 100644 --- a/lib/events/amd64_events_fam15h.h @@ -3934,25 +5668,629 @@ index 0000000..5969eb6 + .umasks = amd64_fam15h_nb_l3_latency, +}, +}; --- -1.8.3.1 - -From ec046652845877d46cc8c62d86f47325380fbaa1 Mon Sep 17 00:00:00 2001 -From: Andreas Beckmann -Date: Thu, 12 Dec 2013 22:46:19 +0100 -Subject: [PATCH 12/14] fix typos in IVB event descriptions - -Signed-off-by: Andreas Beckmann ---- - lib/events/intel_ivb_events.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/lib/events/intel_ivb_events.h b/lib/events/intel_ivb_events.h -index 3c5583e..407059b 100644 ---- a/lib/events/intel_ivb_events.h -+++ b/lib/events/intel_ivb_events.h -@@ -1173,7 +1173,7 @@ static const intel_x86_umask_t ivb_other_assists[]={ - .uflags= INTEL_X86_NCOMBO, +diff --git a/lib/pfmlib_amd64_fam15h.c b/lib/pfmlib_amd64_fam15h.c +index 9170868..b752d87 100644 +--- a/lib/pfmlib_amd64_fam15h.c ++++ b/lib/pfmlib_amd64_fam15h.c +@@ -27,43 +27,72 @@ + #include "pfmlib_priv.h" + #include "pfmlib_amd64_priv.h" + #include "events/amd64_events_fam15h.h" ++#include "events/amd64_events_fam15h_nb.h" + +-#define DEFINE_FAM15H_REV(d, n, r, pmuid) \ +-static int \ +-pfm_amd64_fam15h_##n##_detect(void *this) \ +-{ \ +- int ret; \ +- ret = pfm_amd64_detect(this); \ +- if (ret != PFM_SUCCESS) \ +- return ret; \ +- ret = pfm_amd64_cfg.revision; \ +- return ret == pmuid ? PFM_SUCCESS : PFM_ERR_NOTSUPP; \ +-} \ +-pfmlib_pmu_t amd64_fam15h_##n##_support={ \ +- .desc = "AMD64 Fam15h "#d, \ +- .name = "amd64_fam15h_"#n, \ +- .pmu = pmuid, \ +- .pmu_rev = r, \ +- .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam15h_pe),\ +- .type = PFM_PMU_TYPE_CORE, \ +- .supported_plm = AMD64_FAM10H_PLM, \ +- .num_cntrs = 6, \ +- .max_encoding = 1, \ +- .pe = amd64_fam15h_pe, \ +- .atdesc = amd64_mods, \ +- .flags = PFMLIB_PMU_FL_RAW_UMASK, \ +- \ +- .pmu_detect = pfm_amd64_fam15h_##n##_detect,\ +- .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,\ +- PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), \ +- .get_event_first = pfm_amd64_get_event_first, \ +- .get_event_next = pfm_amd64_get_event_next, \ +- .event_is_valid = pfm_amd64_event_is_valid, \ +- .validate_table = pfm_amd64_validate_table, \ +- .get_event_info = pfm_amd64_get_event_info, \ +- .get_event_attr_info = pfm_amd64_get_event_attr_info,\ +- PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),\ +- .get_event_nattrs = pfm_amd64_get_event_nattrs, \ ++static int ++pfm_amd64_fam15h_detect(void *this) ++{ ++ int ret; ++ ++ ret = pfm_amd64_detect(this); ++ if (ret != PFM_SUCCESS) ++ return ret; ++ ++ if (pfm_amd64_cfg.revision == PFM_PMU_AMD64_FAM15H_INTERLAGOS) ++ return PFM_SUCCESS; ++ ++ return PFM_ERR_NOTSUPP; + } + +-DEFINE_FAM15H_REV(Interlagos, interlagos, 0, PFM_PMU_AMD64_FAM15H_INTERLAGOS); ++pfmlib_pmu_t amd64_fam15h_interlagos_support={ ++ .desc = "AMD64 Fam15h Interlagos", ++ .name = "amd64_fam15h_interlagos", ++ .pmu = PFM_PMU_AMD64_FAM15H_INTERLAGOS, ++ .pmu_rev = 0, ++ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam15h_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .supported_plm = AMD64_FAM10H_PLM, ++ .num_cntrs = 6, ++ .max_encoding = 1, ++ .pe = amd64_fam15h_pe, ++ .atdesc = amd64_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_amd64_fam15h_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), ++ .get_event_first = pfm_amd64_get_event_first, ++ .get_event_next = pfm_amd64_get_event_next, ++ .event_is_valid = pfm_amd64_event_is_valid, ++ .validate_table = pfm_amd64_validate_table, ++ .get_event_info = pfm_amd64_get_event_info, ++ .get_event_attr_info = pfm_amd64_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs), ++ .get_event_nattrs = pfm_amd64_get_event_nattrs, ++}; ++ ++pfmlib_pmu_t amd64_fam15h_nb_support={ ++ .desc = "AMD64 Fam15h NorthBridge", ++ .name = "amd64_fam15h_nb", ++ .pmu = PFM_PMU_AMD64_FAM15H_NB, ++ .perf_name = "amd_nb", ++ .pmu_rev = 0, ++ .pme_count = LIBPFM_ARRAY_SIZE(amd64_fam15h_nb_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .supported_plm = 0, /* no plm support */ ++ .num_cntrs = 4, ++ .max_encoding = 1, ++ .pe = amd64_fam15h_nb_pe, ++ .atdesc = amd64_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_amd64_fam15h_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding), ++ .get_event_first = pfm_amd64_get_event_first, ++ .get_event_next = pfm_amd64_get_event_next, ++ .event_is_valid = pfm_amd64_event_is_valid, ++ .validate_table = pfm_amd64_validate_table, ++ .get_event_info = pfm_amd64_get_event_info, ++ .get_event_attr_info = pfm_amd64_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_amd64_nb_perf_validate_pattrs), ++ .get_event_nattrs = pfm_amd64_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_amd64_perf_event.c b/lib/pfmlib_amd64_perf_event.c +index 68cf2b9..e210328 100644 +--- a/lib/pfmlib_amd64_perf_event.c ++++ b/lib/pfmlib_amd64_perf_event.c +@@ -24,12 +24,38 @@ + #include + #include + #include ++#include + + /* private headers */ + #include "pfmlib_priv.h" /* library private */ + #include "pfmlib_amd64_priv.h" /* architecture private */ + #include "pfmlib_perf_event_priv.h" + ++static int ++find_pmu_type_by_name(const char *name) ++{ ++ char filename[PATH_MAX]; ++ FILE *fp; ++ int ret, type; ++ ++ if (!name) ++ return PFM_ERR_NOTSUPP; ++ ++ sprintf(filename, "/sys/bus/event_source/devices/%s/type", name); ++ ++ fp = fopen(filename, "r"); ++ if (!fp) ++ return PFM_ERR_NOTSUPP; ++ ++ ret = fscanf(fp, "%d", &type); ++ if (ret != 1) ++ type = PFM_ERR_NOTSUPP; ++ ++ fclose(fp); ++ ++ return type; ++} ++ + int + pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e) + { +@@ -52,8 +78,20 @@ pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e) + return PFM_ERR_NOTSUPP; + } + +- /* all events treated as raw for now */ +- attr->type = PERF_TYPE_RAW; ++ ret = PERF_TYPE_RAW; ++ ++ /* ++ * if specific perf PMU is provided then try to locate it ++ * otherwise assume core PMU and thus type RAW ++ */ ++ if (pmu->perf_name) { ++ /* greab PMU type from sysfs */ ++ ret = find_pmu_type_by_name(pmu->perf_name); ++ if (ret < 0) ++ return ret; ++ } ++ DPRINT("amd64_get_perf_encoding: PMU type=%d\n", ret); ++ attr->type = ret; + attr->config = e->codes[0]; + + return PFM_SUCCESS; +@@ -80,8 +118,8 @@ pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PMU) { + + if (e->pattrs[i].idx == AMD64_ATTR_U +- || e->pattrs[i].idx == AMD64_ATTR_K +- || e->pattrs[i].idx == AMD64_ATTR_H) ++ || e->pattrs[i].idx == AMD64_ATTR_K ++ || e->pattrs[i].idx == AMD64_ATTR_H) + compact = 1; + } + +@@ -102,3 +140,30 @@ pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) + } + } + } ++ ++void ++pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) ++{ ++ int i, compact; ++ ++ for (i=0; i < e->npattrs; i++) { ++ compact = 0; ++ ++ /* umasks never conflict */ ++ if (e->pattrs[i].type == PFM_ATTR_UMASK) ++ continue; ++ ++ /* ++ * no perf_events attr is supported by AMD64 Northbridge PMU ++ * sampling is not supported ++ */ ++ if (e->pattrs[i].ctrl == PFM_ATTR_CTRL_PERF_EVENT) { ++ compact = 1; ++ } ++ ++ if (compact) { ++ pfmlib_compact_pattrs(e, i); ++ i--; ++ } ++ } ++} +diff --git a/lib/pfmlib_amd64_priv.h b/lib/pfmlib_amd64_priv.h +index e940758..14c9526 100644 +--- a/lib/pfmlib_amd64_priv.h ++++ b/lib/pfmlib_amd64_priv.h +@@ -212,4 +212,5 @@ extern int pfm_amd64_get_num_events(void *this); + + extern int pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e); + extern void pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); ++extern void pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); + #endif /* __PFMLIB_AMD64_PRIV_H__ */ +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index 0ed9441..4f4092f 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -76,6 +76,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &amd64_fam12h_llano_support, + &amd64_fam14h_bobcat_support, + &amd64_fam15h_interlagos_support, ++ &amd64_fam15h_nb_support, + &intel_core_support, + &intel_atom_support, + &intel_nhm_support, +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 75a2d30..0b46a86 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -213,6 +213,7 @@ extern pfmlib_pmu_t amd64_fam11h_turion_support; + extern pfmlib_pmu_t amd64_fam12h_llano_support; + extern pfmlib_pmu_t amd64_fam14h_bobcat_support; + extern pfmlib_pmu_t amd64_fam15h_interlagos_support; ++extern pfmlib_pmu_t amd64_fam15h_nb_support; + extern pfmlib_pmu_t intel_p6_support; + extern pfmlib_pmu_t intel_ppro_support; + extern pfmlib_pmu_t intel_pii_support; +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index cb781b9..8dc222b 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1879,31 +1879,35 @@ static const test_event_t x86_test_events[]={ + }, + { SRC_LINE, + .name = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT", ++ .ret = PFM_ERR_NOTFOUND, /* event in Northbridge PMU */ ++ }, ++ { SRC_LINE, ++ .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x5308f6, +- .fstr = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT:SUBLINK_0", ++ .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:NOP_DW_SENT:SUBLINK_0", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL", ++ .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x533ff6, +- .fstr = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_0", ++ .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_0", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", ++ .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x53bff6, +- .fstr = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", ++ .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:ALL:SUBLINK_1", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT", ++ .name = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x5303f6, +- .fstr = "amd64_fam15h_interlagos::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT:SUBLINK_0", ++ .fstr = "amd64_fam15h_nb::LINK_TRANSMIT_BANDWIDTH_LINK_0:COMMAND_DW_SENT:DATA_DW_SENT:SUBLINK_0", + }, + { SRC_LINE, + .name = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0x4ff:u", +@@ -1917,40 +1921,40 @@ static const test_event_t x86_test_events[]={ + .fstr = "amd64_fam15h_interlagos::DISPATCHED_FPU_OPS:0xff:k=0:u=1:e=0:i=0:c=0:h=0:g=0" + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_modify:core_3", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_modify:core_3", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x4005334e0ull, +- .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_MODIFY:CORE_3", ++ .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_MODIFY:CORE_3", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x40053f7e0ull, +- .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_ANY:ANY_CORE", ++ .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_ANY:ANY_CORE", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:PREFETCH:READ_BLOCK_MODIFY:core_4", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:PREFETCH:READ_BLOCK_MODIFY:core_4", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x400534de0ull, +- .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:READ_BLOCK_MODIFY:PREFETCH:CORE_4", ++ .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:READ_BLOCK_EXCLUSIVE:READ_BLOCK_MODIFY:PREFETCH:CORE_4", + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1", + .ret = PFM_ERR_FEATCOMB, /* must use individual umasks to combine with prefetch */ + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1:core_3", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:read_block_any:prefetch:core_1:core_3", + .ret = PFM_ERR_FEATCOMB, /* core umasks cannot be combined */ + }, + { SRC_LINE, +- .name = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:prefetch:core_0", ++ .name = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:prefetch:core_0", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x4005308e0ull, +- .fstr = "amd64_fam15h_interlagos::READ_REQUEST_TO_L3_CACHE:PREFETCH:CORE_0", ++ .fstr = "amd64_fam15h_nb::READ_REQUEST_TO_L3_CACHE:PREFETCH:CORE_0", + }, + { SRC_LINE, + .name = "ivb_ep::mem_load_uops_llc_miss_retired:local_dram", + +commit 9007b7acf1aa3d8b6bd344c14f6cf6c566170842 +Author: Stephane Eranian +Date: Sun Dec 1 10:42:24 2013 +0100 + + Add man page for AMD64 Fam15h core and uncore PMU + + Man page was missing. + + Signed-off-by: Stephane Eranian + +diff --git a/README b/README +index 8aa8086..a765cb4 100644 +--- a/README ++++ b/README +@@ -37,7 +37,7 @@ The library supports many PMUs. The current version can handle: + AMD64 Fam11h (Turion) + AMD64 Fam12h (Llano) + AMD64 Fam14h (Bobcat) +- AMD64 Fam15h (Bulldozer) ++ AMD64 Fam15h (Bulldozer) (core and uncore) + + - For Intel X86: + Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M) +diff --git a/docs/Makefile b/docs/Makefile +index 8f28726..f24999f 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -36,6 +36,7 @@ ARCH_MAN=libpfm_intel_core.3 \ + libpfm_amd64_k7.3 \ + libpfm_amd64_k8.3 \ + libpfm_amd64_fam10h.3 \ ++ libpfm_amd64_fam15h.3 \ + libpfm_intel_atom.3 \ + libpfm_intel_nhm.3 \ + libpfm_intel_nhm_unc.3 \ +diff --git a/docs/man3/libpfm_amd64_fam15h.3 b/docs/man3/libpfm_amd64_fam15h.3 +new file mode 100644 +index 0000000..84ae455 +--- /dev/null ++++ b/docs/man3/libpfm_amd64_fam15h.3 +@@ -0,0 +1,55 @@ ++.TH LIBPFM 3 "Nov, 2013" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_amd64_fam15h - support for AMD64 Family 15h processors ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: amd64_fam15h_interlagos ++.B PMU desc: AMD64 Fam15h Interlagos ++.B PMU name: amd64_fam15h_nb ++.B PMU desc: AMD64 Fam15h Northbridge ++.sp ++.SH DESCRIPTION ++The library supports AMD Family 15h processors core PMU in both 32 and 64-bit modes. The ++uncore PMU (Northbridge) is also supported as a separate PMU model. ++ ++.SH MODIFIERS ++The following modifiers are supported on AMD64 Family 15h core PMU: ++.TP ++.B u ++Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B h ++Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR. ++This modifier is available starting with Fam10h. This is a boolean modifier. ++.TP ++.B g ++Measure at while executing in guest mode (when using virtualization). This modifier is available ++starting with Fam10h. This is a boolean modifier. ++.TP ++.B i ++Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR ++occurring. This is a boolean modifier ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier. ++.TP ++.B c ++Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles ++in which the number of occurrences of the event is greater or equal to the threshold. This is an integer ++modifier with values in the range [0:255]. ++.TP ++The uncore (NorthBridge) PMU \fBdoes not support\fR any modifiers. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++Robert Richter ++.if ++.PP + +commit b81ff2dc94f7e9acee2c4ba306d13e343cce4a18 +Author: Stephane Eranian +Date: Sun Dec 1 17:12:49 2013 +0100 + + fix compiler warning on pfm_intel_rapl_get_encoding() + + Avoid clang warning + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_rapl.c b/lib/pfmlib_intel_rapl.c +index 25c51f6..4570d65 100644 +--- a/lib/pfmlib_intel_rapl.c ++++ b/lib/pfmlib_intel_rapl.c +@@ -96,12 +96,8 @@ static int + pfm_intel_rapl_get_encoding(void *this, pfmlib_event_desc_t *e) + + { +- pfmlib_pmu_t *pmu = this; + const intel_x86_entry_t *pe; + +- /* shut up the compiler */ +- pmu = pmu; +- + pe = this_pe(this); + + e->fstr[0] = '\0'; + +commit b35f8115e173f4c1cf5d58b6e6b62f0ad91cb2dd +Author: Stephane Eranian +Date: Tue Dec 3 06:48:24 2013 +0100 + + Add missing Intel Silvermont libpfm4 man page. + + Adds the man pag for Intel Silvermont core PMU. + + Reported-by: Steve Kaufman + Signed-off-by: Stephane Eranian + +diff --git a/docs/man3/libpfm_intel_slm.3 b/docs/man3/libpfm_intel_slm.3 +new file mode 100644 +index 0000000..1e1153f +--- /dev/null ++++ b/docs/man3/libpfm_intel_slm.3 +@@ -0,0 +1,84 @@ ++.TH LIBPFM 3 "November, 2013" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_slm - support for Intel Silvermont core PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: slm ++.B PMU desc: Intel Silvermont ++.sp ++.SH DESCRIPTION ++The library supports the Intel Silvermont core PMU. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Silvermont processors: ++.TP ++.B u ++Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B i ++Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR ++occurring. This is a boolean modifier ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event ++to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one. ++This is a boolean modifier. ++.TP ++.B c ++Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles ++in which the number of occurrences of the event is greater or equal to the threshold. This is an integer ++modifier with values in the range [0:255]. ++ ++.SH OFFCORE_RESPONSE events ++Intel Silvermont provides two offcore_response events: ++\fBOFFCORE_RESPONSE_0\fR and \fBOFFCORE_RESPONSE_1\fR. ++ ++Those events need special treatment in the performance monitoring infrastructure ++because each event uses an extra register to store some settings. Thus, in ++case multiple offcore_response events are monitored simultaneously, the kernel needs ++to manage the sharing of that extra register. ++ ++The offcore_response events are exposed as a normal event by the library. The extra ++settings are exposed as regular umasks. The library takes care of encoding the ++events according to the underlying kernel interface. ++ ++On Intel Silvermont, the umasks are divided into three categories: request, supplier ++and snoop. The user must provide at least one umask for each category. The categories ++are shown in the umask descriptions. The library provides a default umask per category ++if not provided by the user. ++ ++There is also the special response umask called \fBANY_RESPONSE\fR. When this umask ++is used then it overrides any supplier and snoop umasks. In other words, users can ++specify either \fBANY_RESPONSE\fR \fBOR\fR any combinations of supplier + snoops. ++ ++In case no supplier or snoop is specified, the library defaults to using ++\fBANY_RESPONSE\fR. ++ ++For instance, the following are valid event selections: ++.TP ++.B OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE ++.TP ++.B OFFCORE_RESPONSE_0:ANY_REQUEST ++.TP ++.B OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY ++ ++.P ++But the following are illegal: ++ ++.TP ++.B OFFCORE_RESPONSE_0:ANY_RFO:NON_DRAM:ANY_RESPONSE ++.TP ++.B OFFCORE_RESPONSE_0:ANY_RFO:L2_HIT:SNOOP_ANY:ANY_RESPONSE ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP + +commit 4b0a11762f62f7763be31ade2d70ff0ae5f80fd4 +Author: Vince Weaver +Date: Fri Dec 6 10:17:18 2013 -0500 + + add missing Intel Haswell model numbers + + This patch adds support for a few more Haswell + models: 63, 69, 70, 71. + + Signed-off-by: Vince Weaver + +diff --git a/lib/pfmlib_intel_hsw.c b/lib/pfmlib_intel_hsw.c +index 7d01ff1..f4975f6 100644 +--- a/lib/pfmlib_intel_hsw.c ++++ b/lib/pfmlib_intel_hsw.c +@@ -40,6 +40,10 @@ pfm_hsw_detect(void *this) + + switch (pfm_intel_x86_cfg.model) { + case 60: /* Haswell */ ++ case 63: /* Haswell */ ++ case 69: /* Haswell */ ++ case 70: /* Haswell */ ++ case 71: /* Haswell */ + break; + default: + return PFM_ERR_NOTSUPP; + +commit ec046652845877d46cc8c62d86f47325380fbaa1 +Author: Andreas Beckmann +Date: Thu Dec 12 22:46:19 2013 +0100 + + fix typos in IVB event descriptions + + Signed-off-by: Andreas Beckmann + +diff --git a/lib/events/intel_ivb_events.h b/lib/events/intel_ivb_events.h +index 3c5583e..407059b 100644 +--- a/lib/events/intel_ivb_events.h ++++ b/lib/events/intel_ivb_events.h +@@ -1173,7 +1173,7 @@ static const intel_x86_umask_t ivb_other_assists[]={ + .uflags= INTEL_X86_NCOMBO, }, { .uname = "AVX_STORE", - .udesc = "Number of assists associated with 25-bit AVX stores", @@ -3969,48 +6307,16 @@ index 3c5583e..407059b 100644 .ucode = 0x3000, .uflags= INTEL_X86_NCOMBO, }, --- -1.8.3.1 - -From a2eb1c8257b07ebc2f5e7a1ace8d005d0a7a08f0 Mon Sep 17 00:00:00 2001 -From: Steve Kaufmann -Date: Mon, 13 Jan 2014 14:19:16 +0100 -Subject: [PATCH 13/14] fix spelling mistakes in event descriptions - -Applied spell-checker on event descriptions. - -Signed-off-by: Steve Kaufmann ---- - lib/events/amd64_events_fam14h.h | 4 ++-- - lib/events/amd64_events_fam15h.h | 2 +- - lib/events/amd64_events_fam15h_nb.h | 2 +- - lib/events/arm_1176_events.h | 2 +- - lib/events/arm_cortex_a8_events.h | 4 ++-- - lib/events/arm_cortex_a9_events.h | 2 +- - lib/events/intel_atom_events.h | 2 +- - lib/events/intel_coreduo_events.h | 6 +++--- - lib/events/intel_hsw_events.h | 10 +++++----- - lib/events/intel_ivb_events.h | 10 +++++----- - lib/events/intel_netburst_events.h | 4 ++-- - lib/events/intel_nhm_events.h | 12 ++++++------ - lib/events/intel_nhm_unc_events.h | 8 ++++---- - lib/events/intel_p6_events.h | 4 ++-- - lib/events/intel_pii_events.h | 4 ++-- - lib/events/intel_pm_events.h | 4 ++-- - lib/events/intel_ppro_events.h | 4 ++-- - lib/events/intel_slm_events.h | 8 ++++---- - lib/events/intel_snb_events.h | 14 +++++++------- - lib/events/intel_snbep_events.h | 14 +++++++------- - lib/events/intel_snbep_unc_cbo_events.h | 4 ++-- - lib/events/intel_wsm_events.h | 4 ++-- - lib/events/intel_wsm_unc_events.h | 10 +++++----- - lib/events/intel_x86_arch_events.h | 2 +- - lib/events/mips_74k_events.h | 6 +++--- - lib/events/sparc_ultra3_events.h | 8 ++++---- - lib/events/sparc_ultra3i_events.h | 10 +++++----- - lib/events/sparc_ultra3plus_events.h | 10 +++++----- - lib/events/sparc_ultra4plus_events.h | 12 ++++++------ - 29 files changed, 93 insertions(+), 93 deletions(-) + +commit a2eb1c8257b07ebc2f5e7a1ace8d005d0a7a08f0 +Author: Steve Kaufmann +Date: Mon Jan 13 14:19:16 2014 +0100 + + fix spelling mistakes in event descriptions + + Applied spell-checker on event descriptions. + + Signed-off-by: Steve Kaufmann diff --git a/lib/events/amd64_events_fam14h.h b/lib/events/amd64_events_fam14h.h index e975521..0cf11a9 100644 @@ -4926,18 +7232,14 @@ index 47512da..ca473a4 100644 .ctrl = PME_CTRL_S1, .code = 0x31, }, --- -1.8.3.1 -From e799ae1bafabe88d7a63787edd42953850cba676 Mon Sep 17 00:00:00 2001 -From: Steve Kaufmann -Date: Mon, 13 Jan 2014 14:21:09 +0100 -Subject: [PATCH 14/14] fix PMU name description typo in comment +commit e799ae1bafabe88d7a63787edd42953850cba676 +Author: Steve Kaufmann +Date: Mon Jan 13 14:21:09 2014 +0100 -Signed-off-by: Steve Kaufmann ---- - lib/events/intel_snbep_events.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + fix PMU name description typo in comment + + Signed-off-by: Steve Kaufmann diff --git a/lib/events/intel_snbep_events.h b/lib/events/intel_snbep_events.h index 17b51c6..a9d88f5 100644 @@ -4952,6 +7254,9954 @@ index 17b51c6..a9d88f5 100644 */ static const intel_x86_umask_t snbep_agu_bypass_cancel[]={ --- -1.8.3.1 +commit bca43a50f9249df79db82e149de2a8d846eb6d45 +Author: Stephane Eranian +Date: Mon Jan 13 16:21:44 2014 +0100 + + add support for RAPL GPU energy counter + + This patch adds a new RAPL event to measure + builtin GPU energy consumption on Intel SNB/IVB/HSW + client processors. + + Requires a kernel with RAPL support in perf_events + such as Linux v3.13 or later. + + New event: rapl::rapl_energy_gpu + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_rapl.c b/lib/pfmlib_intel_rapl.c +index 4570d65..1215731 100644 +--- a/lib/pfmlib_intel_rapl.c ++++ b/lib/pfmlib_intel_rapl.c +@@ -51,7 +51,12 @@ extern pfmlib_pmu_t intel_rapl_support; + } + + static const intel_x86_entry_t intel_rapl_cln_pe[]={ +- RAPL_COMMON_EVENTS ++ RAPL_COMMON_EVENTS, ++ { .name = "RAPL_ENERGY_GPU", ++ .desc = "Number of Joules consumed by the builtin GPU. Unit is 2^-32 Joules", ++ .cntmsk = 0x8, ++ .code = 0x4, ++ } + }; + + static const intel_x86_entry_t intel_rapl_srv_pe[]={ + +commit 137067de9afc9c5bbb17d0057756c106f7898029 +Author: Stephane Eranian +Date: Thu Feb 6 12:08:18 2014 +0100 + + add INTEL_X86_GRP_DFL_NONE umask flag + + When this flag is set for a umask, it means the umask group + (grpid) does not require at least one umask to be set. In + other words, umasks in the group need to be separated + from the others, but it is okay if none is specified. Normally, + at least one umask per group is required. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_snbep_unc.c b/lib/pfmlib_intel_snbep_unc.c +index 9813e1c..7233e77 100644 +--- a/lib/pfmlib_intel_snbep_unc.c ++++ b/lib/pfmlib_intel_snbep_unc.c +@@ -149,9 +149,19 @@ snbep_unc_add_defaults(void *this, pfmlib_event_desc_t *e, + continue; + } + ++ if (intel_x86_uflag(this, e->event, idx, INTEL_X86_GRP_DFL_NONE)) { ++ skip = 1; ++ continue; ++ } ++ + /* umask is default for group */ + if (intel_x86_uflag(this, e->event, idx, INTEL_X86_DFL)) { +- DPRINT("added default %s for group %d j=%d idx=%d\n", ent->umasks[idx].uname, i, j, idx); ++ DPRINT("added default %s for group %d j=%d idx=%d ucode=0x%"PRIx64"\n", ++ ent->umasks[idx].uname, ++ i, ++ j, ++ idx, ++ ent->umasks[idx].ucode); + /* + * default could be an alias, but + * ucode must reflect actual code +@@ -181,7 +191,7 @@ snbep_unc_add_defaults(void *this, pfmlib_event_desc_t *e, + return PFM_ERR_UMASK; + } + } +- DPRINT("max_grpid=%d nattrs=%d k=%d\n", max_grpid, e->nattrs, k); ++ DPRINT("max_grpid=%d nattrs=%d k=%d umask=0x%"PRIx64"\n", max_grpid, e->nattrs, k, *umask); + done: + e->nattrs = k; + return PFM_SUCCESS; +diff --git a/lib/pfmlib_intel_x86.c b/lib/pfmlib_intel_x86.c +index baa9f63..cfa1730 100644 +--- a/lib/pfmlib_intel_x86.c ++++ b/lib/pfmlib_intel_x86.c +@@ -215,9 +215,19 @@ pfm_intel_x86_add_defaults(void *this, pfmlib_event_desc_t *e, + continue; + } + ++ if (intel_x86_uflag(this, e->event, idx, INTEL_X86_GRP_DFL_NONE)) { ++ skip = 1; ++ continue; ++ } ++ + /* umask is default for group */ + if (intel_x86_uflag(this, e->event, idx, INTEL_X86_DFL)) { +- DPRINT("added default %s for group %d j=%d idx=%d\n", ent->umasks[idx].uname, i, j, idx); ++ DPRINT("added default %s for group %d j=%d idx=%d ucode=0x%"PRIx64"\n", ++ ent->umasks[idx].uname, ++ i, ++ j, ++ idx, ++ ent->umasks[idx].ucode); + /* + * default could be an alias, but + * ucode must reflect actual code +@@ -246,7 +256,7 @@ pfm_intel_x86_add_defaults(void *this, pfmlib_event_desc_t *e, + return PFM_ERR_UMASK; + } + } +- DPRINT("max_grpid=%d nattrs=%d k=%d\n", max_grpid, e->nattrs, k); ++ DPRINT("max_grpid=%d nattrs=%d k=%d umask=0x%"PRIx64"\n", max_grpid, e->nattrs, k, *umask); + done: + e->nattrs = k; + return PFM_SUCCESS; +diff --git a/lib/pfmlib_intel_x86_priv.h b/lib/pfmlib_intel_x86_priv.h +index 0f0c1f5..95a7565 100644 +--- a/lib/pfmlib_intel_x86_priv.h ++++ b/lib/pfmlib_intel_x86_priv.h +@@ -86,6 +86,7 @@ typedef struct { + #define INTEL_X86_NO_AUTOENCODE 0x100 /* does not support auto encoding validation */ + #define INTEL_X86_CODE_OVERRIDE 0x200 /* umask overrides event code */ + #define INTEL_X86_LDLAT 0x400 /* needs load latency modifier (ldlat) */ ++#define INTEL_X86_GRP_DFL_NONE 0x800 /* ok if umask group defaults to no umask */ + + typedef union pfm_intel_x86_reg { + unsigned long long val; /* complete register value */ + +commit 02e07d2585015d5c2eecdc47a35b07fdc21035cb +Author: Stephane Eranian +Date: Thu Feb 6 12:30:33 2014 +0100 + + fix SNBEP uncore default umask settings + + The routine snbep_unc_add_defaults() is already shifting the + raw umask code by 8, so do not shift it by 8 a second time in + the encoding routine, otherwise it will be zero. + + Also combine the default with what is already set for the + other umask groups. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_intel_snbep_unc.c b/lib/pfmlib_intel_snbep_unc.c +index 7233e77..7ca86ca 100644 +--- a/lib/pfmlib_intel_snbep_unc.c ++++ b/lib/pfmlib_intel_snbep_unc.c +@@ -424,8 +424,7 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + ret = snbep_unc_add_defaults(this, e, ugrpmsk, &um, &filter, max_grpid); + if (ret != PFM_SUCCESS) + return ret; +- um >>= 8; +- umask2 = um; ++ umask2 |= um; + } + + /* + +commit 4f070bd5a858c9ce57528018c50798d08811166b +Author: Stephane Eranian +Date: Thu Feb 6 12:32:15 2014 +0100 + + fix SNBEP-UNC CBOX UNC_C_LLC_LOOKUP umasks groups + + NID must qualify another umask. So put them in separate + groups. + + Make DATA_READS the default umask for first group. + + Update validation test suite accordingly. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_snbep_unc_cbo_events.h b/lib/events/intel_snbep_unc_cbo_events.h +index b2f0878..40d3e37 100644 +--- a/lib/events/intel_snbep_unc_cbo_events.h ++++ b/lib/events/intel_snbep_unc_cbo_events.h +@@ -165,7 +165,7 @@ static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ + { .uname = "DATA_READ", + .udesc = "Data read requests", + .grpid = 0, +- .uflags = INTEL_X86_NCOMBO, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + .ucode = 0x300, + }, + { .uname = "WRITE", +@@ -182,12 +182,12 @@ static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ + }, + { .uname = "NID", + .udesc = "Match a given RTID destination NID", +- .uflags = INTEL_X86_NCOMBO, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_GRP_DFL_NONE, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, +- .grpid = 0, ++ .grpid = 1, + .ucode = 0x4100, + }, +- CBO_FILT_MESIFS(1), ++ CBO_FILT_MESIFS(2), + }; + + static const intel_x86_umask_t snbep_unc_c_llc_victims[]={ +@@ -626,7 +626,7 @@ static const intel_x86_entry_t intel_snbep_unc_c_pe[]={ + .modmsk = SNBEP_UNC_CBO_NID_ATTRS, + .cntmsk = 0x3, + .code = 0x34, +- .ngrp = 2, ++ .ngrp = 3, + .flags = INTEL_X86_NO_AUTOENCODE, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_lookup), + .umasks = snbep_unc_c_llc_lookup, +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 8dc222b..d0a6666 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1269,17 +1269,17 @@ static const test_event_t x86_test_events[]={ + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", + .ret = PFM_SUCCESS, + .count = 2, +- .codes[0] = 0x4134, ++ .codes[0] = 0x4334, + .codes[1] = 0x7c0c00, +- .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_MESIF:e=0:i=0:t=0:tf=0:nf=3", ++ .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:NID:STATE_MESIF:e=0:i=0:t=0:tf=0:nf=3", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:nf=3", + .ret = PFM_SUCCESS, + .count = 2, +- .codes[0] = 0x4134, ++ .codes[0] = 0x4334, + .codes[1] = 0x200c00, +- .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:e=0:i=0:t=0:tf=0:nf=3", ++ .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:NID:STATE_M:e=0:i=0:t=0:tf=0:nf=3", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3:tid=1", + +commit 9b6576c74879450618ac8cb65342578401dbf937 +Author: Stephane Eranian +Date: Tue Feb 18 18:56:35 2014 +0100 + + add a match_event() pmu callback + + This patch adds the match_event() pmu + callback. This is an optional callback. + It can be used by PMU models to implement + specific event match algorithm. It operates + only on the event name, not the attributes. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index 861f475..b9d1d67 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -1026,10 +1026,17 @@ pfmlib_release_event(pfmlib_event_desc_t *e) + } + + static int ++match_event(void *this, pfmlib_event_desc_t *d, const char *e, const char *s) ++{ ++ return strcasecmp(e, s); ++} ++ ++static int + pfmlib_parse_equiv_event(const char *event, pfmlib_event_desc_t *d) + { + pfmlib_pmu_t *pmu = d->pmu; + pfm_event_info_t einfo; ++ int (*match)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); + char *str, *s, *p; + int i; + int ret; +@@ -1045,11 +1052,13 @@ pfmlib_parse_equiv_event(const char *event, pfmlib_event_desc_t *d) + if (p) + *p++ = '\0'; + ++ match = pmu->match_event ? pmu->match_event : match_event; ++ + pfmlib_for_each_pmu_event(pmu, i) { + ret = pmu->get_event_info(pmu, i, &einfo); + if (ret != PFM_SUCCESS) + goto error; +- if (!strcasecmp(einfo.name, s)) ++ if (!match(pmu, d, einfo.name, s)) + goto found; + } + free(str); +@@ -1085,6 +1094,7 @@ pfmlib_parse_event(const char *event, pfmlib_event_desc_t *d) + pfm_event_info_t einfo; + char *str, *s, *p; + pfmlib_pmu_t *pmu; ++ int (*match)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); + const char *pname = NULL; + int i, j, ret; + +@@ -1138,6 +1148,8 @@ pfmlib_parse_event(const char *event, pfmlib_event_desc_t *d) + */ + if (pname && !pfmlib_pmu_active(pmu) && !pfm_cfg.inactive) + continue; ++ ++ match = pmu->match_event ? pmu->match_event : match_event; + /* + * for each event + */ +@@ -1145,7 +1157,7 @@ pfmlib_parse_event(const char *event, pfmlib_event_desc_t *d) + ret = pmu->get_event_info(pmu, i, &einfo); + if (ret != PFM_SUCCESS) + goto error; +- if (!strcasecmp(einfo.name, s)) ++ if (!match(pmu, d, einfo.name, s)) + goto found; + } + } +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 287222d..aa7f819 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -132,8 +132,12 @@ typedef struct pfmlib_pmu { + void (*validate_pattrs[PFM_OS_MAX])(void *this, pfmlib_event_desc_t *e); + int (*os_detect[PFM_OS_MAX])(void *this); + int (*validate_table)(void *this, FILE *fp); +- int (*get_num_events)(void *this); /* optional */ +- void (*display_reg)(void *this, pfmlib_event_desc_t *e, void *val); /* optional */ ++ /* ++ * optional callbacks ++ */ ++ int (*get_num_events)(void *this); ++ void (*display_reg)(void *this, pfmlib_event_desc_t *e, void *val); ++ int (*match_event)(void *this, pfmlib_event_desc_t *d, const char *e, const char *s); + } pfmlib_pmu_t; + + typedef struct { +commit 13dab55b0c963a027dbe33c7434efe07433346f5 +Author: Stephane Eranian +Date: Tue Feb 18 17:33:22 2014 +0100 + + add perf_event RAW event syntax support + + This support is integrated via a pseudo PMU called + perf_raw. It provides no events, but instead just the + necessary callbacks to match evnet codes specified in + hex using the following syntax: rX. Where X is a 64-bit + hexadecimal value. It can be followed by the usual + attributes supported by perf_events: + + $ perf_examples/task -e r01c4:u,cycles foo + + This pseudo PMU is only available on Linux. + + Signed-off-by: Stephane Eranian + +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index 5434a96..76bca1b 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -197,6 +197,8 @@ typedef enum { + PFM_PMU_INTEL_SLM, /* Intel Silvermont */ + PFM_PMU_AMD64_FAM15H_NB, /* AMD AMD64 Fam15h NorthBridge */ + ++ PFM_PMU_PERF_EVENT_RAW, /* perf_events RAW event syntax */ ++ + /* MUST ADD NEW PMU MODELS HERE */ + + PFM_PMU_MAX /* end marker */ +diff --git a/lib/Makefile b/lib/Makefile +index 02dcfbb..e4530bf 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -30,7 +30,7 @@ include $(TOPDIR)/rules.mk + SRCS=pfmlib_common.c + + ifeq ($(SYS),Linux) +-SRCS += pfmlib_perf_event_pmu.c pfmlib_perf_event.c ++SRCS += pfmlib_perf_event_pmu.c pfmlib_perf_event.c pfmlib_perf_event_raw.c + endif + + CFLAGS+=-D_REENTRANT -I. +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index b9d1d67..bd2f49f 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -170,6 +170,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + #endif + #ifdef __linux__ + &perf_event_support, ++ &perf_event_raw_support, + #endif + }; + #define PFMLIB_NUM_PMUS (int)(sizeof(pfmlib_pmus)/sizeof(pfmlib_pmu_t *)) +diff --git a/lib/pfmlib_perf_event_raw.c b/lib/pfmlib_perf_event_raw.c +new file mode 100644 +index 0000000..e10d215 +--- /dev/null ++++ b/lib/pfmlib_perf_event_raw.c +@@ -0,0 +1,175 @@ ++/* ++ * pfmlib_perf_events_raw.c: support for raw event syntax ++ * ++ * Copyright (c) 2014 Google, Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pfmlib_priv.h" ++#include "pfmlib_perf_event_priv.h" ++ ++static int ++pfm_perf_raw_detect(void *this) ++{ ++#ifdef __linux__ ++ /* ought to find a better way of detecting PERF */ ++#define PERF_OLD_PROC_FILE "/proc/sys/kernel/perf_counter_paranoid" ++#define PERF_PROC_FILE "/proc/sys/kernel/perf_event_paranoid" ++ return !(access(PERF_PROC_FILE, F_OK) ++ && access(PERF_OLD_PROC_FILE, F_OK)) ? PFM_SUCCESS: PFM_ERR_NOTSUPP; ++#else ++ return PFM_SUCCESS; ++#endif ++} ++ ++static int ++pfm_perf_raw_get_event_first(void *this) ++{ ++ return 0; ++} ++ ++static int ++pfm_perf_raw_get_event_next(void *this, int idx) ++{ ++ /* only one pseudo event */ ++ return -1; ++} ++ ++static int ++pfm_perf_raw_get_encoding(void *this, pfmlib_event_desc_t *e) ++{ ++ /* ++ * actual enoding done in pfm_perf_raw_match_event() ++ */ ++ e->fstr[0] = '\0'; ++ evt_strcat(e->fstr, "r%"PRIx64, e->codes[0]); ++ return PFM_SUCCESS; ++} ++ ++static int ++pfm_perf_raw_get_perf_encoding(void *this, pfmlib_event_desc_t *e) ++{ ++ struct perf_event_attr *attr; ++ ++ attr = e->os_data; ++ attr->type = PERF_TYPE_RAW; ++ attr->config = e->codes[0]; ++ ++ attr->config1 = e->codes[1]; ++ attr->config2 = e->codes[2]; ++ ++ return PFM_SUCCESS; ++} ++ ++static int ++pfm_perf_raw_event_is_valid(void *this, int idx) ++{ ++ return idx == 0; ++} ++ ++static int ++pfm_perf_raw_get_event_attr_info(void *this, int idx, int attr_idx, pfm_event_attr_info_t *info) ++{ ++ return PFM_ERR_ATTR; ++} ++ ++static int ++pfm_perf_raw_get_event_info(void *this, int idx, pfm_event_info_t *info) ++{ ++ pfmlib_pmu_t *pmu = this; ++ ++ info->name = "r0000"; ++ info->desc = "perf_events raw event syntax: r[0-9a-fA-F]+", ++ info->code = 0; ++ info->equiv = NULL; ++ info->idx = 0; ++ info->pmu = pmu->pmu; ++ info->is_precise = 0; ++ ++ /* unit masks + modifiers */ ++ info->nattrs = 0; ++ ++ return PFM_SUCCESS; ++} ++ ++static unsigned int ++pfm_perf_raw_get_event_nattrs(void *this, int idx) ++{ ++ return 0; ++} ++ ++/* ++ * remove attrs which are in conflicts (or duplicated) with os layer ++ */ ++static void ++pfm_perf_raw_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e) ++{ ++} ++ ++/* ++ * returns 0 if match (like strcmp()) ++ */ ++static int ++pfm_perf_raw_match_event(void *this, pfmlib_event_desc_t *d, const char *e, const char *s) ++{ ++ uint64_t code; ++ int ret; ++ ++ if (*s != 'r' || !isxdigit(*(s+1))) ++ return 1; ++ ++ ret = sscanf(s+1, "%"PRIx64, &code); ++ if (ret != 1) ++ return 1; ++ /* ++ * stash code in final position ++ */ ++ d->codes[0] = code; ++ d->count = 1; ++ ++ return 0; ++} ++ ++pfmlib_pmu_t perf_event_raw_support={ ++ .desc = "perf_events raw PMU", ++ .name = "perf_raw", ++ .pmu = PFM_PMU_PERF_EVENT_RAW, ++ .pme_count = 1, ++ .type = PFM_PMU_TYPE_OS_GENERIC, ++ .max_encoding = 1, ++ .supported_plm = PERF_PLM_ALL, ++ .pmu_detect = pfm_perf_raw_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_perf_raw_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_perf_raw_get_perf_encoding), ++ .get_event_first = pfm_perf_raw_get_event_first, ++ .get_event_next = pfm_perf_raw_get_event_next, ++ .event_is_valid = pfm_perf_raw_event_is_valid, ++ .get_event_info = pfm_perf_raw_get_event_info, ++ .get_event_attr_info = pfm_perf_raw_get_event_attr_info, ++ .get_event_nattrs = pfm_perf_raw_get_event_nattrs, ++ .match_event = pfm_perf_raw_match_event, ++ PFMLIB_VALID_PERF_PATTRS(pfm_perf_raw_perf_validate_pattrs), ++}; +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index aa7f819..e1a2458 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -288,6 +288,7 @@ extern pfmlib_pmu_t sparc_niagara1_support; + extern pfmlib_pmu_t sparc_niagara2_support; + extern pfmlib_pmu_t cell_support; + extern pfmlib_pmu_t perf_event_support; ++extern pfmlib_pmu_t perf_event_raw_support; + extern pfmlib_pmu_t intel_wsm_sp_support; + extern pfmlib_pmu_t intel_wsm_dp_support; + extern pfmlib_pmu_t intel_wsm_unc_support; +commit 6c21b52f3fd6815505fe2ed68f82a02d44fde6cb +Author: Stephane Eranian +Date: Wed Feb 19 15:01:32 2014 +0100 + + create a per-system man variable in man pages Makefile + + This patches add SYS_MAN to separate system-specific + man pages. For instance, the perf_events entry points + are only available on Linux. + + Signed-off-by: Stephane Eranian + +diff --git a/docs/Makefile b/docs/Makefile +index 45180d5..bbc73c6 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -28,6 +28,7 @@ include $(TOPDIR)/rules.mk + .PHONY: all clean distclean depend + + ARCH_MAN= ++SYS_MAN= + + ifeq ($(CONFIG_PFMLIB_ARCH_X86),y) + ARCH_MAN=libpfm_intel_core.3 \ +@@ -81,14 +81,17 @@ GEN_MAN= libpfm.3 \ + pfm_get_event_encoding.3 \ + pfm_get_event_next.3 \ + pfm_get_pmu_info.3 \ +- pfm_get_perf_event_encoding.3 \ + pfm_get_os_event_encoding.3 \ + pfm_get_version.3 \ + pfm_initialize.3 \ + pfm_terminate.3 \ + pfm_strerror.3 + +-MAN=$(GEN_MAN) $(ARCH_MAN) ++ifeq ($(SYS),Linux) ++SYS_MAN=pfm_get_perf_event_encoding.3 ++endif ++ ++MAN=$(GEN_MAN) $(ARCH_MAN) $(SYS_MAN) + + install: + +commit 1703fb2f259c330707373b3badb5192d6a193c1c +Author: Stephane Eranian +Date: Wed Feb 19 15:53:46 2014 +0100 + + add man page for perf_events RAW PMU + + Add the man page for the perf_events pseudo PMU + to pass raw events syntax. + + Signed-off-by: Stephane Eranian + +diff --git a/docs/Makefile b/docs/Makefile +index bbc73c6..330c26b 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -88,7 +88,7 @@ GEN_MAN= libpfm.3 \ + pfm_strerror.3 + + ifeq ($(SYS),Linux) +-SYS_MAN=pfm_get_perf_event_encoding.3 ++SYS_MAN=pfm_get_perf_event_encoding.3 libpfm_perf_event_raw.3 + endif + + MAN=$(GEN_MAN) $(ARCH_MAN) $(SYS_MAN) +diff --git a/docs/man3/libpfm_perf_event_raw.3 b/docs/man3/libpfm_perf_event_raw.3 +new file mode 100644 +index 0000000..2f8b535 +--- /dev/null ++++ b/docs/man3/libpfm_perf_event_raw.3 +@@ -0,0 +1,76 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_perf_event_raw - support for perf_events raw events syntax ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: perf_raw ++.B PMU desc: Raw perf_events event syntax ++.sp ++.SH DESCRIPTION ++The library supports a pseudo PMU model to allow raw encodings of PMU events ++for the Linux perf_events kernel interface. ++ ++With this PMU, it is possible to provide the raw hexadecimal encoding of any ++hardware event for any PMU models. The raw encoding is passed as is to the ++kernel. All events are encoded as \fBPERF_TYPE_RAW\fR. As such, perf_events ++generic events, such as cycles, instructions, cannot be encoded by this ++PMU. ++ ++The syntax is very simple: rX. X is the hexadecimal 64-bit value for the event. ++It may include event filters on some PMU models. The hexadecimal number is passed ++without the 0x prefix, e.g., r01c4. ++ ++The library's standard perf_events attributes are supported oby this PMU model. ++They are separated with colons as is customary with the library. ++ ++.SH MODIFIERS ++The following modifiers are supported by this PMU model: ++.TP ++.B u ++Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B h ++Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. ++This is a boolean modifier ++.TP ++.B mg ++Measure guest execution only. This is a boolean modifier ++.TP ++.B mh ++Measure host execution only. This is a boolean modifier ++.TP ++.B period ++Specify the the sampling period value. Value can be expressed in decimal or hexadecimal. ++Value is 64-bit wide. This option is mutually exclusive with ++\fBfreq\fR. The period is expressed in the unit of the event. There is no default value. ++.TP ++.B freq ++Specify the the sampling frequency value. Value can be expressed in decimal or hexadecimal. ++Value is 64-bit wide. This options is mutually exclusive with ++\fBperiod\fR. The value is expressed in Hertz. For instance, freq=100, means that the ++event should be sampled 100 times per second on average. There is no default value. ++.TP ++.B excl ++The associated event is the only event measured on the PMU. This applies only to hardware ++events. This atrtribute requires admin privileges. Default is off. ++.TP ++.B precise ++Enables precise sampling mode. This option is only valid on sampling events. This is an ++integer value. It can have the following values: 1 enable precise sampling, 2 enable precise ++sampling and eliminate skid. Not all events necessarily support precise mode, this is dependent ++on the underlying PMU. Eliminating skid is a best effort feature. It may not work for all ++samples. ++ ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +commit 921eb7acc4082f8dd0e7efe27918ee666e2b291d +Author: Stephane Eranian +Date: Mon Jan 27 02:25:00 2014 -0800 + + add Intel IvyBridge-EP (IvyTown) uncore PMU support + + This patch adds support for Intel IvyBridge-EP (IvyTown) + uncore PMUs. That includes the following PMUs: + - CBOX + - UBOX + - PCU + - HA + - IMC + - IRP + - R3QPI + - R2PCIE + - QPI + + This event table are based on the following documentation: + http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf + + Signed-off-by: Stephane Eranian + +diff --git a/docs/Makefile b/docs/Makefile +index 330c26b..ecf6769 100644 +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -58,6 +58,15 @@ ARCH_MAN=libpfm_intel_core.3 \ + libpfm_intel_snbep_unc_ubo.3 \ + libpfm_intel_snbep_unc_r2pcie.3 \ + libpfm_intel_snbep_unc_r3qpi.3 \ ++ libpfm_intel_ivbep_unc_cbo.3 \ ++ libpfm_intel_ivbep_unc_ha.3 \ ++ libpfm_intel_ivbep_unc_imc.3 \ ++ libpfm_intel_ivbep_unc_pcu.3 \ ++ libpfm_intel_ivbep_unc_qpi.3 \ ++ libpfm_intel_ivbep_unc_ubo.3 \ ++ libpfm_intel_ivbep_unc_r2pcie.3 \ ++ libpfm_intel_ivbep_unc_r3qpi.3 \ ++ libpfm_intel_ivbep_unc_irp.3 \ + libpfm_intel_knc.3 + + ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) +diff --git a/docs/man3/libpfm_intel_ivbep_unc_cbo.3 b/docs/man3/libpfm_intel_ivbep_unc_cbo.3 +new file mode 100644 +index 0000000..e417a46 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_cbo.3 +@@ -0,0 +1,68 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_cbo - support for Intel Ivy Bridge-EP C-Box uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_cbo[0-7] ++.B PMU desc: Intel Ivy Bridge-EP C-Box uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge C-Box (coherency engine) uncore PMU. ++This PMU model only exists on Ivy Bridge model 45. There is one C-box ++PMU per physical core. Therefore there are up to fifteen identical C-Box PMU instances ++numbered from 0 to 14. On dual-socket systems, the number refers to the C-Box ++PMU on the socket where the program runs. For instance, if running on CPU15, then ++ivbep_unc_cbo0 refers to the C-Box for physical core 0 on socket 1. Conversely, ++if running on CPU0, then the same ivbep_unc_cbo0 refers to the C-Box for physical ++core 0 but on socket 0. ++ ++Each C-Box PMU implements 4 generic counters and two filter registers used only ++with certain events and umasks. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of C-Box cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:255]. ++.TP ++.B nf ++Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. ++Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. ++The node filter is an 8-bit max bitmask. A node corresponds to a processor ++socket. The legal values therefore depdend on the underlying hardware configuration. For ++dual-socket systems, the bitmask has two valid bits [0:1]. ++.TP ++.B cf ++Core Filter. This is a 3-bit filter which is used to filter based on phyiscal core origin ++of the C-Box request. Possible values are 0-7. If the filter is not specified, then no ++filtering takes place. ++.TP ++.B tf ++Thread Filter. This is a 1-bit filter which is used to filter C-Box requests based on logical ++processor (hyper-thread) identification. Possibles values are 0-1. If the filter is not ++specified, then no filtering takes place. ++ ++.SH Opcode filtering ++ ++Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction ++type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. ++Second, the opcode to match on must be selected via a second umasks amongs the OPC_* umasks. ++For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO ++transactions. ++ ++Opcode matching may be combined with node filtering with certain umasks. In general, the ++filtering support is encoded into the umask name, e.g., NID_OPCODE supports both ++node and opcode filtering. For instance, UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:nf=1. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_ha.3 b/docs/man3/libpfm_intel_ivbep_unc_ha.3 +new file mode 100644 +index 0000000..0d4d4e2 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_ha.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_ha - support for Intel Ivy Bridge-EP Home Agent (HA) uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_ha0, ivbep_unc_ha1 ++.B PMU desc: Intel Ivy Bridge-EP HA uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge Home Agent (HA) uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge HA uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of HA cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:255]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_imc.3 b/docs/man3/libpfm_intel_ivbep_unc_imc.3 +new file mode 100644 +index 0000000..0050bcb +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_imc.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_imc - support for Intel Ivy Bridge-EP Integrated Memory Controller (IMC) uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_imc[0-7] ++.B PMU desc: Intel Ivy Bridge-EP IMC uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge Integrated Memory Controller (IMC) uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of IMC cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:255]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_irp.3 b/docs/man3/libpfm_intel_ivbep_unc_irp.3 +new file mode 100644 +index 0000000..7f4f8b0 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_irp.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_irp - support for Intel Ivy Bridge-EP IRP uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_irp ++.B PMU desc: Intel Ivy Bridge-EP IRP uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge IRP uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:255]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_pcu.3 b/docs/man3/libpfm_intel_ivbep_unc_pcu.3 +new file mode 100644 +index 0000000..65ec6a3 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_pcu.3 +@@ -0,0 +1,44 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_pcu - support for Intel Ivy Bridge-EP Power Controller Unit (PCU) uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_pcu ++.B PMU desc: Intel Ivy Bridge-EP PCU uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge Power Controller Unit uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge C-Box uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of HA cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:15]. ++.TP ++.B ff ++Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. ++The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be ++multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++counted. ++ ++.SH Frequency band filtering ++ ++There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, ++UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into ++a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the ++encoding for each event individually because it processes events one at a time. The caller or the underlying kernel ++interface may have to merge the band filter settings to program the filter register properly. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_qpi.3 b/docs/man3/libpfm_intel_ivbep_unc_qpi.3 +new file mode 100644 +index 0000000..2b33f47 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_qpi.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_qpi - support for Intel Ivy Bridge-EP QPI uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_qpi0, ivbep_unc_qpi1 ++.B PMU desc: Intel Ivy Bridge-EP QPI uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge Power QPI uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge QPI uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of QPI cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:255]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_r2pcie.3 b/docs/man3/libpfm_intel_ivbep_unc_r2pcie.3 +new file mode 100644 +index 0000000..196e46e +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_r2pcie.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_r2pcie - support for Intel Ivy Bridge-EP R2 PCIe uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_r2pcie ++.B PMU desc: Intel Ivy Bridge-EP R2 PCIe uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge R2 PCIe uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge R2PCIe uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of R2PCIe cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:15]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_r3qpi.3 b/docs/man3/libpfm_intel_ivbep_unc_r3qpi.3 +new file mode 100644 +index 0000000..1f7f48b +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_r3qpi.3 +@@ -0,0 +1,30 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_r3qpi - support for Intel Ivy Bridge-EP R3QPI uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_r3qpi0, ivbep_unc_r3qpi1, ivbep_unc_r3qpi2 ++.B PMU desc: Intel Ivy Bridge-EP R3QPI uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge R3QPI uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge R3PQI uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of R3QPI cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:15]. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/docs/man3/libpfm_intel_ivbep_unc_ubo.3 b/docs/man3/libpfm_intel_ivbep_unc_ubo.3 +new file mode 100644 +index 0000000..2c4a6c1 +--- /dev/null ++++ b/docs/man3/libpfm_intel_ivbep_unc_ubo.3 +@@ -0,0 +1,54 @@ ++.TH LIBPFM 3 "February, 2014" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_intel_ivbep_unc_ubo - support for Intel Ivy Bridge-EP U-Box uncore PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: ivbep_unc_ubo ++.B PMU desc: Intel Ivy Bridge-EP U-Box uncore PMU ++.sp ++.SH DESCRIPTION ++The library supports the Intel Ivy Bridge system configuration unit (U-Box) uncore PMU. ++This PMU model only exists on Ivy Bridge model 62. ++ ++.SH MODIFIERS ++The following modifiers are supported on Intel Ivy Bridge U-Box uncore PMU: ++.TP ++.B e ++Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. ++.TP ++.B t ++Set the threshold value. When set to a non-zero value, the counter counts the number ++of HA cycles in which the number of occurrences of the event is greater or equal to ++the threshold. This is an integer modifier with values in the range [0:15]. ++.TP ++.B oi ++Invert the meaning of the occupancy event POWER_STATE_OCCUPANCY. The counter will now count PCU cycles in which the ++event is \fBnot\fR occurring. This is a boolean modifier ++.TP ++.B oe ++Enable edge detection for the occupancy event POWER_STATE_OCCUPANCY. The event now counts only when there is a state ++transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold ++modifier (t) with a value greater or equal to one. This is a boolean modifier. ++ ++.TP ++.B ff ++Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. ++The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be ++multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++counted. ++ ++.SH Frequency band filtering ++ ++There are 3 events which support frequency band filtering, namely, UNC_P_FREQ_BAND0_CYCLES, UNC_P_FREQ_BAND1_CYCLES, ++UNC_P_FREQ_BAND2_CYCLES, UNC_P_FREQ_BAND3_CYCLES. The frequency filter (available via the ff modifier) is stored into ++a PMU shared register which hold all 4 possible frequency bands, one per event. However, the library generate the ++encoding for each event individually because it processes events one at a time. The caller or the underlying kernel ++interface may have to merge the band filter settings to program the filter register properly. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index 76bca1b..ccd3211 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -199,6 +199,42 @@ typedef enum { + + PFM_PMU_PERF_EVENT_RAW, /* perf_events RAW event syntax */ + ++ PFM_PMU_INTEL_IVBEP_UNC_CB0, /* Intel IvyBridge-EP C-Box core 0 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB1, /* Intel IvyBridge-EP C-Box core 1 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB2, /* Intel IvyBridge-EP C-Box core 2 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB3, /* Intel IvyBridge-EP C-Box core 3 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB4, /* Intel IvyBridge-EP C-Box core 4 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB5, /* Intel IvyBridge-EP C-Box core 5 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB6, /* Intel IvyBridge-EP C-Box core 6 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB7, /* Intel IvyBridge-EP C-Box core 7 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB8, /* Intel IvyBridge-EP C-Box core 8 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB9, /* Intel IvyBridge-EP C-Box core 9 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB10, /* Intel IvyBridge-EP C-Box core 10 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB11, /* Intel IvyBridge-EP C-Box core 11 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB12, /* Intel IvyBridge-EP C-Box core 12 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB13, /* Intel IvyBridge-EP C-Box core 13 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_CB14, /* Intel IvyBridge-EP C-Box core 14 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_HA0, /* Intel IvyBridge-EP HA 0 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_HA1, /* Intel IvyBridge-EP HA 1 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC0, /* Intel IvyBridge-EP IMC socket 0 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC1, /* Intel IvyBridge-EP IMC socket 1 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC2, /* Intel IvyBridge-EP IMC socket 2 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC3, /* Intel IvyBridge-EP IMC socket 3 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC4, /* Intel IvyBridge-EP IMC socket 4 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC5, /* Intel IvyBridge-EP IMC socket 5 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC6, /* Intel IvyBridge-EP IMC socket 6 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IMC7, /* Intel IvyBridge-EP IMC socket 7 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_PCU, /* Intel IvyBridge-EP PCU uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_QPI0, /* Intel IvyBridge-EP QPI link 0 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_QPI1, /* Intel IvyBridge-EP QPI link 1 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_QPI2, /* Intel IvyBridge-EP QPI link 2 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_UBOX, /* Intel IvyBridge-EP U-Box uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_R2PCIE, /* Intel IvyBridge-EP R2PCIe uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_R3QPI0, /* Intel IvyBridge-EP R3QPI 0 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_R3QPI1, /* Intel IvyBridge-EP R3QPI 1 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_R3QPI2, /* Intel IvyBridge-EP R3QPI 2 uncore */ ++ PFM_PMU_INTEL_IVBEP_UNC_IRP, /* Intel IvyBridge-EP IRP uncore */ ++ + /* MUST ADD NEW PMU MODELS HERE */ + + PFM_PMU_MAX /* end marker */ +diff --git a/lib/Makefile b/lib/Makefile +index e4530bf..531167e 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -70,6 +70,15 @@ SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ + pfmlib_intel_snbep_unc_ubo.c \ + pfmlib_intel_snbep_unc_r2pcie.c \ + pfmlib_intel_snbep_unc_r3qpi.c \ ++ pfmlib_intel_ivbep_unc_cbo.c \ ++ pfmlib_intel_ivbep_unc_ha.c \ ++ pfmlib_intel_ivbep_unc_imc.c \ ++ pfmlib_intel_ivbep_unc_pcu.c \ ++ pfmlib_intel_ivbep_unc_qpi.c \ ++ pfmlib_intel_ivbep_unc_ubo.c \ ++ pfmlib_intel_ivbep_unc_r2pcie.c \ ++ pfmlib_intel_ivbep_unc_r3qpi.c \ ++ pfmlib_intel_ivbep_unc_irp.c \ + pfmlib_intel_knc.c \ + pfmlib_intel_slm.c \ + pfmlib_intel_netburst.c \ +@@ -219,6 +228,15 @@ INC_X86= pfmlib_intel_x86_priv.h \ + events/intel_snbep_unc_r2pcie_events.h \ + events/intel_snbep_unc_r3qpi_events.h \ + events/intel_knc_events.h \ ++ events/intel_ivbep_unc_cbo_events.h \ ++ events/intel_ivbep_unc_ha_events.h \ ++ events/intel_ivbep_unc_imc_events.h \ ++ events/intel_ivbep_unc_pcu_events.h \ ++ events/intel_ivbep_unc_qpi_events.h \ ++ events/intel_ivbep_unc_ubo_events.h \ ++ events/intel_ivbep_unc_r2pcie_events.h \ ++ events/intel_ivbep_unc_r3qpi_events.h \ ++ events/intel_ivbep_unc_irp_events.h \ + events/intel_slm_events.h + + INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h +diff --git a/lib/events/intel_ivbep_unc_cbo_events.h b/lib/events/intel_ivbep_unc_cbo_events.h +new file mode 100644 +index 0000000..ee8959f +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_cbo_events.h +@@ -0,0 +1,981 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * PMU: ivbep_unc_cbo (Intel IvyBridge-EP C-Box uncore PMU) ++ */ ++ ++#define CBO_FILT_MESIF(a, b, c, d) \ ++ { .uname = "STATE_"#a,\ ++ .udesc = #b" cacheline state",\ ++ .ufilters[0] = 1ULL << (17 + (c)),\ ++ .grpid = d, \ ++ } ++ ++#define CBO_FILT_MESIFS(d) \ ++ CBO_FILT_MESIF(I, Invalid, 0, d), \ ++ CBO_FILT_MESIF(S, Shared, 1, d), \ ++ CBO_FILT_MESIF(E, Exclusive, 2, d), \ ++ CBO_FILT_MESIF(M, Modified, 3, d), \ ++ CBO_FILT_MESIF(F, Forward, 4, d), \ ++ { .uname = "STATE_MESIF",\ ++ .udesc = "Any cache line state",\ ++ .ufilters[0] = 0x3fULL << 17,\ ++ .grpid = d, \ ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, \ ++ } ++ ++#define CBO_FILT_OPC(d) \ ++ { .uname = "OPC_RFO",\ ++ .udesc = "Demand data RFO (combine with any OPCODE umask)",\ ++ .ufilters[1] = 0x180ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_CRD",\ ++ .udesc = "Demand code read (combine with any OPCODE umask)",\ ++ .ufilters[1] = 0x181ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_DRD",\ ++ .udesc = "Demand data read (combine with any OPCODE umask)",\ ++ .ufilters[1] = 0x182ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PRD",\ ++ .udesc = "Partial reads (UC) (combine with any OPCODE umask)",\ ++ .ufilters[1] = 0x187ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_WCILF",\ ++ .udesc = "Full Stream store (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x18cULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_WCIL",\ ++ .udesc = "Partial Stream store (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x18dULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PF_RFO",\ ++ .udesc = "Prefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x190ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PF_CODE",\ ++ .udesc = "Prefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x191ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PF_DATA",\ ++ .udesc = "Prefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x192ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCIWILF",\ ++ .udesc = "PCIe write (non-allocating) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x194ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCIPRD",\ ++ .udesc = "PCIe UC read (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x195ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCIITOM",\ ++ .udesc = "PCIe write (allocating) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x19cULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCIRDCUR",\ ++ .udesc = "PCIe read current (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x19eULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_WBMTOI",\ ++ .udesc = "Request writeback modified invalidate line (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1c4ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_WBMTOE",\ ++ .udesc = "Request writeback modified set to exclusive (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1c5ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_ITOM",\ ++ .udesc = "Request invalidate line (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1c8ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCINSRD",\ ++ .udesc = "PCIe non-snoop read (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1e4ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCINSWR",\ ++ .udesc = "PCIe non-snoop write (partial) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1e5ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ }, \ ++ { .uname = "OPC_PCINSWRF",\ ++ .udesc = "PCIe non-snoop write (full) (combine with any OPCODE umask)", \ ++ .ufilters[1] = 0x1e6ULL << 20, \ ++ .uflags = INTEL_X86_NCOMBO, \ ++ .grpid = d, \ ++ } ++ ++static const intel_x86_umask_t ivbep_unc_c_llc_lookup[]={ ++ { .uname = "DATA_READ", ++ .udesc = "Data read requests", ++ .grpid = 0, ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WRITE", ++ .udesc = "Write requests. Includes all write transactions (cached, uncached)", ++ .grpid = 0, ++ .ucode = 0x500, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REMOTE_SNOOP", ++ .udesc = "External snoop request", ++ .grpid = 0, ++ .ucode = 0x900, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ANY", ++ .udesc = "Any request", ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ .ucode = 0x1100, ++ }, ++ { .uname = "NID", ++ .udesc = "Match a given RTID destination NID", ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .grpid = 1, ++ .ucode = 0x4100, ++ .uflags = INTEL_X86_GRP_DFL_NONE ++ }, ++ CBO_FILT_MESIFS(2), ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_llc_victims[]={ ++ { .uname = "STATE_M", ++ .udesc = "Lines in M state", ++ .ucode = 0x100, ++ .grpid = 0, ++ }, ++ { .uname = "STATE_E", ++ .udesc = "Lines in E state", ++ .ucode = 0x200, ++ .grpid = 0, ++ }, ++ { .uname = "STATE_S", ++ .udesc = "Lines in S state", ++ .ucode = 0x400, ++ .grpid = 0, ++ }, ++ { .uname = "MISS", ++ .udesc = "TBD", ++ .ucode = 0x800, ++ .grpid = 0, ++ }, ++ { .uname = "NID", ++ .udesc = "Victimized Lines matching the NID filter", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_GRP_DFL_NONE, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .grpid = 1, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_ring_ad_used[]={ ++ { .uname = "UP_VR0_EVEN", ++ .udesc = "Up and Even ring polarity filter on virutal ring 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "UP_VR0_ODD", ++ .udesc = "Up and odd ring polarity filter on virtual ring 0", ++ .ucode = 0x200, ++ }, ++ { .uname = "DOWN_VR0_EVEN", ++ .udesc = "Down and even ring polarity filter on virtual ring 0", ++ .ucode = 0x400, ++ }, ++ { .uname = "DOWN_VR0_ODD", ++ .udesc = "Down and odd ring polarity filter on virtual ring 0", ++ .ucode = 0x800, ++ }, ++ { .uname = "UP_VR1_EVEN", ++ .udesc = "Up and Even ring polarity filter on virutal ring 1", ++ .ucode = 0x1000, ++ }, ++ { .uname = "UP_VR1_ODD", ++ .udesc = "Up and odd ring polarity filter on virtual ring 1", ++ .ucode = 0x2000, ++ }, ++ { .uname = "DOWN_VR1_EVEN", ++ .udesc = "Down and even ring polarity filter on virtual ring 1", ++ .ucode = 0x4000, ++ }, ++ { .uname = "DOWN_VR1_ODD", ++ .udesc = "Down and odd ring polarity filter on virtual ring 1", ++ .ucode = 0x8000, ++ }, ++ { .uname = "UP", ++ .udesc = "Up on any virtual ring", ++ .ucode = 0x3300, ++ }, ++ { .uname = "DOWN", ++ .udesc = "Down any virtual ring", ++ .ucode = 0xcc00, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_ring_bounces[]={ ++ { .uname = "AD_IRQ", ++ .udesc = "TBD", ++ .ucode = 0x200, ++ }, ++ { .uname = "AK", ++ .udesc = "Acknowledgments to core", ++ .ucode = 0x400, ++ }, ++ ++ { .uname = "BL", ++ .udesc = "Data responses to core", ++ .ucode = 0x800, ++ }, ++ { .uname = "IV", ++ .udesc = "Snoops of processor cache", ++ .ucode = 0x1000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_ring_iv_used[]={ ++ { .uname = "ANY", ++ .udesc = "Any filter", ++ .ucode = 0xf00, ++ .uflags = INTEL_X86_DFL, ++ }, ++ { .uname = "UP", ++ .udesc = "Filter on any up polarity", ++ .ucode = 0x3300, ++ }, ++ { .uname = "DOWN", ++ .udesc = "Filter on any down polarity", ++ .ucode = 0xcc00, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_ext_starved[]={ ++ { .uname = "IRQ", ++ .udesc = "Irq externally starved, therefore blocking the IPQ", ++ .ucode = 0x100, ++ }, ++ { .uname = "IPQ", ++ .udesc = "IPQ externally starved, therefore blocking the IRQ", ++ .ucode = 0x200, ++ }, ++ { .uname = "PRQ", ++ .udesc = "IRQ is blocking the ingress queue and causing starvation", ++ .ucode = 0x400, ++ }, ++ { .uname = "ISMQ_BIDS", ++ .udesc = "Number of time the ISMQ bids", ++ .ucode = 0x800, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_inserts[]={ ++ { .uname = "IPQ", ++ .udesc = "IPQ", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IRQ", ++ .udesc = "IRQ", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IRQ_REJECTED", ++ .udesc = "IRQ rejected", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "VFIFO", ++ .udesc = "Counts the number of allocated into the IRQ ordering FIFO", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_ipq_retry[]={ ++ { .uname = "ADDR_CONFLICT", ++ .udesc = "Address conflict", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ANY", ++ .udesc = "Any Reject", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "FULL", ++ .udesc = "No Egress credits", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "QPI_CREDITS", ++ .udesc = "No QPI credits", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_irq_retry[]={ ++ { .uname = "ADDR_CONFLICT", ++ .udesc = "Address conflict", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ANY", ++ .udesc = "Any reject", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "FULL", ++ .udesc = "No Egress credits", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "QPI_CREDITS", ++ .udesc = "No QPI credits", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RTID", ++ .udesc = "No RTIDs", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IIO_CREDITS", ++ .udesc = "No IIO Credits", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_ismq_retry[]={ ++ { .uname = "ANY", ++ .udesc = "Any reject", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "FULL", ++ .udesc = "No Egress credits", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IIO_CREDITS", ++ .udesc = "No IIO credits", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "QPI_CREDITS", ++ .udesc = "NO QPI credits", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RTID", ++ .udesc = "No RTIDs", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WB_CREDITS", ++ .udesc = "No WB credits", ++ .ucode = 0x8000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_rxr_occupancy[]={ ++ { .uname = "IPQ", ++ .udesc = "IPQ", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IRQ", ++ .udesc = "IRQ", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IRQ_REJECTED", ++ .udesc = "IRQ rejected", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "VFIFO", ++ .udesc = "Number of used entries in the IRQ ordering FIFO in each cycle", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_tor_inserts[]={ ++ { .uname = "OPCODE", ++ .udesc = "Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)", ++ .ucode = 0x100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_OPCODE", ++ .udesc = "Number of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)", ++ .ucode = 0x300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EVICTION", ++ .udesc = "Number of Evictions transactions inserted into TOR", ++ .ucode = 0x400, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "ALL", ++ .udesc = "Number of transactions inserted in TOR", ++ .ucode = 0x800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "WB", ++ .udesc = "Number of write transactions inserted into the TOR", ++ .ucode = 0x1000, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "LOCAL_OPCODE", ++ .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_LOCAL_OPCODE", ++ .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "LOCAL", ++ .udesc = "Number of transactions inserted into the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "MISS_LOCAL", ++ .udesc = "Number of miss transactions inserted into the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2a00, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_OPCODE", ++ .udesc = "Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)", ++ .ucode = 0x4100, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NID_MISS_OPCODE", ++ .udesc = "Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)", ++ .ucode = 0x4300, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NID_EVICTION", ++ .udesc = "Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)", ++ .ucode = 0x4400, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_ALL", ++ .udesc = "Number of NID-matched transactions inserted into the TOR", ++ .ucode = 0x4800, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_MISS_ALL", ++ .udesc = "Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)", ++ .ucode = 0x4a00, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_WB", ++ .udesc = "Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)", ++ .ucode = 0x5000, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "REMOTE_OPCODE", ++ .udesc = "Number of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_REMOTE_OPCODE", ++ .udesc = "Number of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REMOTE", ++ .udesc = "Number of transactions inserted into the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "MISS_REMOTE", ++ .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8a00, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ CBO_FILT_OPC(1) ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_tor_occupancy[]={ ++ { .uname = "OPCODE", ++ .udesc = "Number of TOR entries that match an opcode (must provide opc_* umask)", ++ .ucode = 0x100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_OPCODE", ++ .udesc = "Number of TOR entries that match a NID and an opcode (must provide opc_* umask)", ++ .ucode = 0x300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EVICTION", ++ .udesc = "Number of outstanding eviction transactions in the TOR", ++ .ucode = 0x400, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "ALL", ++ .udesc = "All valid TOR entries", ++ .ucode = 0x800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "MISS_ALL", ++ .udesc = "Number of outstanding miss requests in the TOR", ++ .ucode = 0xa00, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "WB", ++ .udesc = "Number of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the core", ++ .ucode = 0x1000, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "LOCAL_OPCODE", ++ .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_LOCAL_OPCODE", ++ .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "LOCAL", ++ .udesc = "Number of transactions in the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "MISS_LOCAL", ++ .udesc = "Number of miss transactions in the TOR that are satisfied by locally homed memory", ++ .ucode = 0x2a00, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_OPCODE", ++ .udesc = "Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)", ++ .ucode = 0x4100, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NID_MISS_OPCODE", ++ .udesc = "Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)", ++ .ucode = 0x4300, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NID_EVICTION", ++ .udesc = "Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)", ++ .ucode = 0x4400, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_ALL", ++ .udesc = "Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)", ++ .ucode = 0x4800, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_MISS_ALL", ++ .udesc = "Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)", ++ .ucode = 0x4a00, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "NID_WB", ++ .udesc = "Number of NID-matched write transactions in the TOR (must provide a nf=X modifier)", ++ .ucode = 0x5000, ++ .grpid = 0, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF1, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "REMOTE_OPCODE", ++ .udesc = "Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8100, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MISS_REMOTE_OPCODE", ++ .udesc = "Number of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8300, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REMOTE", ++ .udesc = "Number of transactions in the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8800, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ { .uname = "MISS_REMOTE", ++ .udesc = "Number of miss transactions inserted into the TOR that are satisfied by remote caches or memory", ++ .ucode = 0x8a00, ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, ++ }, ++ CBO_FILT_OPC(1) ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_txr_inserts[]={ ++ { .uname = "AD_CACHE", ++ .udesc = "Counts the number of ring transactions from Cachebo to AD ring", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "AK_CACHE", ++ .udesc = "Counts the number of ring transactions from Cachebo to AK ring", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "BL_CACHE", ++ .udesc = "Counts the number of ring transactions from Cachebo to BL ring", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IV_CACHE", ++ .udesc = "Counts the number of ring transactions from Cachebo ton IV ring", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "AD_CORE", ++ .udesc = "Counts the number of ring transactions from Corebo to AD ring", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "AK_CORE", ++ .udesc = "Counts the number of ring transactions from Corebo to AK ring", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "BL_CORE", ++ .udesc = "Counts the number of ring transactions from Corebo to BL ring", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_txr_ads_used[]={ ++ { .uname = "AD", ++ .udesc = "onto AD ring", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "AK", ++ .udesc = "Onto AK ring", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "BL", ++ .udesc = "Onto BL ring", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_c_misc[]={ ++ { .uname = "RSPI_WAS_FSE", ++ .udesc = "Counts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WC_ALIASING", ++ .udesc = "Counts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasing", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "STARTED", ++ .udesc = "TBD", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RFO_HIT_S", ++ .udesc = "Counts the number of times that an RFO hits in S state. This is usfeul for determining if it might be good for a workload to use RSPIWB instead of RSPSWB", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_c_pe[]={ ++ { .name = "UNC_C_CLOCKTICKS", ++ .desc = "C-box Uncore clockticks", ++ .modmsk = 0x0, ++ .cntmsk = 0xf, ++ .code = 0x00, ++ .flags = INTEL_X86_FIXED, ++ }, ++ { .name = "UNC_C_COUNTER0_OCCUPANCY", ++ .desc = "Counter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0xe, ++ .code = 0x1f, ++ }, ++ { .name = "UNC_C_LLC_LOOKUP", ++ .desc = "Cache lookups", ++ .modmsk = IVBEP_UNC_CBO_NID_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x34, ++ .ngrp = 3, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_llc_lookup), ++ .umasks = ivbep_unc_c_llc_lookup, ++ }, ++ { .name = "UNC_C_LLC_VICTIMS", ++ .desc = "Lines victimized", ++ .modmsk = IVBEP_UNC_CBO_NID_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x37, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_llc_victims), ++ .ngrp = 2, ++ .umasks = ivbep_unc_c_llc_victims, ++ }, ++ { .name = "UNC_C_MISC", ++ .desc = "Miscelleanous C-Box events", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x39, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_misc), ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_misc, ++ }, ++ { .name = "UNC_C_RING_AD_USED", ++ .desc = "Address ring in use. Counts number of cycles ring is being used at this ring stop", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0xc, ++ .code = 0x1b, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_ring_ad_used, ++ }, ++ { .name = "UNC_C_RING_AK_USED", ++ .desc = "Acknowledgement ring in use. Counts number of cycles ring is being used at this ring stop", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0xc, ++ .code = 0x1c, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_ring_ad_used, ++ }, ++ { .name = "UNC_C_RING_BL_USED", ++ .desc = "Bus or Data ring in use. Counts number of cycles ring is being used at this ring stop", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0xc, ++ .code = 0x1d, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_ad_used), /* identical to RING_AD_USED */ ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_ring_ad_used, ++ }, ++ { .name = "UNC_C_RING_BOUNCES", ++ .desc = "Number of LLC responses that bounced in the ring", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x05, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_bounces), ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_ring_bounces, ++ }, ++ { .name = "UNC_C_RING_IV_USED", ++ .desc = "Invalidate ring in use. Counts number of cycles ring is being used at this ring stop", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0xc, ++ .code = 0x1e, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_ring_iv_used), ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_ring_iv_used, ++ }, ++ { .name = "UNC_C_RING_SRC_THRTL", ++ .desc = "TDB", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x07, ++ }, ++ { .name = "UNC_C_RXR_EXT_STARVED", ++ .desc = "Ingress arbiter blocking cycles", ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .cntmsk = 0x3, ++ .code = 0x12, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ext_starved), ++ .ngrp = 1, ++ .umasks = ivbep_unc_c_rxr_ext_starved, ++ }, ++ { .name = "UNC_C_RXR_INSERTS", ++ .desc = "Ingress Allocations", ++ .code = 0x13, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_inserts), ++ .umasks = ivbep_unc_c_rxr_inserts ++ }, ++ { .name = "UNC_C_RXR_IPQ_RETRY", ++ .desc = "Probe Queue Retries", ++ .code = 0x31, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ipq_retry), ++ .umasks = ivbep_unc_c_rxr_ipq_retry ++ }, ++ { .name = "UNC_C_RXR_IRQ_RETRY", ++ .desc = "Ingress Request Queue Rejects", ++ .code = 0x32, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_irq_retry), ++ .umasks = ivbep_unc_c_rxr_irq_retry ++ }, ++ { .name = "UNC_C_RXR_ISMQ_RETRY", ++ .desc = "ISMQ Retries", ++ .code = 0x33, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_ismq_retry), ++ .umasks = ivbep_unc_c_rxr_ismq_retry ++ }, ++ { .name = "UNC_C_RXR_OCCUPANCY", ++ .desc = "Ingress Occupancy", ++ .code = 0x11, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_rxr_inserts), ++ .umasks = ivbep_unc_c_rxr_inserts, /* identical to ivbep_unc_c_rxr_inserts */ ++ }, ++ { .name = "UNC_C_TOR_INSERTS", ++ .desc = "TOR Inserts", ++ .code = 0x35, ++ .cntmsk = 0x3, ++ .ngrp = 2, ++ .modmsk = IVBEP_UNC_CBO_NID_ATTRS, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_tor_inserts), ++ .umasks = ivbep_unc_c_tor_inserts ++ }, ++ { .name = "UNC_C_TOR_OCCUPANCY", ++ .desc = "TOR Occupancy", ++ .code = 0x36, ++ .cntmsk = 0x1, ++ .ngrp = 2, ++ .modmsk = IVBEP_UNC_CBO_NID_ATTRS, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_tor_occupancy), ++ .umasks = ivbep_unc_c_tor_occupancy ++ }, ++ { .name = "UNC_C_TXR_ADS_USED", ++ .desc = "Egress events", ++ .code = 0x04, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_txr_ads_used), ++ .umasks = ivbep_unc_c_txr_ads_used ++ }, ++ { .name = "UNC_C_TXR_INSERTS", ++ .desc = "Egress allocations", ++ .code = 0x02, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_CBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_c_txr_inserts), ++ .umasks = ivbep_unc_c_txr_inserts ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_ha_events.h b/lib/events/intel_ivbep_unc_ha_events.h +new file mode 100644 +index 0000000..58f0e06 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_ha_events.h +@@ -0,0 +1,925 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * This file has been automatically generated. ++ * ++ * PMU: ivbep_unc_ha (Intel IvyBridge-EP HA uncore PMU) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_h_conflict_cycles[]={ ++ { .uname = "CONFLICT", ++ .udesc = "Number of cycles that we are handling conflicts", ++ .ucode = 0x200, ++ }, ++ { .uname = "LAST", ++ .udesc = "Count every last conflictor in conflict chain. Can be used to compute average conflict chain length", ++ .ucode = 0x400, ++ }, ++ { .uname = "CMP_FWDS", ++ .udesc = "Count the number of cmp_fwd. This gives the number of late conflicts", ++ .ucode = 0x1000, ++ }, ++ { .uname = "ACKCNFLTS", ++ .udesc = "Count the number Acknflts", ++ .ucode = 0x800, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_directory_lookup[]={ ++ { .uname = "NO_SNP", ++ .udesc = "Snoop not needed", ++ .ucode = 0x200, ++ }, ++ { .uname = "SNOOP", ++ .udesc = "SNooop needed", ++ .ucode = 0x100, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_bypass_imc[]={ ++ { .uname = "TAKEN", ++ .udesc = "Bypass taken", ++ .ucode = 0x200, ++ }, ++ { .uname = "NOT_TAKEN", ++ .udesc = "Bypass not taken", ++ .ucode = 0x100, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_directory_update[]={ ++ { .uname = "ANY", ++ .udesc = "Counts any directory update", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "CLEAR", ++ .udesc = "Directory clears", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SET", ++ .udesc = "Directory set", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_igr_no_credit_cycles[]={ ++ { .uname = "AD_QPI0", ++ .udesc = "AD to QPI link 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "AD_QPI1", ++ .udesc = "AD to QPI link 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "BL_QPI0", ++ .udesc = "BL to QPI link 0", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "BL_QPI1", ++ .udesc = "BL to QPI link 1", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_imc_writes[]={ ++ { .uname = "ALL", ++ .udesc = "Counts all writes", ++ .ucode = 0xf00, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "FULL", ++ .udesc = "Counts full line non ISOCH", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FULL_ISOCH", ++ .udesc = "Counts ISOCH full line", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "PARTIAL", ++ .udesc = "Counts partial non-ISOCH", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "PARTIAL_ISOCH", ++ .udesc = "Counts ISOCH partial", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_imc_reads[]={ ++ { .uname = "NORMAL", ++ .udesc = "Normal priority", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_DFL, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_requests[]={ ++ { .uname = "READS", ++ .udesc = "Counts incoming read requests. Good proxy for LLC read misses, incl. RFOs", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "READS_LOCAL", ++ .udesc = "Counts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socket", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "READS_REMOTE", ++ .udesc = "Counts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socket", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WRITES", ++ .udesc = "Counts incoming writes", ++ .ucode = 0xc00, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WRITES_LOCAL", ++ .udesc = "Counts incoming writes from local socket", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WRITES_REMOTE", ++ .udesc = "Counts incoming writes from remote socket", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "INVITOE_LOCAL", ++ .udesc = "Counts InvItoE coming from local socket", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "INVITOE_REMOTE", ++ .udesc = "Counts InvItoE coming from remote socket", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_rpq_cycles_no_reg_credits[]={ ++ { .uname = "CHN0", ++ .udesc = "Channel 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CHN1", ++ .udesc = "Channel 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CHN2", ++ .udesc = "channel 2", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CHN3", ++ .udesc = "Chanell 3", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_tad_requests_g0[]={ ++ { .uname = "REGION0", ++ .udesc = "Counts for TAD Region 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION1", ++ .udesc = "Counts for TAD Region 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION2", ++ .udesc = "Counts for TAD Region 2", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION3", ++ .udesc = "Counts for TAD Region 3", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION4", ++ .udesc = "Counts for TAD Region 4", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION5", ++ .udesc = "Counts for TAD Region 5", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION6", ++ .udesc = "Counts for TAD Region 6", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION7", ++ .udesc = "Counts for TAD Region 7", ++ .ucode = 0x8000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_tad_requests_g1[]={ ++ { .uname = "REGION8", ++ .udesc = "Counts for TAD Region 8", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION9", ++ .udesc = "Counts for TAD Region 9", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION10", ++ .udesc = "Counts for TAD Region 10", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "REGION11", ++ .udesc = "Counts for TAD Region 11", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_snoop_resp[]={ ++ { .uname = "RSPI", ++ .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", ++ .ucode = 0x100, ++ }, ++ { .uname = "RSPS", ++ .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", ++ .ucode = 0x200, ++ }, ++ { .uname = "RSPIFWD", ++ .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", ++ .ucode = 0x400, ++ }, ++ { .uname = "RSPSFWD", ++ .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", ++ .ucode = 0x800, ++ }, ++ { .uname = "RSP_WB", ++ .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", ++ .ucode = 0x1000, ++ }, ++ { .uname = "RSP_FWD_WB", ++ .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", ++ .ucode = 0x2000, ++ }, ++ { .uname = "RSPCNFLCT", ++ .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", ++ .ucode = 0x4000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_ad[]={ ++ { .uname = "NDR", ++ .udesc = "Counts non-data responses", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SNP", ++ .udesc = "Counts outbound snoops send on the ring", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_ad_cycles_full[]={ ++ { .uname = "ALL", ++ .udesc = "Counts cycles full from both schedulers", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "SCHED0", ++ .udesc = "Counts cycles full from scheduler bank 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SCHED1", ++ .udesc = "Counts cycles full from scheduler bank 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_bl_occupancy[]={ ++ { .uname = "SCHED0", ++ .udesc = "Counts cycles full from scheduler bank 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SCHED1", ++ .udesc = "Counts cycles full from scheduler bank 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_ak_cycles_full[]={ ++ { .uname = "ALL", ++ .udesc = "Counts cycles from both schedulers", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "SCHED0", ++ .udesc = "Counts cycles from scheduler bank 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SCHED1", ++ .udesc = "Counts cycles from scheduler bank 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_bl[]={ ++ { .uname = "DRS_CACHE", ++ .udesc = "Counts data being sent to the cache", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "DRS_CORE", ++ .udesc = "Counts data being sent directly to the requesting core", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "DRS_QPI", ++ .udesc = "Counts data being sent to a remote socket over QPI", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_bl_cycles_full[]={ ++ { .uname = "ALL", ++ .udesc = "BL Egress Full", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SCHED0", ++ .udesc = "BL Egress Full", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SCHED1", ++ .udesc = "BL Egress Full", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++#if 0 ++static const intel_x86_umask_t ivbep_unc_h_addr_opc_match[]={ ++ { .uname = "FILT", ++ .udesc = "Number of addr and opcode matches (opc via opc= or address via addr= modifiers)", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL | INTEL_X86_ADDR, ++ }, ++}; ++#endif ++ ++static const intel_x86_umask_t ivbep_unc_h_bt_occupancy[]={ ++ { .uname = "LOCAL", ++ .udesc = "Local", ++ .ucode = 0x100, ++ }, ++ { .uname = "REMOTE", ++ .udesc = "Remote", ++ .ucode = 0x200, ++ }, ++ { .uname = "READS_REMOTE", ++ .udesc = "Reads remote", ++ .ucode = 0x800, ++ }, ++ { .uname = "WRITES_LOCAL", ++ .udesc = "Writes local", ++ .ucode = 0x1000, ++ }, ++ { .uname = "WRITES_REMOTE", ++ .udesc = "Writes remote", ++ .ucode = 0x2000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_bt_to_ht_not_issued[]={ ++ { .uname = "INCOMING_SNP_HAZARD", ++ .udesc = "Number of cycles unable to issue from BT due to incoming snoop hazard", ++ .ucode = 0x200, ++ }, ++ { .uname = "INCOMING_BL_HAZARD", ++ .udesc = "Number of cycles unable to issue from BT due to incoming BL data hazard", ++ .ucode = 0x400, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_osb[]={ ++ { .uname = "REMOTE", ++ .udesc = "Remote", ++ .ucode = 0x800, ++ }, ++ { .uname = "READS_LOCAL", ++ .udesc = "Local reads", ++ .ucode = 0x200, ++ }, ++ { .uname = "INVITOE_LOCAL", ++ .udesc = "Local InvItoE", ++ .ucode = 0x400, ++ } ++}; ++static const intel_x86_umask_t ivbep_unc_h_osb_edr[]={ ++ { .uname = "ALL", ++ .udesc = "All data returns", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, ++ }, ++ { .uname = "READS_LOCAL_I", ++ .udesc = "Reads to local I", ++ .ucode = 0x200, ++ }, ++ { .uname = "READS_REMOTE_I", ++ .udesc = "Reads to remote I", ++ .ucode = 0x400, ++ }, ++ { .uname = "READS_LOCAL_S", ++ .udesc = "Reads to local S", ++ .ucode = 0x800, ++ }, ++ { .uname = "READS_REMOTE_S", ++ .udesc = "Reads to remote S", ++ .ucode = 01000, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_ring_ad_used[]={ ++ { .uname = "CCW_VR0_EVEN", ++ .udesc = "Counter-clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x400, ++ }, ++ { .uname = "CCW_VR0_ODD", ++ .udesc = "Counter-clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x800, ++ }, ++ { .uname = "CW_VR0_EVEN", ++ .udesc = "Clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "CW_VR0_ODD", ++ .udesc = "Clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x200, ++ }, ++ { .uname = "CCW_VR1_EVEN", ++ .udesc = "Counter-clockwise and even ring polarity on virtual ring 1", ++ .ucode = 0x400, ++ }, ++ { .uname = "CCW_VR1_ODD", ++ .udesc = "Counter-clockwise and odd ring polarity on virtual ring 1", ++ .ucode = 0x800, ++ }, ++ { .uname = "CW_VR1_EVEN", ++ .udesc = "Clockwise and even ring polarity on virtual ring 1", ++ .ucode = 0x100, ++ }, ++ { .uname = "CW_VR1_ODD", ++ .udesc = "Clockwise and odd ring polarity on virtual ring 1", ++ .ucode = 0x200, ++ }, ++ { .uname = "CW", ++ .udesc = "Clockwise with any polarity on either virtual rings", ++ .ucode = 0x3300, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xcc00, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_snp_resp_recv_local[]={ ++ { .uname = "RSPI", ++ .udesc = "Filters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)", ++ .ucode = 0x100, ++ }, ++ { .uname = "RSPS", ++ .udesc = "Filters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-state", ++ .ucode = 0x200, ++ }, ++ { .uname = "RSPIFWD", ++ .udesc = "Filters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFE", ++ .ucode = 0x400, ++ }, ++ { .uname = "RSPSFWD", ++ .udesc = "Filters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state", ++ .ucode = 0x800, ++ }, ++ { .uname = "RSP_WB", ++ .udesc = "Filters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership", ++ .ucode = 0x1000, ++ }, ++ { .uname = "RSP_FWD_WB", ++ .udesc = "Filters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memory", ++ .ucode = 0x2000, ++ }, ++ { .uname = "RSPCNFLCT", ++ .udesc = "Filters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBI", ++ .ucode = 0x4000, ++ }, ++ { .uname = "OTHER", ++ .udesc = "Filters all other snoop responses", ++ .ucode = 0x8000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_tracker_cycles_full[]={ ++ { .uname = "GP", ++ .udesc = "Number of cycles when the general purpose (GP) HA trakcer pool is completely used. It will not return valid count when BT is disabled", ++ .ucode = 0x100, ++ }, ++ { .uname = "ALL", ++ .udesc = "Number of cycles when the general purpose (GP) HA trakcer pool is completely used including reserved HT entries. It will not return vaid count when BT is disabled", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_DFL, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_txr_ak[]={ ++ { .uname = "NDR", ++ .udesc = "Number of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socket", ++ .ucode = 0x100, ++ }, ++ { .uname = "CRD_CBO", ++ .udesc = "Number of outbound CDR transactions send on the AK ring to CBO", ++ .ucode = 0x200, ++ }, ++ { .uname = "CRD_QPI", ++ .udesc = "Number of outbound CDR transactions send on the AK ring to QPI", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_h_iodc_conflicts[]={ ++ { .uname = "ANY", ++ .udesc = "Any conflict", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_DFL | INTEL_X86_NCOMBO, ++ }, ++ { .uname = "LAST", ++ .udesc = "Last conflict", ++ .ucode = 0x400, ++ } ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_h_pe[]={ ++ { .name = "UNC_H_CLOCKTICKS", ++ .desc = "HA Uncore clockticks", ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .cntmsk = 0xf, ++ .code = 0x00, ++ }, ++ { .name = "UNC_H_CONFLICT_CYCLES", ++ .desc = "Conflict Checks", ++ .code = 0xb, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_conflict_cycles), ++ .umasks = ivbep_unc_h_conflict_cycles, ++ }, ++ { .name = "UNC_H_DIRECT2CORE_COUNT", ++ .desc = "Direct2Core Messages Sent", ++ .code = 0x11, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_DIRECT2CORE_CYCLES_DISABLED", ++ .desc = "Cycles when Direct2Core was Disabled", ++ .code = 0x12, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_DIRECT2CORE_TXN_OVERRIDE", ++ .desc = "Number of Reads that had Direct2Core Overridden", ++ .code = 0x13, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_DIRECTORY_LOOKUP", ++ .desc = "Directory Lookups", ++ .code = 0xc, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_directory_lookup), ++ .umasks = ivbep_unc_h_directory_lookup ++ }, ++ { .name = "UNC_H_DIRECTORY_UPDATE", ++ .desc = "Directory Updates", ++ .code = 0xd, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_directory_update), ++ .umasks = ivbep_unc_h_directory_update ++ }, ++ { .name = "UNC_H_IGR_NO_CREDIT_CYCLES", ++ .desc = "Cycles without QPI Ingress Credits", ++ .code = 0x22, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_igr_no_credit_cycles), ++ .umasks = ivbep_unc_h_igr_no_credit_cycles ++ }, ++ { .name = "UNC_H_IMC_RETRY", ++ .desc = "Retry Events", ++ .code = 0x1e, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_IMC_WRITES", ++ .desc = "HA to IMC Full Line Writes Issued", ++ .code = 0x1a, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_imc_writes), ++ .umasks = ivbep_unc_h_imc_writes ++ }, ++ { .name = "UNC_H_IMC_READS", ++ .desc = "HA to IMC normal priority reads issued", ++ .code = 0x17, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_imc_reads), ++ .umasks = ivbep_unc_h_imc_reads ++ }, ++ { .name = "UNC_H_REQUESTS", ++ .desc = "Read and Write Requests", ++ .code = 0x1, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_requests), ++ .umasks = ivbep_unc_h_requests ++ }, ++ { .name = "UNC_H_RPQ_CYCLES_NO_REG_CREDITS", ++ .desc = "IMC RPQ Credits Empty", ++ .code = 0x15, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_rpq_cycles_no_reg_credits), ++ .umasks = ivbep_unc_h_rpq_cycles_no_reg_credits ++ }, ++ { .name = "UNC_H_TAD_REQUESTS_G0", ++ .desc = "HA Requests to a TAD Region", ++ .code = 0x1b, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_tad_requests_g0), ++ .umasks = ivbep_unc_h_tad_requests_g0 ++ }, ++ { .name = "UNC_H_TAD_REQUESTS_G1", ++ .desc = "HA Requests to a TAD Region", ++ .code = 0x1c, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_tad_requests_g1), ++ .umasks = ivbep_unc_h_tad_requests_g1 ++ }, ++ { .name = "UNC_H_TXR_AD_CYCLES_FULL", ++ .desc = "AD Egress Full", ++ .code = 0x2a, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ad_cycles_full), ++ .umasks = ivbep_unc_h_txr_ad_cycles_full ++ }, ++ { .name = "UNC_H_TXR_AK_CYCLES_FULL", ++ .desc = "AK Egress Full", ++ .code = 0x32, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak_cycles_full), ++ .umasks = ivbep_unc_h_txr_ak_cycles_full ++ }, ++ { .name = "UNC_H_TXR_AK", ++ .desc = "Outbound Ring Transactions on AK", ++ .code = 0xe, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak), ++ .umasks = ivbep_unc_h_txr_ak ++ }, ++ { .name = "UNC_H_TXR_BL", ++ .desc = "Outbound DRS Ring Transactions to Cache", ++ .code = 0x10, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_bl), ++ .umasks = ivbep_unc_h_txr_bl ++ }, ++ { .name = "UNC_H_TXR_BL_CYCLES_FULL", ++ .desc = "BL Egress Full", ++ .code = 0x36, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_ak_cycles_full), ++ .umasks = ivbep_unc_h_txr_ak_cycles_full, /* identical to snbep_unc_h_txr_ak_cycles_full */ ++ }, ++ { .name = "UNC_H_WPQ_CYCLES_NO_REG_CREDITS", ++ .desc = "HA IMC CHN0 WPQ Credits Empty", ++ .code = 0x18, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_rpq_cycles_no_reg_credits), ++ .umasks = ivbep_unc_h_rpq_cycles_no_reg_credits, /* shared */ ++ }, ++ { .name = "UNC_H_BT_BYPASS", ++ .desc = "Backup Tracker bypass", ++ .code = 0x52, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_BYPASS_IMC", ++ .desc = "HA to IMC bypass", ++ .code = 0x14, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_bypass_imc), ++ .umasks = ivbep_unc_h_bypass_imc, ++ }, ++ { .name = "UNC_H_BT_CYCLES_NE", ++ .desc = "Backup Tracker cycles not empty", ++ .code = 0x42, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_BT_OCCUPANCY", ++ .desc = "Backup Tracker inserts", ++ .code = 0x43, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_bt_occupancy), ++ .umasks = ivbep_unc_h_bt_occupancy, ++ }, ++ { .name = "UNC_H_IGR_AD_QPI2", ++ .desc = "AD QPI Link 2 credit accumulator", ++ .code = 0x59, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_IGR_BL_QPI2", ++ .desc = "BL QPI Link 2 credit accumulator", ++ .code = 0x5a, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_IODC_INSERTS", ++ .desc = "IODC inserts", ++ .code = 0x56, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_IODC_CONFLICTS", ++ .desc = "IODC conflicts", ++ .code = 0x57, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_iodc_conflicts), ++ .umasks = ivbep_unc_h_iodc_conflicts, ++ }, ++ { .name = "UNC_H_IODC_OLEN_WBMTOI", ++ .desc = "IODC zero length writes", ++ .code = 0x58, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ { .name = "UNC_H_OSB", ++ .desc = "OSB snoop broadcast", ++ .code = 0x53, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_osb), ++ .umasks = ivbep_unc_h_osb, ++ }, ++ { .name = "UNC_H_OSB_EDR", ++ .desc = "OSB early data return", ++ .code = 0x54, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_osb_edr), ++ .umasks = ivbep_unc_h_osb_edr, ++ }, ++ { .name = "UNC_H_RING_AD_USED", ++ .desc = "AD ring in use", ++ .code = 0x3e, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), ++ .umasks = ivbep_unc_h_ring_ad_used, ++ }, ++ { .name = "UNC_H_RING_AK_USED", ++ .desc = "AK ring in use", ++ .code = 0x3f, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), /* shared */ ++ .umasks = ivbep_unc_h_ring_ad_used, ++ }, ++ { .name = "UNC_H_RING_BL_USED", ++ .desc = "BL ring in use", ++ .code = 0x40, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_ring_ad_used), /* shared */ ++ .umasks = ivbep_unc_h_ring_ad_used, ++ }, ++ { .name = "UNC_H_DIRECTORY_LAT_OPT", ++ .desc = "Directory latency optimization data return path taken", ++ .code = 0x41, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ }, ++ ++ { .name = "UNC_H_SNP_RESP_RECV_LOCAL", ++ .desc = "Snoop responses received local", ++ .code = 0x60, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_snp_resp_recv_local), ++ .umasks = ivbep_unc_h_snp_resp_recv_local, ++ }, ++ { .name = "UNC_H_TXR_BL_OCCUPANCY", ++ .desc = "BL Egress occupancy", ++ .code = 0x34, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_txr_bl_occupancy), ++ .umasks = ivbep_unc_h_txr_bl_occupancy, ++ }, ++ { .name = "UNC_H_SNOOP_RESP", ++ .desc = "Snoop responses received", ++ .code = 0x21, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_HA_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_h_snoop_resp), ++ .umasks = ivbep_unc_h_snoop_resp ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_imc_events.h b/lib/events/intel_ivbep_unc_imc_events.h +new file mode 100644 +index 0000000..ac8ef41 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_imc_events.h +@@ -0,0 +1,644 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * PMU: ivbep_unc_imc (Intel IvyBridge-EP IMC uncore PMU) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_m_cas_count[]={ ++ { .uname = "ALL", ++ .udesc = "Counts total number of DRAM CAS commands issued on this channel", ++ .ucode = 0xf00, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "RD", ++ .udesc = "Counts all DRAM reads on this channel, incl. underfills", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RD_REG", ++ .udesc = "Counts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit precharge", ++ .ucode = 0x100, ++ }, ++ { .uname = "RD_UNDERFILL", ++ .udesc = "Counts number of underfill reads issued by the memory controller", ++ .ucode = 0x200, ++ }, ++ { .uname = "WR", ++ .udesc = "Counts number of DRAM write CAS commands on this channel", ++ .ucode = 0xc00, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "WR_RMM", ++ .udesc = "Counts Number of opportunistic DRAM write CAS commands issued on this channel", ++ .ucode = 0x800, ++ }, ++ { .uname = "WR_WMM", ++ .udesc = "Counts number of DRAM write CAS commands issued on this channel while in Write-Major mode", ++ .ucode = 0x400, ++ }, ++ { .uname = "RD_RMM", ++ .udesc = "Counts Number of opportunistic DRAM read CAS commands issued on this channel", ++ .ucode = 0x1000, ++ }, ++ { .uname = "RD_WMM", ++ .udesc = "Counts number of DRAM read CAS commands issued on this channel while in Write-Major mode", ++ .ucode = 0x2000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_dram_refresh[]={ ++ { .uname = "HIGH", ++ .udesc = "TBD", ++ .ucode = 0x400, ++ }, ++ { .uname = "PANIC", ++ .udesc = "TBD", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_major_modes[]={ ++ { .uname = "ISOCH", ++ .udesc = "Counts cycles in ISOCH Major maode", ++ .ucode = 0x800, ++ }, ++ { .uname = "PARTIAL", ++ .udesc = "Counts cycles in Partial Major mode", ++ .ucode = 0x400, ++ }, ++ { .uname = "READ", ++ .udesc = "Counts cycles in Read Major mode", ++ .ucode = 0x100, ++ }, ++ { .uname = "WRITE", ++ .udesc = "Counts cycles in Write Major mode", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_power_cke_cycles[]={ ++ { .uname = "RANK0", ++ .udesc = "Count cycles for rank 0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK1", ++ .udesc = "Count cycles for rank 1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK2", ++ .udesc = "Count cycles for rank 2", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK3", ++ .udesc = "Count cycles for rank 3", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK4", ++ .udesc = "Count cycles for rank 4", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK5", ++ .udesc = "Count cycles for rank 5", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK6", ++ .udesc = "Count cycles for rank 6", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RANK7", ++ .udesc = "Count cycles for rank 7", ++ .ucode = 0x8000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_preemption[]={ ++ { .uname = "RD_PREEMPT_RD", ++ .udesc = "Counts read over read preemptions", ++ .ucode = 0x100, ++ }, ++ { .uname = "RD_PREEMPT_WR", ++ .udesc = "Counts read over write preemptions", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_pre_count[]={ ++ { .uname = "PAGE_CLOSE", ++ .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of the page close counter expiring", ++ .ucode = 0x200, ++ }, ++ { .uname = "PAGE_MISS", ++ .udesc = "Counts number of DRAM precharge commands sent on this channel as a result of page misses", ++ .ucode = 0x100, ++ }, ++ { .uname = "RD", ++ .udesc = "Precharge due to read", ++ .ucode = 0x100, ++ }, ++ { .uname = "WR", ++ .udesc = "Precharhe due to write", ++ .ucode = 0x200, ++ }, ++ { .uname = "BYP", ++ .udesc = "Precharge due to bypass", ++ .ucode = 0x800, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_act_count[]={ ++ { .uname = "RD", ++ .udesc = "Activate due to read", ++ .ucode = 0x100, ++ }, ++ { .uname = "WR", ++ .udesc = "Activate due to write", ++ .ucode = 0x200, ++ }, ++ { .uname = "BYP", ++ .udesc = "Activate due to bypass", ++ .ucode = 0x800, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_byp_cmds[]={ ++ { .uname = "ACT", ++ .udesc = "ACT command issued by 2 cycle bypass", ++ .ucode = 0x100, ++ }, ++ { .uname = "CAS", ++ .udesc = "CAS command issued by 2 cycle bypass", ++ .ucode = 0x200, ++ }, ++ { .uname = "PRE", ++ .udesc = "PRE command issued by 2 cycle bypass", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_rd_cas_prio[]={ ++ { .uname = "LOW", ++ .udesc = "Read CAS issued with low priority", ++ .ucode = 0x100, ++ }, ++ { .uname = "MED", ++ .udesc = "Read CAS issued with medium priority", ++ .ucode = 0x200, ++ }, ++ { .uname = "HIGH", ++ .udesc = "Read CAS issued with high priority", ++ .ucode = 0x400, ++ }, ++ { .uname = "PANIC", ++ .udesc = "Read CAS issued with panic non isoch priority (starved)", ++ .ucode = 0x800, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_rd_cas_rank0[]={ ++ { .uname = "BANK0", ++ .udesc = "Bank 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "BANK1", ++ .udesc = "Bank 1", ++ .ucode = 0x200, ++ }, ++ { .uname = "BANK2", ++ .udesc = "Bank 2", ++ .ucode = 0x400, ++ }, ++ { .uname = "BANK3", ++ .udesc = "Bank 3", ++ .ucode = 0x800, ++ }, ++ { .uname = "BANK4", ++ .udesc = "Bank 4", ++ .ucode = 0x1000, ++ }, ++ { .uname = "BANK5", ++ .udesc = "Bank 5", ++ .ucode = 0x2000, ++ }, ++ { .uname = "BANK6", ++ .udesc = "Bank 6", ++ .ucode = 0x4000, ++ }, ++ { .uname = "BANK7", ++ .udesc = "Bank 7", ++ .ucode = 0x8000, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_vmse_wr_push[]={ ++ { .uname = "WMM", ++ .udesc = "VMSE write push issued in WMM", ++ .ucode = 0x100, ++ }, ++ { .uname = "RMM", ++ .udesc = "VMSE write push issued in RMM", ++ .ucode = 0x200, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_m_wmm_to_rmm[]={ ++ { .uname = "LOW_THRES", ++ .udesc = "Transition from WMM to RMM because of starve counter", ++ .ucode = 0x100, ++ }, ++ { .uname = "STARVE", ++ .udesc = "TBD", ++ .ucode = 0x200, ++ }, ++ { .uname = "VMSE_RETRY", ++ .udesc = "TBD", ++ .ucode = 0x400, ++ } ++}; ++ ++ ++static const intel_x86_entry_t intel_ivbep_unc_m_pe[]={ ++ { .name = "UNC_M_CLOCKTICKS", ++ .desc = "IMC Uncore clockticks (fixed counter)", ++ .modmsk = 0x0, ++ .cntmsk = 0x100000000ull, ++ .code = 0xff, /* perf pseudo encoding for fixed counter */ ++ .flags = INTEL_X86_FIXED, ++ }, ++ { .name = "UNC_M_DCLOCKTICKS", ++ .desc = "IMC Uncore clockticks (generic counters)", ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .cntmsk = 0xf, ++ .code = 0x00, /*encoding for generic counters */ ++ }, ++ { .name = "UNC_M_ACT_COUNT", ++ .desc = "DRAM Activate Count", ++ .code = 0x1, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_act_count), ++ .umasks = ivbep_unc_m_act_count ++ }, ++ { .name = "UNC_M_CAS_COUNT", ++ .desc = "DRAM RD_CAS and WR_CAS Commands.", ++ .code = 0x4, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_cas_count), ++ .umasks = ivbep_unc_m_cas_count ++ }, ++ { .name = "UNC_M_DRAM_PRE_ALL", ++ .desc = "DRAM Precharge All Commands", ++ .code = 0x6, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_DRAM_REFRESH", ++ .desc = "Number of DRAM Refreshes Issued", ++ .code = 0x5, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_dram_refresh), ++ .umasks = ivbep_unc_m_dram_refresh ++ }, ++ { .name = "UNC_M_ECC_CORRECTABLE_ERRORS", ++ .desc = "ECC Correctable Errors", ++ .code = 0x9, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_MAJOR_MODES", ++ .desc = "Cycles in a Major Mode", ++ .code = 0x7, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_major_modes), ++ .umasks = ivbep_unc_m_major_modes ++ }, ++ { .name = "UNC_M_POWER_CHANNEL_DLLOFF", ++ .desc = "Channel DLLOFF Cycles", ++ .code = 0x84, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_POWER_CHANNEL_PPD", ++ .desc = "Channel PPD Cycles", ++ .code = 0x85, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_POWER_CKE_CYCLES", ++ .desc = "CKE_ON_CYCLES by Rank", ++ .code = 0x83, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_power_cke_cycles), ++ .umasks = ivbep_unc_m_power_cke_cycles ++ }, ++ { .name = "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", ++ .desc = "Critical Throttle Cycles", ++ .code = 0x86, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_POWER_SELF_REFRESH", ++ .desc = "Clock-Enabled Self-Refresh", ++ .code = 0x43, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_POWER_THROTTLE_CYCLES", ++ .desc = "Throttle Cycles", ++ .code = 0x41, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_power_cke_cycles), ++ .umasks = ivbep_unc_m_power_cke_cycles /* identical to snbep_unc_m_power_cke_cycles */ ++ }, ++ { .name = "UNC_M_PREEMPTION", ++ .desc = "Read Preemption Count", ++ .code = 0x8, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_preemption), ++ .umasks = ivbep_unc_m_preemption ++ }, ++ { .name = "UNC_M_PRE_COUNT", ++ .desc = "DRAM Precharge commands.", ++ .code = 0x2, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_pre_count), ++ .umasks = ivbep_unc_m_pre_count ++ }, ++ { .name = "UNC_M_RPQ_CYCLES_NE", ++ .desc = "Read Pending Queue Not Empty", ++ .code = 0x11, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_RPQ_INSERTS", ++ .desc = "Read Pending Queue Allocations", ++ .code = 0x10, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WPQ_CYCLES_FULL", ++ .desc = "Write Pending Queue Full Cycles", ++ .code = 0x22, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WPQ_CYCLES_NE", ++ .desc = "Write Pending Queue Not Empty", ++ .code = 0x21, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WPQ_INSERTS", ++ .desc = "Write Pending Queue Allocations", ++ .code = 0x20, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WPQ_READ_HIT", ++ .desc = "Write Pending Queue CAM Match", ++ .code = 0x23, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WPQ_WRITE_HIT", ++ .desc = "Write Pending Queue CAM Match", ++ .code = 0x24, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_BYP_CMDS", ++ .desc = "Bypass command event", ++ .code = 0xa1, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_byp_cmds), ++ .umasks = ivbep_unc_m_byp_cmds ++ }, ++ { .name = "UNC_M_RD_CAS_PRIO", ++ .desc = "Read CAS priority", ++ .code = 0xa0, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_prio), ++ .umasks = ivbep_unc_m_rd_cas_prio ++ }, ++ { .name = "UNC_M_RD_CAS_RANK0", ++ .desc = "Read CAS access to Rank 0", ++ .code = 0xb0, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK1", ++ .desc = "Read CAS access to Rank 1", ++ .code = 0xb1, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK2", ++ .desc = "Read CAS access to Rank 2", ++ .code = 0xb2, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK3", ++ .desc = "Read CAS access to Rank 3", ++ .code = 0xb3, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK4", ++ .desc = "Read CAS access to Rank 4", ++ .code = 0xb4, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK5", ++ .desc = "Read CAS access to Rank 5", ++ .code = 0xb5, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK6", ++ .desc = "Read CAS access to Rank 6", ++ .code = 0xb6, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_RD_CAS_RANK7", ++ .desc = "Read CAS access to Rank 7", ++ .code = 0xb7, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_VMSE_MXB_WR_OCCUPANCY", ++ .desc = "VMSE MXB write buffer occupancy", ++ .code = 0x91, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_VMSE_WR_PUSH", ++ .desc = "VMSE WR push issued", ++ .code = 0x90, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_vmse_wr_push), ++ .umasks = ivbep_unc_m_vmse_wr_push ++ }, ++ { .name = "UNC_M_WMM_TO_RMM", ++ .desc = "Transitions from WMM to RMM because of low threshold", ++ .code = 0xc0, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_wmm_to_rmm), ++ .umasks = ivbep_unc_m_wmm_to_rmm ++ }, ++ { .name = "UNC_M_WRONG_MM", ++ .desc = "Not getting the requested major mode", ++ .code = 0xc1, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ }, ++ { .name = "UNC_M_WR_CAS_RANK0", ++ .desc = "Write CAS access to Rank 0", ++ .code = 0xb8, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK1", ++ .desc = "Write CAS access to Rank 1", ++ .code = 0xb9, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK2", ++ .desc = "Write CAS access to Rank 2", ++ .code = 0xba, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK3", ++ .desc = "Write CAS access to Rank 3", ++ .code = 0xbb, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK4", ++ .desc = "Write CAS access to Rank 4", ++ .code = 0xbc, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK5", ++ .desc = "Write CAS access to Rank 5", ++ .code = 0xbd, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK6", ++ .desc = "Write CAS access to Rank 6", ++ .code = 0xbe, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++ { .name = "UNC_M_WR_CAS_RANK7", ++ .desc = "Write CAS access to Rank 7", ++ .code = 0xbf, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_IMC_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_m_rd_cas_rank0), /* shared */ ++ .umasks = ivbep_unc_m_rd_cas_rank0 ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_irp_events.h b/lib/events/intel_ivbep_unc_irp_events.h +new file mode 100644 +index 0000000..86b5168 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_irp_events.h +@@ -0,0 +1,267 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * This file has been automatically generated. ++ * ++ * PMU: ivbep_unc_irp (Intel IvyBridge-EP IRP uncore) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_i_address_match[]={ ++ { .uname = "STALL_COUNT", ++ .udesc = "Number of time when it is not possible to merge two conflicting requests, a stall event occurs", ++ .ucode = 0x100, ++ }, ++ { .uname = "MERGE_COUNT", ++ .udesc = "Number of times when two reuqests to the same address from the same source are received back to back, it is possible to merge them", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_i_cache_ack_pending_occupancy[]={ ++ { .uname = "ANY", ++ .udesc = "Any source", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++ { .uname = "SOURCE", ++ .udesc = "Track all requests from any source port", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_i_tickles[]={ ++ { .uname = "LOST_OWNERSHIP", ++ .udesc = "Number of request that lost ownership as a result of a tickle", ++ .ucode = 0x100, ++ }, ++ { .uname = "TOP_OF_QUEUE", ++ .udesc = "Number of cases when a tickle was received but the request was at the head of the queue in the switch. In this case data is returned rather than releasing ownership", ++ .ucode = 0x200, ++ }, ++}; ++ ++ ++static const intel_x86_umask_t ivbep_unc_i_transactions[]={ ++ { .uname = "READS", ++ .udesc = "Number of read requests (not including read prefetches)", ++ .ucode = 0x100, ++ }, ++ { .uname = "WRITES", ++ .udesc = "Number of write requests. Each write should have a prefetch, so there is no need to explicitly track these requests", ++ .ucode = 0x200, ++ }, ++ { .uname = "RD_PREFETCHES", ++ .udesc = "Number of read prefetches", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_i_pe[]={ ++ { .name = "UNC_I_CLOCKTICKS", ++ .desc = "Number of uclks in domain", ++ .code = 0x0, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_ADDRESS_MATCH", ++ .desc = "Address match conflict count", ++ .code = 0x17, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_address_match), ++ .umasks = ivbep_unc_i_address_match ++ }, ++ { .name = "UNC_I_CACHE_ACK_PENDING_OCCUPANCY", ++ .desc = "Write ACK pending occupancy", ++ .code = 0x14, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), ++ .umasks = ivbep_unc_i_cache_ack_pending_occupancy ++ }, ++ { .name = "UNC_I_CACHE_OWN_OCCUPANCY", ++ .desc = "Outstanding write ownership occupancy", ++ .code = 0x13, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), ++ .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ ++ }, ++ { .name = "UNC_I_CACHE_READ_OCCUPANCY", ++ .desc = "Outstanding read occupancy", ++ .code = 0x10, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), ++ .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ ++ }, ++ { .name = "UNC_I_CACHE_TOTAL_OCCUPANCY", ++ .desc = "Total write cache occupancy", ++ .code = 0x12, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), ++ .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ ++ }, ++ { .name = "UNC_I_CACHE_WRITE_OCCUPANCY", ++ .desc = "Outstanding write occupancy", ++ .code = 0x11, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_cache_ack_pending_occupancy), ++ .umasks = ivbep_unc_i_cache_ack_pending_occupancy /* shared */ ++ }, ++ { .name = "UNC_I_RXR_AK_CYCLES_FULL", ++ .desc = "TBD", ++ .code = 0xb, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_AK_INSERTS", ++ .desc = "Egress cycles full", ++ .code = 0xa, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_AK_OCCUPANCY", ++ .desc = "TBD", ++ .code = 0x0c, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_DRS_CYCLES_FULL", ++ .desc = "TBD", ++ .code = 0x4, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_DRS_INSERTS", ++ .desc = "BL Ingress occupancy DRS", ++ .code = 0x1, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_DRS_OCCUPANCY", ++ .desc = "TBD", ++ .code = 0x7, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCB_CYCLES_FULL", ++ .desc = "TBD", ++ .code = 0x5, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCB_INSERTS", ++ .desc = "BL Ingress occupancy NCB", ++ .code = 0x2, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCB_OCCUPANCY", ++ .desc = "TBD", ++ .code = 0x8, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCS_CYCLES_FULL", ++ .desc = "TBD", ++ .code = 0x6, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCS_INSERTS", ++ .desc = "BL Ingress Occupancy NCS", ++ .code = 0x3, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_RXR_BL_NCS_OCCUPANCY", ++ .desc = "TBD", ++ .code = 0x9, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_TICKLES", ++ .desc = "Tickle count", ++ .code = 0x16, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_tickles), ++ .umasks = ivbep_unc_i_tickles ++ }, ++ { .name = "UNC_I_TRANSACTIONS", ++ .desc = "Inbound transaction count", ++ .code = 0x15, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_i_transactions), ++ .umasks = ivbep_unc_i_transactions ++ }, ++ { .name = "UNC_I_TXR_AD_STALL_CREDIT_CYCLES", ++ .desc = "No AD Egress credit stalls", ++ .code = 0x18, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_TXR_BL_STALL_CREDIT_CYCLES", ++ .desc = "No BL Egress credit stalls", ++ .code = 0x19, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_TXR_DATA_INSERTS_NCB", ++ .desc = "Outbound read requests", ++ .code = 0xe, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_TXR_DATA_INSERTS_NCS", ++ .desc = "Outbound read requests", ++ .code = 0xf, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_TXR_REQUEST_OCCUPANCY", ++ .desc = "Outbound request queue occupancy", ++ .code = 0xd, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++ { .name = "UNC_I_WRITE_ORDERING_STALL_CYCLES", ++ .desc = "Write ordering stalls", ++ .code = 0x1a, ++ .cntmsk = 0x3, ++ .modmsk = SNBEP_UNC_IRP_ATTRS, ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_pcu_events.h b/lib/events/intel_ivbep_unc_pcu_events.h +new file mode 100644 +index 0000000..14188e5 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_pcu_events.h +@@ -0,0 +1,485 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * PMU: ivbep_unc_pcu (Intel IvyBridge-EP PCU uncore) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_p_power_state_occupancy[]={ ++ { .uname = "CORES_C0", ++ .udesc = "Counts number of cores in C0", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CORES_C3", ++ .udesc = "Counts number of cores in C3", ++ .ucode = 0x8000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CORES_C6", ++ .udesc = "Counts number of cores in C6", ++ .ucode = 0xc000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_p_occupancy_counters[]={ ++ { .uname = "C0", ++ .udesc = "Counts number of cores in C0", ++ .ucode = 0x0100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "C3", ++ .udesc = "Counts number of cores in C3", ++ .ucode = 0x0200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "C6", ++ .udesc = "Counts number of cores in C6", ++ .ucode = 0x0300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_p_pe[]={ ++ { .name = "UNC_P_CLOCKTICKS", ++ .desc = "PCU Uncore clockticks", ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ .cntmsk = 0xf, ++ .code = 0x00, ++ }, ++ { .name = "UNC_P_CORE0_TRANSITION_CYCLES", ++ .desc = "Core 0 C State Transition Cycles", ++ .code = 0x70, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE1_TRANSITION_CYCLES", ++ .desc = "Core 1 C State Transition Cycles", ++ .code = 0x71, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE2_TRANSITION_CYCLES", ++ .desc = "Core 2 C State Transition Cycles", ++ .code = 0x72, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE3_TRANSITION_CYCLES", ++ .desc = "Core 3 C State Transition Cycles", ++ .code = 0x73, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE4_TRANSITION_CYCLES", ++ .desc = "Core 4 C State Transition Cycles", ++ .code = 0x74, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE5_TRANSITION_CYCLES", ++ .desc = "Core 5 C State Transition Cycles", ++ .code = 0x75, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE6_TRANSITION_CYCLES", ++ .desc = "Core 6 C State Transition Cycles", ++ .code = 0x76, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE7_TRANSITION_CYCLES", ++ .desc = "Core 7 C State Transition Cycles", ++ .code = 0x77, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE8_TRANSITION_CYCLES", ++ .desc = "Core 8 C State Transition Cycles", ++ .code = 0x78, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE9_TRANSITION_CYCLES", ++ .desc = "Core 9 C State Transition Cycles", ++ .code = 0x79, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE10_TRANSITION_CYCLES", ++ .desc = "Core 10 C State Transition Cycles", ++ .code = 0x7a, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE11_TRANSITION_CYCLES", ++ .desc = "Core 11 C State Transition Cycles", ++ .code = 0x7b, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE12_TRANSITION_CYCLES", ++ .desc = "Core 12 C State Transition Cycles", ++ .code = 0x7c, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE13_TRANSITION_CYCLES", ++ .desc = "Core 13 C State Transition Cycles", ++ .code = 0x7d, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_CORE14_TRANSITION_CYCLES", ++ .desc = "Core 14 C State Transition Cycles", ++ .code = 0x7e, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE0", ++ .desc = "Deep C state rejection Core 0", ++ .code = 0x17 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE1", ++ .desc = "Deep C state rejection Core 1", ++ .code = 0x18 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE2", ++ .desc = "Deep C state rejection Core 2", ++ .code = 0x19 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE3", ++ .desc = "Deep C state rejection Core 3", ++ .code = 0x1a | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE4", ++ .desc = "Deep C state rejection Core 4", ++ .code = 0x1b | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE5", ++ .desc = "Deep C state rejection Core 5", ++ .code = 0x1c | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE6", ++ .desc = "Deep C state rejection Core 6", ++ .code = 0x1d | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE7", ++ .desc = "Deep C state rejection Core 7", ++ .code = 0x1e | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE8", ++ .desc = "Deep C state rejection Core 8", ++ .code = 0x1f | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE9", ++ .desc = "Deep C state rejection Core 9", ++ .code = 0x20 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE10", ++ .desc = "Deep C state rejection Core 10", ++ .code = 0x21 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE11", ++ .desc = "Deep C state rejection Core 11", ++ .code = 0x22 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE12", ++ .desc = "Deep C state rejection Core 12", ++ .code = 0x23 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE13", ++ .desc = "Deep C state rejection Core 13", ++ .code = 0x24 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE14", ++ .desc = "Deep C state rejection Core 14", ++ .code = 0x25 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE0", ++ .desc = "Core 0 C State Demotions", ++ .code = 0x1e, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE1", ++ .desc = "Core 1 C State Demotions", ++ .code = 0x1f, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE2", ++ .desc = "Core 2 C State Demotions", ++ .code = 0x20, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE3", ++ .desc = "Core 3 C State Demotions", ++ .code = 0x21, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE4", ++ .desc = "Core 4 C State Demotions", ++ .code = 0x22, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE5", ++ .desc = "Core 5 C State Demotions", ++ .code = 0x23, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE6", ++ .desc = "Core 6 C State Demotions", ++ .code = 0x24, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE7", ++ .desc = "Core 7 C State Demotions", ++ .code = 0x25, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE8", ++ .desc = "Core 8 C State Demotions", ++ .code = 0x40, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE9", ++ .desc = "Core 9 C State Demotions", ++ .code = 0x41, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE10", ++ .desc = "Core 10 C State Demotions", ++ .code = 0x42, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE11", ++ .desc = "Core 11 C State Demotions", ++ .code = 0x43, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE12", ++ .desc = "Core 12 C State Demotions", ++ .code = 0x44, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE13", ++ .desc = "Core 13 C State Demotions", ++ .code = 0x45, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE14", ++ .desc = "Core 14 C State Demotions", ++ .code = 0x46, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_DEMOTIONS_CORE14", ++ .desc = "Core 14 C State Demotions", ++ .code = 0x2d, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_BAND0_CYCLES", ++ .desc = "Frequency Residency", ++ .code = 0xb, ++ .cntmsk = 0xf, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, ++ .modmsk_req = _SNBEP_UNC_ATTR_FF, ++ }, ++ { .name = "UNC_P_FREQ_BAND1_CYCLES", ++ .desc = "Frequency Residency", ++ .code = 0xc, ++ .cntmsk = 0xf, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, ++ .modmsk_req = _SNBEP_UNC_ATTR_FF, ++ }, ++ { .name = "UNC_P_FREQ_BAND2_CYCLES", ++ .desc = "Frequency Residency", ++ .code = 0xd, ++ .cntmsk = 0xf, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, ++ .modmsk_req = _SNBEP_UNC_ATTR_FF, ++ }, ++ { .name = "UNC_P_FREQ_BAND3_CYCLES", ++ .desc = "Frequency Residency", ++ .code = 0xe, ++ .cntmsk = 0xf, ++ .flags = INTEL_X86_NO_AUTOENCODE, ++ .modmsk = IVBEP_UNC_PCU_BAND_ATTRS, ++ .modmsk_req = _SNBEP_UNC_ATTR_FF, ++ }, ++ { .name = "UNC_P_FREQ_MAX_CURRENT_CYCLES", ++ .desc = "Current Strongest Upper Limit Cycles", ++ .code = 0x7, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", ++ .desc = "Thermal Strongest Upper Limit Cycles", ++ .code = 0x4, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_MAX_OS_CYCLES", ++ .desc = "OS Strongest Upper Limit Cycles", ++ .code = 0x6, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", ++ .desc = "Power Strongest Upper Limit Cycles", ++ .code = 0x5, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_MIN_PERF_P_CYCLES", ++ .desc = "Perf P Limit Strongest Lower Limit Cycles", ++ .code = 0x02 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ ++ { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", ++ .desc = "IO P Limit Strongest Lower Limit Cycles", ++ .code = 0x61, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_FREQ_TRANS_CYCLES", ++ .desc = "Cycles spent changing Frequency", ++ .code = 0x60, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", ++ .desc = "Memory Phase Shedding Cycles", ++ .code = 0x2f, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_PKG_C_EXIT_LATENCY", ++ .desc = "Package C state exit latency. Counts cycles the package is transitioning from C2 to C3", ++ .code = 0x26 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_POWER_STATE_OCCUPANCY", ++ .desc = "Number of cores in C0", ++ .code = 0x80, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_p_power_state_occupancy), ++ .umasks = ivbep_unc_p_power_state_occupancy ++ }, ++ { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", ++ .desc = "External Prochot", ++ .code = 0xa, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", ++ .desc = "Internal Prochot", ++ .code = 0x9, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", ++ .desc = "Total Core C State Transition Cycles", ++ .code = 0x63, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_VOLT_TRANS_CYCLES_CHANGE", ++ .desc = "Cycles Changing Voltage", ++ .code = 0x3, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_VOLT_TRANS_CYCLES_DECREASE", ++ .desc = "Cycles Decreasing Voltage", ++ .code = 0x2, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_VOLT_TRANS_CYCLES_INCREASE", ++ .desc = "Cycles Increasing Voltage", ++ .code = 0x1, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++ { .name = "UNC_P_VR_HOT_CYCLES", ++ .desc = "VR Hot", ++ .code = 0x32, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_PCU_ATTRS, ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_qpi_events.h b/lib/events/intel_ivbep_unc_qpi_events.h +new file mode 100644 +index 0000000..cfb3469 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_qpi_events.h +@@ -0,0 +1,696 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * This file has been automatically generated. ++ * ++ * PMU: ivbep_unc_qpi (Intel IvyBridge-EP QPI uncore) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_q_direct2core[]={ ++ { .uname = "FAILURE_CREDITS", ++ .udesc = "Number of spawn failures due to lack of Egress credits", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_CREDITS_RBT", ++ .udesc = "Number of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not set", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_RBT_HIT", ++ .udesc = "Number of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transaction", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SUCCESS_RBT_HIT", ++ .udesc = "Number of spawn successes", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_MISS", ++ .udesc = "Number of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress credits", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_CREDITS_MISS", ++ .udesc = "Number of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was set", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_RBT_MISS", ++ .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress credits", ++ .ucode = 0x4000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "FAILURE_CREDITS_RBT_MISS", ++ .udesc = "Number of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress credits", ++ .ucode = 0x8000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_rxl_credits_consumed_vn0[]={ ++ { .uname = "DRS", ++ .udesc = "Number of times VN0 consumed for DRS message class", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "HOM", ++ .udesc = "Number of times VN0 consumed for HOM message class", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCB", ++ .udesc = "Number of times VN0 consumed for NCB message class", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCS", ++ .udesc = "Number of times VN0 consumed for NCS message class", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NDR", ++ .udesc = "Number of times VN0 consumed for NDR message class", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SNP", ++ .udesc = "Number of times VN0 consumed for SNP message class", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_rxl_credits_consumed_vn1[]={ ++ { .uname = "DRS", ++ .udesc = "Number of times VN1 consumed for DRS message class", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "HOM", ++ .udesc = "Number of times VN1 consumed for HOM message class", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCB", ++ .udesc = "Number of times VN1 consumed for NCB message class", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCS", ++ .udesc = "Number of times VN1 consumed for NCS message class", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NDR", ++ .udesc = "Number of times VN1 consumed for NDR message class", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SNP", ++ .udesc = "Number of times VN1 consumed for SNP message class", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++ ++static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g0[]={ ++ { .uname = "DATA", ++ .udesc = "Number of data flits over QPI", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IDLE", ++ .udesc = "Number of flits over QPI that do not hold protocol payload", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NON_DATA", ++ .udesc = "Number of non-NULL non-data flits over QPI", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_txl_flits_g0[]={ ++ { .uname = "DATA", ++ .udesc = "Number of data flits over QPI", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NON_DATA", ++ .udesc = "Number of non-NULL non-data flits over QPI", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g1[]={ ++ { .uname = "DRS", ++ .udesc = "Number of flits over QPI on the Data Response (DRS) channel", ++ .ucode = 0x1800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "DRS_DATA", ++ .udesc = "Number of data flits over QPI on the Data Response (DRS) channel", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "DRS_NONDATA", ++ .udesc = "Number of protocol flits over QPI on the Data Response (DRS) channel", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "HOM", ++ .udesc = "Number of flits over QPI on the home channel", ++ .ucode = 0x600, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "HOM_NONREQ", ++ .udesc = "Number of non-request flits over QPI on the home channel", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "HOM_REQ", ++ .udesc = "Number of data requests over QPI on the home channel", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "SNP", ++ .udesc = "Number of snoop requests flits over QPI", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_rxl_flits_g2[]={ ++ { .uname = "NCB", ++ .udesc = "Number of non-coherent bypass flits", ++ .ucode = 0xc00, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCB_DATA", ++ .udesc = "Number of non-coherent data flits", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCB_NONDATA", ++ .udesc = "Number of bypass non-data flits", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCS", ++ .udesc = "Number of non-coherent standard (NCS) flits", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NDR_AD", ++ .udesc = "Number of flits received over Non-data response (NDR) channel", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NDR_AK", ++ .udesc = "Number of flits received on the Non-data response (NDR) channel)", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_q_txr_ad_hom_credit_acquired[]={ ++ { .uname = "VN0", ++ .udesc = "for VN0", ++ .ucode = 0x100, ++ }, ++ { .uname = "VN1", ++ .udesc = "for VN1", ++ .ucode = 0x200, ++ }, ++}; ++ ++ static const intel_x86_umask_t ivbep_unc_q_txr_bl_drs_credit_acquired[]={ ++ { .uname = "VN0", ++ .udesc = "for VN0", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "VN1", ++ .udesc = "for VN1", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "VN_SHR", ++ .udesc = "for shared VN", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_q_pe[]={ ++ { .name = "UNC_Q_CLOCKTICKS", ++ .desc = "Number of qfclks", ++ .code = 0x14, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_CTO_COUNT", ++ .desc = "Count of CTO Events", ++ .code = 0x38 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_DIRECT2CORE", ++ .desc = "Direct 2 Core Spawning", ++ .code = 0x13, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_direct2core), ++ .umasks = ivbep_unc_q_direct2core ++ }, ++ { .name = "UNC_Q_L1_POWER_CYCLES", ++ .desc = "Cycles in L1", ++ .code = 0x12, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL0P_POWER_CYCLES", ++ .desc = "Cycles in L0p", ++ .code = 0x10, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL0_POWER_CYCLES", ++ .desc = "Cycles in L0", ++ .code = 0xf, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_BYPASSED", ++ .desc = "Rx Flit Buffer Bypassed", ++ .code = 0x9, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN0", ++ .desc = "VN0 Credit Consumed", ++ .code = 0x1e | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_credits_consumed_vn0), ++ .umasks = ivbep_unc_q_rxl_credits_consumed_vn0 ++ }, ++ { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VN1", ++ .desc = "VN1 Credit Consumed", ++ .code = 0x39 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_credits_consumed_vn1), ++ .umasks = ivbep_unc_q_rxl_credits_consumed_vn1 ++ }, ++ { .name = "UNC_Q_RXL_CREDITS_CONSUMED_VNA", ++ .desc = "VNA Credit Consumed", ++ .code = 0x1d | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_CYCLES_NE", ++ .desc = "RxQ Cycles Not Empty", ++ .code = 0xa, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_FLITS_G0", ++ .desc = "Flits Received - Group 0", ++ .code = 0x1, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g0), ++ .umasks = ivbep_unc_q_rxl_flits_g0 ++ }, ++ { .name = "UNC_Q_RXL_FLITS_G1", ++ .desc = "Flits Received - Group 1", ++ .code = 0x2 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g1), ++ .umasks = ivbep_unc_q_rxl_flits_g1 ++ }, ++ ++ { .name = "UNC_Q_RXL_FLITS_G2", ++ .desc = "Flits Received - Group 2", ++ .code = 0x3 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g2), ++ .umasks = ivbep_unc_q_rxl_flits_g2 ++ }, ++ { .name = "UNC_Q_RXL_INSERTS", ++ .desc = "Rx Flit Buffer Allocations", ++ .code = 0x8, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_DRS", ++ .desc = "Rx Flit Buffer Allocations - DRS", ++ .code = 0x9 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_HOM", ++ .desc = "Rx Flit Buffer Allocations - HOM", ++ .code = 0xc | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_NCB", ++ .desc = "Rx Flit Buffer Allocations - NCB", ++ .code = 0xa | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_NCS", ++ .desc = "Rx Flit Buffer Allocations - NCS", ++ .code = 0xb | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_NDR", ++ .desc = "Rx Flit Buffer Allocations - NDR", ++ .code = 0xe | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_INSERTS_SNP", ++ .desc = "Rx Flit Buffer Allocations - SNP", ++ .code = 0xd | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY", ++ .desc = "RxQ Occupancy - All Packets", ++ .code = 0xb, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_DRS", ++ .desc = "RxQ Occupancy - DRS", ++ .code = 0x15 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_HOM", ++ .desc = "RxQ Occupancy - HOM", ++ .code = 0x18 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_NCB", ++ .desc = "RxQ Occupancy - NCB", ++ .code = 0x16 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_NCS", ++ .desc = "RxQ Occupancy - NCS", ++ .code = 0x17 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_NDR", ++ .desc = "RxQ Occupancy - NDR", ++ .code = 0x1a | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_RXL_OCCUPANCY_SNP", ++ .desc = "RxQ Occupancy - SNP", ++ .code = 0x19 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXL0P_POWER_CYCLES", ++ .desc = "Cycles in L0p", ++ .code = 0xd, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXL0_POWER_CYCLES", ++ .desc = "Cycles in L0", ++ .code = 0xc, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXL_BYPASSED", ++ .desc = "Tx Flit Buffer Bypassed", ++ .code = 0x5, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXL_CYCLES_NE", ++ .desc = "Tx Flit Buffer Cycles not Empty", ++ .code = 0x6, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXL_FLITS_G0", ++ .desc = "Flits Transferred - Group 0", ++ .code = 0x0, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txl_flits_g0), ++ .umasks = ivbep_unc_q_txl_flits_g0 ++ }, ++ { .name = "UNC_Q_TXL_FLITS_G1", ++ .desc = "Flits Transferred - Group 1", ++ .code = 0x0 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g1), ++ .umasks = ivbep_unc_q_rxl_flits_g1 /* shared with rxl_flits_g1 */ ++ }, ++ { .name = "UNC_Q_TXL_FLITS_G2", ++ .desc = "Flits Transferred - Group 2", ++ .code = 0x1 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_rxl_flits_g2), ++ .umasks = ivbep_unc_q_rxl_flits_g2 /* shared with rxl_flits_g2 */ ++ }, ++ { .name = "UNC_Q_TXL_INSERTS", ++ .desc = "Tx Flit Buffer Allocations", ++ .code = 0x4, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXL_OCCUPANCY", ++ .desc = "Tx Flit Buffer Occupancy", ++ .code = 0x7, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_VNA_CREDIT_RETURNS", ++ .desc = "VNA Credits Returned", ++ .code = 0x1c | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", ++ .desc = "VNA Credits Pending Return - Occupancy", ++ .code = 0x1b | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ }, ++ { .name = "UNC_Q_TXR_AD_HOM_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy AD HOM", ++ .code = 0x26 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy AD HOM", ++ .code = 0x22 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AD_NDR_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy AD NDR", ++ .code = 0x28 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy AD NDR", ++ .code = 0x24 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AD_SNP_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy AD SNP", ++ .code = 0x27 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy AD SNP", ++ .code = 0x23 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AK_NDR_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy AK NDR", ++ .code = 0x29 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy AD NDR", ++ .code = 0x25 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_DRS_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy BL DRS", ++ .code = 0x2a | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_bl_drs_credit_acquired), ++ .umasks = ivbep_unc_q_txr_bl_drs_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy BL DRS", ++ .code = 0x1f | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_bl_drs_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_bl_drs_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_NCB_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy BL NCB", ++ .code = 0x2b | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy BL NCB", ++ .code = 0x20 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_NCS_CREDIT_ACQUIRED", ++ .desc = "R3QPI Egress credit occupancy BL NCS", ++ .code = 0x2c | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++ { .name = "UNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY", ++ .desc = "R3QPI Egress credit occupancy BL NCS", ++ .code = 0x21 | (1ULL << 21), /* sel_ext */ ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_q_txr_ad_hom_credit_acquired), /* shared */ ++ .umasks = ivbep_unc_q_txr_ad_hom_credit_acquired, ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_r2pcie_events.h b/lib/events/intel_ivbep_unc_r2pcie_events.h +new file mode 100644 +index 0000000..59d96b9 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_r2pcie_events.h +@@ -0,0 +1,253 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * This file has been automatically generated. ++ * ++ * PMU: ivbep_unc_r2pcie (Intel IvyBridge-EP R2PCIe uncore) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_r2_ring_ad_used[]={ ++ { .uname = "CCW_VR0_EVEN", ++ .udesc = "Counter-clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x400, ++ }, ++ { .uname = "CCW_VR0_ODD", ++ .udesc = "Counter-clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x800, ++ }, ++ { .uname = "CW_VR0_EVEN", ++ .udesc = "Clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "CW_VR0_ODD", ++ .udesc = "Clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x200, ++ }, ++ { .uname = "CCW_VR1_EVEN", ++ .udesc = "Counter-clockwise and even ring polarity on virtual ring 1", ++ .ucode = 0x400, ++ }, ++ { .uname = "CCW_VR1_ODD", ++ .udesc = "Counter-clockwise and odd ring polarity on virtual ring 1", ++ .ucode = 0x800, ++ }, ++ { .uname = "CW_VR1_EVEN", ++ .udesc = "Clockwise and even ring polarity on virtual ring 1", ++ .ucode = 0x100, ++ }, ++ { .uname = "CW_VR1_ODD", ++ .udesc = "Clockwise and odd ring polarity on virtual ring 1", ++ .ucode = 0x200, ++ }, ++ { .uname = "CW", ++ .udesc = "Clockwise with any polarity on either virtual rings", ++ .ucode = 0x3300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xcc00, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r2_rxr_ak_bounces[]={ ++ { .uname = "CW", ++ .udesc = "Clockwise", ++ .ucode = 0x100, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r2_rxr_occupancy[]={ ++ { .uname = "DRS", ++ .udesc = "DRS Ingress queue", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_DFL, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r2_ring_iv_used[]={ ++ { .uname = "CW", ++ .udesc = "Clockwise with any polarity on either virtual rings", ++ .ucode = 0x3300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xcc00, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ANY", ++ .udesc = "any direction and any polarity on any virtual ring", ++ .ucode = 0xff00, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r2_rxr_cycles_ne[]={ ++ { .uname = "NCB", ++ .udesc = "NCB Ingress queue", ++ .ucode = 0x1000, ++ }, ++ { .uname = "NCS", ++ .udesc = "NCS Ingress queue", ++ .ucode = 0x2000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r2_txr_cycles_full[]={ ++ { .uname = "AD", ++ .udesc = "AD Egress queue", ++ .ucode = 0x100, ++ }, ++ { .uname = "AK", ++ .udesc = "AK Egress queue", ++ .ucode = 0x200, ++ }, ++ { .uname = "BL", ++ .udesc = "BL Egress queue", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_r2_pe[]={ ++ { .name = "UNC_R2_CLOCKTICKS", ++ .desc = "Number of uclks in domain", ++ .code = 0x1, ++ .cntmsk = 0xf, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ }, ++ { .name = "UNC_R2_RING_AD_USED", ++ .desc = "R2 AD Ring in Use", ++ .code = 0x7, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), ++ .umasks = ivbep_unc_r2_ring_ad_used ++ }, ++ { .name = "UNC_R2_RING_AK_USED", ++ .desc = "R2 AK Ring in Use", ++ .code = 0x8, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), ++ .umasks = ivbep_unc_r2_ring_ad_used /* shared */ ++ }, ++ { .name = "UNC_R2_RING_BL_USED", ++ .desc = "R2 BL Ring in Use", ++ .code = 0x9, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_ad_used), ++ .umasks = ivbep_unc_r2_ring_ad_used /* shared */ ++ }, ++ { .name = "UNC_R2_RING_IV_USED", ++ .desc = "R2 IV Ring in Use", ++ .code = 0xa, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_ring_iv_used), ++ .umasks = ivbep_unc_r2_ring_iv_used ++ }, ++ { .name = "UNC_R2_RXR_AK_BOUNCES", ++ .desc = "AK Ingress Bounced", ++ .code = 0x12, ++ .cntmsk = 0x1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_ak_bounces), ++ .umasks = ivbep_unc_r2_rxr_ak_bounces ++ }, ++ { .name = "UNC_R2_RXR_OCCUPANCY", ++ .desc = "Ingress occpancy accumulator", ++ .code = 0x13, ++ .cntmsk = 0x1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .ngrp = 1, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_occupancy), ++ .umasks = ivbep_unc_r2_rxr_occupancy ++ }, ++ { .name = "UNC_R2_RXR_CYCLES_NE", ++ .desc = "Ingress Cycles Not Empty", ++ .code = 0x10, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_cycles_ne), ++ .umasks = ivbep_unc_r2_rxr_cycles_ne ++ }, ++ { .name = "UNC_R2_RXR_INSERTS", ++ .desc = "Ingress inserts", ++ .code = 0x11, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_rxr_cycles_ne), ++ .umasks = ivbep_unc_r2_rxr_cycles_ne, /* shared */ ++ }, ++ { .name = "UNC_R2_TXR_CYCLES_FULL", ++ .desc = "Egress Cycles Full", ++ .code = 0x25, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), ++ .umasks = ivbep_unc_r2_txr_cycles_full ++ }, ++ { .name = "UNC_R2_TXR_CYCLES_NE", ++ .desc = "Egress Cycles Not Empty", ++ .code = 0x23, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), ++ .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ ++ }, ++ { .name = "UNC_R2_TXR_NACK_CCW", ++ .desc = "Egress counter-clockwise BACK", ++ .code = 0x28, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), ++ .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ ++ }, ++ { .name = "UNC_R2_TXR_NACK_CW", ++ .desc = "Egress clockwise BACK", ++ .code = 0x26, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R2PCIE_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r2_txr_cycles_full), ++ .umasks = ivbep_unc_r2_txr_cycles_full /* shared */ ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_r3qpi_events.h b/lib/events/intel_ivbep_unc_r3qpi_events.h +new file mode 100644 +index 0000000..75cb533 +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_r3qpi_events.h +@@ -0,0 +1,552 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * This file has been automatically generated. ++ * ++ * PMU: ivbep_unc_r3qpi (Intel IvyBridge-EP R3QPI uncore) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_r3_iio_credits_acquired[]={ ++ { .uname = "DRS", ++ .udesc = "DRS", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCB", ++ .udesc = "NCB", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "NCS", ++ .udesc = "NCS", ++ .ucode = 0x2000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_ring_ad_used[]={ ++ { .uname = "CCW_VR0_EVEN", ++ .udesc = "Counter-Clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x400, ++ }, ++ { .uname = "CCW_VR0_ODD", ++ .udesc = "Counter-Clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x800, ++ }, ++ { .uname = "CW_VR0_EVEN", ++ .udesc = "Clockwise and even ring polarity on virtual ring 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "CW_VR0_ODD", ++ .udesc = "Clockwise and odd ring polarity on virtual ring 0", ++ .ucode = 0x200, ++ }, ++ { .uname = "CW", ++ .udesc = "Clockwise with any polarity on either virtual rings", ++ .ucode = 0x3300, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xcc00, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_ring_iv_used[]={ ++ { .uname = "CW", ++ .udesc = "Clockwise with any polarity on either virtual rings", ++ .ucode = 0x3300, ++ }, ++ { .uname = "CCW", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xcc00, ++ }, ++ { .uname = "ANY", ++ .udesc = "Counter-clockwise with any polarity on either virtual rings", ++ .ucode = 0xff00, ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_rxr_cycles_ne[]={ ++ { .uname = "HOM", ++ .udesc = "HOM Ingress queue", ++ .ucode = 0x100, ++ }, ++ { .uname = "SNP", ++ .udesc = "SNP Ingress queue", ++ .ucode = 0x200, ++ }, ++ { .uname = "NDR", ++ .udesc = "NDR Ingress queue", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_rxr_inserts[]={ ++ { .uname = "DRS", ++ .udesc = "DRS Ingress queue", ++ .ucode = 0x800, ++ }, ++ { .uname = "HOM", ++ .udesc = "HOM Ingress queue", ++ .ucode = 0x100, ++ }, ++ { .uname = "NCB", ++ .udesc = "NCB Ingress queue", ++ .ucode = 0x1000, ++ }, ++ { .uname = "NCS", ++ .udesc = "NCS Ingress queue", ++ .ucode = 0x2000, ++ }, ++ { .uname = "NDR", ++ .udesc = "NDR Ingress queue", ++ .ucode = 0x400, ++ }, ++ { .uname = "SNP", ++ .udesc = "SNP Ingress queue", ++ .ucode = 0x200, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_vn0_credits_used[]={ ++ { .uname = "HOM", ++ .udesc = "Filter HOM message class", ++ .ucode = 0x100, ++ }, ++ { .uname = "SNP", ++ .udesc = "Filter SNP message class", ++ .ucode = 0x200, ++ }, ++ { .uname = "NDR", ++ .udesc = "Filter NDR message class", ++ .ucode = 0x400, ++ }, ++ { .uname = "DRS", ++ .udesc = "Filter DRS message class", ++ .ucode = 0x800, ++ }, ++ { .uname = "NCB", ++ .udesc = "Filter NCB message class", ++ .ucode = 0x1000, ++ }, ++ { .uname = "NCS", ++ .udesc = "Filter NCS message class", ++ .ucode = 0x2000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_c_hi_ad_credits_empty[]={ ++ { .uname = "CBO8", ++ .udesc = "CBox 8", ++ .ucode = 0x100, ++ }, ++ { .uname = "CBO9", ++ .udesc = "CBox 9", ++ .ucode = 0x200, ++ }, ++ { .uname = "CBO10", ++ .udesc = "CBox 10", ++ .ucode = 0x400, ++ }, ++ { .uname = "CBO11", ++ .udesc = "CBox 11", ++ .ucode = 0x800, ++ }, ++ { .uname = "CBO12", ++ .udesc = "CBox 12", ++ .ucode = 0x1000, ++ }, ++ { .uname = "CBO13", ++ .udesc = "CBox 13", ++ .ucode = 0x2000, ++ }, ++ { .uname = "CBO14", ++ .udesc = "CBox 14 & 16", ++ .ucode = 0x4000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_c_lo_ad_credits_empty[]={ ++ { .uname = "CBO0", ++ .udesc = "CBox 0", ++ .ucode = 0x100, ++ }, ++ { .uname = "CBO1", ++ .udesc = "CBox 1", ++ .ucode = 0x200, ++ }, ++ { .uname = "CBO2", ++ .udesc = "CBox 2", ++ .ucode = 0x400, ++ }, ++ { .uname = "CBO3", ++ .udesc = "CBox 3", ++ .ucode = 0x800, ++ }, ++ { .uname = "CBO4", ++ .udesc = "CBox 4", ++ .ucode = 0x1000, ++ }, ++ { .uname = "CBO5", ++ .udesc = "CBox 5", ++ .ucode = 0x2000, ++ }, ++ { .uname = "CBO6", ++ .udesc = "CBox 6", ++ .ucode = 0x4000, ++ }, ++ { .uname = "CBO7", ++ .udesc = "CBox 7", ++ .ucode = 0x8000, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_ha_r2_bl_credits_empty[]={ ++ { .uname = "HA0", ++ .udesc = "HA0", ++ .ucode = 0x100, ++ }, ++ { .uname = "HA1", ++ .udesc = "HA1", ++ .ucode = 0x200, ++ }, ++ { .uname = "R2_NCB", ++ .udesc = "R2 NCB messages", ++ .ucode = 0x400, ++ }, ++ { .uname = "R2_NCS", ++ .udesc = "R2 NCS messages", ++ .ucode = 0x800, ++ } ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_qpi0_ad_credits_empty[]={ ++ { .uname = "VNA", ++ .udesc = "VNA", ++ .ucode = 0x100, ++ }, ++ { .uname = "VN0_HOM", ++ .udesc = "VN0 HOM messages", ++ .ucode = 0x200, ++ }, ++ { .uname = "VN0_SNP", ++ .udesc = "VN0 SNP messages", ++ .ucode = 0x400, ++ }, ++ { .uname = "VN0_NDR", ++ .udesc = "VN0 NDR messages", ++ .ucode = 0x800, ++ }, ++ { .uname = "VN1_HOM", ++ .udesc = "VN1 HOM messages", ++ .ucode = 0x1000, ++ }, ++ { .uname = "VN1_SNP", ++ .udesc = "VN1 SNP messages", ++ .ucode = 0x2000, ++ }, ++ { .uname = "VN1_NDR", ++ .udesc = "VN1 NDR messages", ++ .ucode = 0x4000, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_txr_nack_ccw[]={ ++ { .uname = "AD", ++ .udesc = "BL counter-clockwise Egress queue", ++ .ucode = 0x100, ++ }, ++ { .uname = "AK", ++ .udesc = "AD clockwise Egress queue", ++ .ucode = 0x200, ++ }, ++ { .uname = "BL", ++ .udesc = "AD counter-clockwise Egress queue", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_txr_nack_cw[]={ ++ { .uname = "AD", ++ .udesc = "AD clockwise Egress queue", ++ .ucode = 0x100, ++ }, ++ { .uname = "AK", ++ .udesc = "AD counter-clockwise Egress queue", ++ .ucode = 0x200, ++ }, ++ { .uname = "BL", ++ .udesc = "BL clockwise Egress queue", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_umask_t ivbep_unc_r3_vna_credits_acquired[]={ ++ { .uname = "AD", ++ .udesc = "For AD ring", ++ .ucode = 0x100, ++ }, ++ { .uname = "BL", ++ .udesc = "For BL ring", ++ .ucode = 0x400, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_r3_pe[]={ ++ { .name = "UNC_R3_CLOCKTICKS", ++ .desc = "Number of uclks in domain", ++ .code = 0x1, ++ .cntmsk = 0x7, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_RING_AD_USED", ++ .desc = "R3 AD Ring in Use", ++ .code = 0x7, ++ .cntmsk = 0x7, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), ++ .umasks = ivbep_unc_r3_ring_ad_used ++ }, ++ { .name = "UNC_R3_RING_AK_USED", ++ .desc = "R3 AK Ring in Use", ++ .code = 0x8, ++ .cntmsk = 0x7, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), ++ .umasks = ivbep_unc_r3_ring_ad_used /* shared */ ++ }, ++ { .name = "UNC_R3_RING_BL_USED", ++ .desc = "R3 BL Ring in Use", ++ .code = 0x9, ++ .cntmsk = 0x7, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_ad_used), ++ .umasks = ivbep_unc_r3_ring_ad_used /* shared */ ++ }, ++ { .name = "UNC_R3_RING_IV_USED", ++ .desc = "R3 IV Ring in Use", ++ .code = 0xa, ++ .cntmsk = 0x7, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ring_iv_used), ++ .umasks = ivbep_unc_r3_ring_iv_used ++ }, ++ { .name = "UNC_R3_RXR_AD_BYPASSED", ++ .desc = "Ingress Bypassed", ++ .code = 0x12, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_RXR_CYCLES_NE", ++ .desc = "Ingress Cycles Not Empty", ++ .code = 0x10, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_cycles_ne), ++ .umasks = ivbep_unc_r3_rxr_cycles_ne ++ }, ++ { .name = "UNC_R3_RXR_INSERTS", ++ .desc = "Ingress Allocations", ++ .code = 0x11, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_inserts), ++ .umasks = ivbep_unc_r3_rxr_inserts ++ }, ++ { .name = "UNC_R3_RXR_OCCUPANCY", ++ .desc = "Ingress Occupancy Accumulator", ++ .code = 0x13, ++ .cntmsk = 0x1, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_rxr_inserts), ++ .umasks = ivbep_unc_r3_rxr_inserts/* shared */ ++ }, ++ { .name = "UNC_R3_TXR_CYCLES_FULL", ++ .desc = "Egress cycles full", ++ .code = 0x25, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_VN0_CREDITS_REJECT", ++ .desc = "VN0 Credit Acquisition Failed", ++ .code = 0x37, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), ++ .umasks = ivbep_unc_r3_vn0_credits_used ++ }, ++ { .name = "UNC_R3_VN0_CREDITS_USED", ++ .desc = "VN0 Credit Used", ++ .code = 0x36, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), ++ .umasks = ivbep_unc_r3_vn0_credits_used ++ }, ++ { .name = "UNC_R3_VNA_CREDITS_ACQUIRED", ++ .desc = "VNA credit Acquisitions", ++ .code = 0x33, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vna_credits_acquired), ++ .umasks = ivbep_unc_r3_vna_credits_acquired ++ }, ++ { .name = "UNC_R3_VNA_CREDITS_REJECT", ++ .desc = "VNA Credit Reject", ++ .code = 0x34, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), ++ .umasks = ivbep_unc_r3_vn0_credits_used /* shared */ ++ }, ++ { .name = "UNC_R3_VNA_CREDIT_CYCLES_OUT", ++ .desc = "Cycles with no VNA credits available", ++ .code = 0x31, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_VNA_CREDIT_CYCLES_USED", ++ .desc = "Cycles with 1 or more VNA credits in use", ++ .code = 0x32, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_C_HI_AD_CREDITS_EMPTY", ++ .desc = "Cbox AD credits empty", ++ .code = 0x2c, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_c_hi_ad_credits_empty), ++ .umasks = ivbep_unc_r3_c_hi_ad_credits_empty ++ }, ++ { .name = "UNC_R3_C_LO_AD_CREDITS_EMPTY", ++ .desc = "Cbox AD credits empty", ++ .code = 0x2b, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_c_lo_ad_credits_empty), ++ .umasks = ivbep_unc_r3_c_lo_ad_credits_empty ++ }, ++ { .name = "UNC_R3_HA_R2_BL_CREDITS_EMPTY", ++ .desc = "HA/R2 AD credits empty", ++ .code = 0x2f, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_ha_r2_bl_credits_empty), ++ .umasks = ivbep_unc_r3_ha_r2_bl_credits_empty ++ }, ++ { .name = "UNC_R3_QPI0_AD_CREDITS_EMPTY", ++ .desc = "QPI0 AD credits empty", ++ .code = 0x29, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), ++ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty ++ }, ++ { .name = "UNC_R3_QPI0_BL_CREDITS_EMPTY", ++ .desc = "QPI0 BL credits empty", ++ .code = 0x2d, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ ++ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty ++ }, ++ { .name = "UNC_R3_QPI1_AD_CREDITS_EMPTY", ++ .desc = "QPI1 AD credits empty", ++ .code = 0x2a, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ ++ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty ++ }, ++ { .name = "UNC_R3_QPI1_BL_CREDITS_EMPTY", ++ .desc = "QPI1 BL credits empty", ++ .code = 0x2e, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_qpi0_ad_credits_empty), /* shared */ ++ .umasks = ivbep_unc_r3_qpi0_ad_credits_empty ++ }, ++ { .name = "UNC_R3_TXR_CYCLES_NE", ++ .desc = "Egress cycles not empty", ++ .code = 0x23, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ }, ++ { .name = "UNC_R3_TXR_NACK_CCW", ++ .desc = "Egress NACK counter-clockwise", ++ .code = 0x28, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_txr_nack_ccw), ++ .umasks = ivbep_unc_r3_txr_nack_ccw ++ }, ++ { .name = "UNC_R3_TXR_NACK_CW", ++ .desc = "Egress NACK counter-clockwise", ++ .code = 0x26, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_txr_nack_cw), ++ .umasks = ivbep_unc_r3_txr_nack_cw ++ }, ++ { .name = "UNC_R3_VN1_CREDITS_REJECT", ++ .desc = "VN1 Credit Acquisition Failed", ++ .code = 0x39, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), /* shared */ ++ .umasks = ivbep_unc_r3_vn0_credits_used ++ }, ++ { .name = "UNC_R3_VN1_CREDITS_USED", ++ .desc = "VN0 Credit Used", ++ .code = 0x38, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_R3QPI_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_r3_vn0_credits_used), /* shared */ ++ .umasks = ivbep_unc_r3_vn0_credits_used ++ }, ++}; +diff --git a/lib/events/intel_ivbep_unc_ubo_events.h b/lib/events/intel_ivbep_unc_ubo_events.h +new file mode 100644 +index 0000000..ce08bde +--- /dev/null ++++ b/lib/events/intel_ivbep_unc_ubo_events.h +@@ -0,0 +1,101 @@ ++/* ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * This file is part of libpfm, a performance monitoring support library for ++ * applications on Linux. ++ * ++ * PMU: ivbep_unc_ubo (Intel IvyBridge-EP U-Box uncore PMU) ++ */ ++ ++static const intel_x86_umask_t ivbep_unc_u_event_msg[]={ ++ { .uname = "DOORBELL_RCVD", ++ .udesc = "TBD", ++ .ucode = 0x800, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "INT_PRIO", ++ .udesc = "TBD", ++ .ucode = 0x1000, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "IPI_RCVD", ++ .udesc = "TBD", ++ .ucode = 0x400, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "MSI_RCVD", ++ .udesc = "TBD", ++ .ucode = 0x200, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "VLW_RCVD", ++ .udesc = "TBD", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++ ++static const intel_x86_umask_t ivbep_unc_u_phold_cycles[]={ ++ { .uname = "ASSERT_TO_ACK", ++ .udesc = "Number of cycles asserted to ACK", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ACK_TO_DEASSERT", ++ .udesc = "Number of cycles ACK to deassert", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++}; ++ ++static const intel_x86_entry_t intel_ivbep_unc_u_pe[]={ ++ { .name = "UNC_U_EVENT_MSG", ++ .desc = "VLW Received", ++ .code = 0x42, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_UBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_u_event_msg), ++ .umasks = ivbep_unc_u_event_msg ++ }, ++ { .name = "UNC_U_LOCK_CYCLES", ++ .desc = "IDI Lock/SplitLock Cycles", ++ .code = 0x44, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_UBO_ATTRS, ++ }, ++ { .name = "UNC_U_PHOLD_CYCLES", ++ .desc = "Cycles PHOLD asserts to Ack", ++ .code = 0x45, ++ .cntmsk = 0x3, ++ .ngrp = 1, ++ .modmsk = IVBEP_UNC_UBO_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_u_phold_cycles), ++ .umasks = ivbep_unc_u_phold_cycles ++ }, ++ { .name = "UNC_U_RACU_REQUESTS", ++ .desc = "RACU requests", ++ .code = 0x46, ++ .cntmsk = 0x3, ++ .modmsk = IVBEP_UNC_UBO_ATTRS, ++ }, ++}; +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index bd2f49f..cd68301 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -121,6 +121,41 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &intel_snbep_unc_r3qpi1_support, + &intel_knc_support, + &intel_slm_support, ++ &intel_ivbep_unc_cb0_support, ++ &intel_ivbep_unc_cb1_support, ++ &intel_ivbep_unc_cb2_support, ++ &intel_ivbep_unc_cb3_support, ++ &intel_ivbep_unc_cb4_support, ++ &intel_ivbep_unc_cb5_support, ++ &intel_ivbep_unc_cb6_support, ++ &intel_ivbep_unc_cb7_support, ++ &intel_ivbep_unc_cb8_support, ++ &intel_ivbep_unc_cb9_support, ++ &intel_ivbep_unc_cb10_support, ++ &intel_ivbep_unc_cb11_support, ++ &intel_ivbep_unc_cb12_support, ++ &intel_ivbep_unc_cb13_support, ++ &intel_ivbep_unc_cb14_support, ++ &intel_ivbep_unc_ha0_support, ++ &intel_ivbep_unc_ha1_support, ++ &intel_ivbep_unc_imc0_support, ++ &intel_ivbep_unc_imc1_support, ++ &intel_ivbep_unc_imc2_support, ++ &intel_ivbep_unc_imc3_support, ++ &intel_ivbep_unc_imc4_support, ++ &intel_ivbep_unc_imc5_support, ++ &intel_ivbep_unc_imc6_support, ++ &intel_ivbep_unc_imc7_support, ++ &intel_ivbep_unc_pcu_support, ++ &intel_ivbep_unc_qpi0_support, ++ &intel_ivbep_unc_qpi1_support, ++ &intel_ivbep_unc_qpi2_support, ++ &intel_ivbep_unc_ubo_support, ++ &intel_ivbep_unc_r2pcie_support, ++ &intel_ivbep_unc_r3qpi0_support, ++ &intel_ivbep_unc_r3qpi1_support, ++ &intel_ivbep_unc_r3qpi2_support, ++ &intel_ivbep_unc_irp_support, + &intel_x86_arch_support, /* must always be last for x86 */ + #endif + +diff --git a/lib/pfmlib_intel_ivbep_unc_cbo.c b/lib/pfmlib_intel_ivbep_unc_cbo.c +new file mode 100644 +index 0000000..6053aa5 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_cbo.c +@@ -0,0 +1,125 @@ ++/* ++ * pfmlib_intel_ivbep_unc_cbo.c : Intel IvyBridge-EP C-Box uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_cbo_events.h" ++ ++static void ++display_cbo(void *this, pfmlib_event_desc_t *e, void *val) ++{ ++ const intel_x86_entry_t *pe = this_pe(this); ++ pfm_snbep_unc_reg_t *reg = val; ++ pfm_snbep_unc_reg_t f; ++ ++ __pfm_vbprintf("[UNC_CBO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " ++ "inv=%d edge=%d thres=%d tid_en=%d] %s\n", ++ reg->val, ++ reg->cbo.unc_event, ++ reg->cbo.unc_umask, ++ reg->cbo.unc_en, ++ reg->cbo.unc_inv, ++ reg->cbo.unc_edge, ++ reg->cbo.unc_thres, ++ reg->cbo.unc_tid, ++ pe[e->event].name); ++ ++ if (e->count == 1) ++ return; ++ ++ f.val = e->codes[1]; ++ ++ __pfm_vbprintf("[UNC_CBOX_FILTER0=0x%"PRIx64" tid=%d core=0x%x" ++ " state=0x%x]\n", ++ f.val, ++ f.ivbep_cbo_filt0.tid, ++ f.ivbep_cbo_filt0.cid, ++ f.ivbep_cbo_filt0.state); ++ ++ if (e->count == 2) ++ return; ++ ++ f.val = e->codes[2]; ++ ++ __pfm_vbprintf("[UNC_CBOX_FILTER1=0x%"PRIx64" nid=%d opc=0x%x" ++ " nc=0x%x isoc=0x%x]\n", ++ f.val, ++ f.ivbep_cbo_filt1.nid, ++ f.ivbep_cbo_filt1.opc, ++ f.ivbep_cbo_filt1.nc, ++ f.ivbep_cbo_filt1.isoc); ++} ++ ++#define DEFINE_C_BOX(n) \ ++pfmlib_pmu_t intel_ivbep_unc_cb##n##_support = {\ ++ .desc = "Intel Ivy Bridge-EP C-Box "#n" uncore",\ ++ .name = "ivbep_unc_cbo"#n,\ ++ .perf_name = "uncore_cbox_"#n,\ ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_CB##n,\ ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_c_pe),\ ++ .type = PFM_PMU_TYPE_UNCORE,\ ++ .num_cntrs = 4,\ ++ .num_fixed_cntrs = 0,\ ++ .max_encoding = 2,\ ++ .pe = intel_ivbep_unc_c_pe,\ ++ .atdesc = snbep_unc_mods,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK|INTEL_PMU_FL_UNC_CBO,\ ++ .pmu_detect = pfm_intel_ivbep_unc_detect,\ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first,\ ++ .get_event_next = pfm_intel_x86_get_event_next,\ ++ .event_is_valid = pfm_intel_x86_event_is_valid,\ ++ .validate_table = pfm_intel_x86_validate_table,\ ++ .get_event_info = pfm_intel_x86_get_event_info,\ ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ ++ .can_auto_encode = pfm_intel_x86_can_auto_encode, \ ++ .display_reg = display_cbo,\ ++} ++ ++DEFINE_C_BOX(0); ++DEFINE_C_BOX(1); ++DEFINE_C_BOX(2); ++DEFINE_C_BOX(3); ++DEFINE_C_BOX(4); ++DEFINE_C_BOX(5); ++DEFINE_C_BOX(6); ++DEFINE_C_BOX(7); ++DEFINE_C_BOX(8); ++DEFINE_C_BOX(9); ++DEFINE_C_BOX(10); ++DEFINE_C_BOX(11); ++DEFINE_C_BOX(12); ++DEFINE_C_BOX(13); ++DEFINE_C_BOX(14); +diff --git a/lib/pfmlib_intel_ivbep_unc_ha.c b/lib/pfmlib_intel_ivbep_unc_ha.c +new file mode 100644 +index 0000000..d4bd6f9 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_ha.c +@@ -0,0 +1,97 @@ ++/* ++ * pfmlib_intel_ivbep_unc_ha.c : Intel IvyBridge-EP Home Agent (HA) uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_ha_events.h" ++ ++static void ++display_ha(void *this, pfmlib_event_desc_t *e, void *val) ++{ ++ const intel_x86_entry_t *pe = this_pe(this); ++ pfm_snbep_unc_reg_t *reg = val; ++ pfm_snbep_unc_reg_t f; ++ ++ __pfm_vbprintf("[UNC_HA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " ++ "inv=%d edge=%d thres=%d] %s\n", ++ reg->val, ++ reg->com.unc_event, ++ reg->com.unc_umask, ++ reg->com.unc_en, ++ reg->com.unc_inv, ++ reg->com.unc_edge, ++ reg->com.unc_thres, ++ pe[e->event].name); ++ ++ if (e->count == 1) ++ return; ++ ++ f.val = e->codes[1]; ++ __pfm_vbprintf("[UNC_HA_ADDR=0x%"PRIx64" lo_addr=0x%x hi_addr=0x%x]\n", ++ f.val, ++ f.ha_addr.lo_addr, ++ f.ha_addr.hi_addr); ++ ++ f.val = e->codes[2]; ++ __pfm_vbprintf("[UNC_HA_OPC=0x%"PRIx64" opc=0x%x]\n", f.val, f.ha_opc.opc); ++} ++ ++#define DEFINE_HA_BOX(n) \ ++pfmlib_pmu_t intel_ivbep_unc_ha##n##_support = {\ ++ .desc = "Intel Ivy Bridge-EP HA "#n" uncore",\ ++ .name = "ivbep_unc_ha"#n,\ ++ .perf_name = "uncore_ha_"#n,\ ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_HA##n,\ ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_h_pe),\ ++ .type = PFM_PMU_TYPE_UNCORE,\ ++ .num_cntrs = 4,\ ++ .num_fixed_cntrs = 0,\ ++ .max_encoding = 3, /* address matchers */\ ++ .pe = intel_ivbep_unc_h_pe,\ ++ .atdesc = snbep_unc_mods,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .pmu_detect = pfm_intel_ivbep_unc_detect,\ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first,\ ++ .get_event_next = pfm_intel_x86_get_event_next,\ ++ .event_is_valid = pfm_intel_x86_event_is_valid,\ ++ .validate_table = pfm_intel_x86_validate_table,\ ++ .get_event_info = pfm_intel_x86_get_event_info,\ ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ ++ .display_reg = display_ha,\ ++} ++ ++DEFINE_HA_BOX(0); ++DEFINE_HA_BOX(1); +diff --git a/lib/pfmlib_intel_ivbep_unc_imc.c b/lib/pfmlib_intel_ivbep_unc_imc.c +new file mode 100644 +index 0000000..aa7d3a8 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_imc.c +@@ -0,0 +1,71 @@ ++/* ++ * pfmlib_intel_ivbep_unc_imc.c : Intel IvyBridge-EP Integrated Memory Controller (IMC) uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_imc_events.h" ++ ++#define DEFINE_IMC_BOX(n) \ ++pfmlib_pmu_t intel_ivbep_unc_imc##n##_support = { \ ++ .desc = "Intel Iyy Bridge-EP IMC"#n" uncore", \ ++ .name = "ivbep_unc_imc"#n, \ ++ .perf_name = "uncore_imc_"#n, \ ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_IMC##n, \ ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_m_pe), \ ++ .type = PFM_PMU_TYPE_UNCORE, \ ++ .num_cntrs = 4, \ ++ .num_fixed_cntrs = 1, \ ++ .max_encoding = 1, \ ++ .pe = intel_ivbep_unc_m_pe, \ ++ .atdesc = snbep_unc_mods, \ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, \ ++ .pmu_detect = pfm_intel_ivbep_unc_detect, \ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, \ ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), \ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first, \ ++ .get_event_next = pfm_intel_x86_get_event_next, \ ++ .event_is_valid = pfm_intel_x86_event_is_valid, \ ++ .validate_table = pfm_intel_x86_validate_table, \ ++ .get_event_info = pfm_intel_x86_get_event_info, \ ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, \ ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), \ ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, \ ++}; ++ ++DEFINE_IMC_BOX(0); ++DEFINE_IMC_BOX(1); ++DEFINE_IMC_BOX(2); ++DEFINE_IMC_BOX(3); ++DEFINE_IMC_BOX(4); ++DEFINE_IMC_BOX(5); ++DEFINE_IMC_BOX(6); ++DEFINE_IMC_BOX(7); +diff --git a/lib/pfmlib_intel_ivbep_unc_irp.c b/lib/pfmlib_intel_ivbep_unc_irp.c +new file mode 100644 +index 0000000..84fc22f +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_irp.c +@@ -0,0 +1,79 @@ ++/* ++ * pfmlib_intel_ivbep_irp.c : Intel IvyBridge-EP IRP uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_irp_events.h" ++ ++static void ++display_irp(void *this, pfmlib_event_desc_t *e, void *val) ++{ ++ const intel_x86_entry_t *pe = this_pe(this); ++ pfm_snbep_unc_reg_t *reg = val; ++ ++ __pfm_vbprintf("[UNC_IRP=0x%"PRIx64" event=0x%x umask=0x%x en=%d " ++ "edge=%d thres=%d] %s\n", ++ reg->val, ++ reg->irp.unc_event, ++ reg->irp.unc_umask, ++ reg->irp.unc_en, ++ reg->irp.unc_edge, ++ reg->irp.unc_thres, ++ pe[e->event].name); ++} ++ ++pfmlib_pmu_t intel_ivbep_unc_irp_support = { ++ .desc = "Intel Ivy Bridge-EP IRP uncore", ++ .name = "ivbep_unc_irp", ++ .perf_name = "uncore_irp", ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_IRP, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_i_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .num_cntrs = 4, ++ .num_fixed_cntrs = 0, ++ .max_encoding = 3, ++ .pe = intel_ivbep_unc_i_pe, ++ .atdesc = snbep_unc_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_intel_ivbep_unc_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++ .display_reg = display_irp, ++}; +diff --git a/lib/pfmlib_intel_ivbep_unc_pcu.c b/lib/pfmlib_intel_ivbep_unc_pcu.c +new file mode 100644 +index 0000000..782f881 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_pcu.c +@@ -0,0 +1,97 @@ ++/* ++ * pfmlib_intel_ivbep_unc_pcu.c : Intel IvyBridge-EP Power Control Unit (PCU) uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_pcu_events.h" ++ ++static void ++display_pcu(void *this, pfmlib_event_desc_t *e, void *val) ++{ ++ const intel_x86_entry_t *pe = this_pe(this); ++ pfm_snbep_unc_reg_t *reg = val; ++ pfm_snbep_unc_reg_t f; ++ ++ __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x sel_ext=%d occ_sel=0x%x en=%d " ++ "edge=%d thres=%d occ_inv=%d occ_edge=%d] %s\n", ++ reg->val, ++ reg->ivbep_pcu.unc_event, ++ reg->ivbep_pcu.unc_sel_ext, ++ reg->ivbep_pcu.unc_occ, ++ reg->ivbep_pcu.unc_en, ++ reg->ivbep_pcu.unc_edge, ++ reg->ivbep_pcu.unc_thres, ++ reg->ivbep_pcu.unc_occ_inv, ++ reg->ivbep_pcu.unc_occ_edge, ++ pe[e->event].name); ++ ++ if (e->count == 1) ++ return; ++ ++ f.val = e->codes[1]; ++ ++ __pfm_vbprintf("[UNC_PCU_FILTER=0x%"PRIx64" band0=%u band1=%u band2=%u band3=%u]\n", ++ f.val, ++ f.pcu_filt.filt0, ++ f.pcu_filt.filt1, ++ f.pcu_filt.filt2, ++ f.pcu_filt.filt3); ++} ++ ++ ++pfmlib_pmu_t intel_ivbep_unc_pcu_support = { ++ .desc = "Intel Ivy Bridge-EP PCU uncore", ++ .name = "ivbep_unc_pcu", ++ .perf_name = "uncore_pcu", ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_PCU, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_p_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .num_cntrs = 4, ++ .num_fixed_cntrs = 0, ++ .max_encoding = 2, ++ .pe = intel_ivbep_unc_p_pe, ++ .atdesc = snbep_unc_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_intel_ivbep_unc_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++ .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, ++ .display_reg = display_pcu, ++}; +diff --git a/lib/pfmlib_intel_ivbep_unc_qpi.c b/lib/pfmlib_intel_ivbep_unc_qpi.c +new file mode 100644 +index 0000000..e68eb75 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_qpi.c +@@ -0,0 +1,85 @@ ++/* ++ * pfmlib_intel_ivbep_qpi.c : Intel IvyBridge-EP QPI uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_qpi_events.h" ++ ++static void ++display_qpi(void *this, pfmlib_event_desc_t *e, void *val) ++{ ++ const intel_x86_entry_t *pe = this_pe(this); ++ pfm_snbep_unc_reg_t *reg = val; ++ ++ __pfm_vbprintf("[UNC_QPI=0x%"PRIx64" event=0x%x sel_ext=%d umask=0x%x en=%d " ++ "inv=%d edge=%d thres=%d] %s\n", ++ reg->val, ++ reg->qpi.unc_event, ++ reg->qpi.unc_event_ext, ++ reg->qpi.unc_umask, ++ reg->qpi.unc_en, ++ reg->qpi.unc_inv, ++ reg->qpi.unc_edge, ++ reg->qpi.unc_thres, ++ pe[e->event].name); ++} ++ ++#define DEFINE_QPI_BOX(n) \ ++pfmlib_pmu_t intel_ivbep_unc_qpi##n##_support = {\ ++ .desc = "Intel Ivy Bridge-EP QPI"#n" uncore",\ ++ .name = "ivbep_unc_qpi"#n,\ ++ .perf_name = "uncore_qpi_"#n,\ ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_QPI##n,\ ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_q_pe),\ ++ .type = PFM_PMU_TYPE_UNCORE,\ ++ .num_cntrs = 4,\ ++ .num_fixed_cntrs = 0,\ ++ .max_encoding = 3,\ ++ .pe = intel_ivbep_unc_q_pe,\ ++ .atdesc = snbep_unc_mods,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .pmu_detect = pfm_intel_ivbep_unc_detect,\ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first,\ ++ .get_event_next = pfm_intel_x86_get_event_next,\ ++ .event_is_valid = pfm_intel_x86_event_is_valid,\ ++ .validate_table = pfm_intel_x86_validate_table,\ ++ .get_event_info = pfm_intel_x86_get_event_info,\ ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ ++ .display_reg = display_qpi,\ ++} ++DEFINE_QPI_BOX(0); ++DEFINE_QPI_BOX(1); ++DEFINE_QPI_BOX(2); +diff --git a/lib/pfmlib_intel_ivbep_unc_r2pcie.c b/lib/pfmlib_intel_ivbep_unc_r2pcie.c +new file mode 100644 +index 0000000..87c680c +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_r2pcie.c +@@ -0,0 +1,61 @@ ++/* ++ * pfmlib_intel_ivbep_r2pcie.c : Intel IvyBridge-EP R2PCIe uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_r2pcie_events.h" ++ ++pfmlib_pmu_t intel_ivbep_unc_r2pcie_support = { ++ .desc = "Intel Ivy Bridge-EP R2PCIe uncore", ++ .name = "ivbep_unc_r2pcie", ++ .perf_name = "uncore_r2pcie", ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_R2PCIE, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_r2_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .num_cntrs = 4, ++ .num_fixed_cntrs = 0, ++ .max_encoding = 1, ++ .pe = intel_ivbep_unc_r2_pe, ++ .atdesc = snbep_unc_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_intel_ivbep_unc_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_intel_ivbep_unc_r3qpi.c b/lib/pfmlib_intel_ivbep_unc_r3qpi.c +new file mode 100644 +index 0000000..5ed7e4d +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_r3qpi.c +@@ -0,0 +1,65 @@ ++/* ++ * pfmlib_intel_ivbep_r3qpi.c : Intel IvyBridge-EP R3QPI uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_r3qpi_events.h" ++ ++#define DEFINE_R3QPI_BOX(n) \ ++pfmlib_pmu_t intel_ivbep_unc_r3qpi##n##_support = {\ ++ .desc = "Intel Ivy Bridge-EP R3QPI"#n" uncore", \ ++ .name = "ivbep_unc_r3qpi"#n,\ ++ .perf_name = "uncore_r3qpi_"#n, \ ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_R3QPI##n, \ ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_r3_pe),\ ++ .type = PFM_PMU_TYPE_UNCORE,\ ++ .num_cntrs = 3,\ ++ .num_fixed_cntrs = 0,\ ++ .max_encoding = 1,\ ++ .pe = intel_ivbep_unc_r3_pe,\ ++ .atdesc = snbep_unc_mods,\ ++ .flags = PFMLIB_PMU_FL_RAW_UMASK,\ ++ .pmu_detect = pfm_intel_ivbep_unc_detect,\ ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ ++ .get_event_first = pfm_intel_x86_get_event_first,\ ++ .get_event_next = pfm_intel_x86_get_event_next,\ ++ .event_is_valid = pfm_intel_x86_event_is_valid,\ ++ .validate_table = pfm_intel_x86_validate_table,\ ++ .get_event_info = pfm_intel_x86_get_event_info,\ ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ ++} ++DEFINE_R3QPI_BOX(0); ++DEFINE_R3QPI_BOX(1); ++DEFINE_R3QPI_BOX(2); +diff --git a/lib/pfmlib_intel_ivbep_unc_ubo.c b/lib/pfmlib_intel_ivbep_unc_ubo.c +new file mode 100644 +index 0000000..db7f629 +--- /dev/null ++++ b/lib/pfmlib_intel_ivbep_unc_ubo.c +@@ -0,0 +1,61 @@ ++/* ++ * pfmlib_intel_ivbep_unc_ubo.c : Intel IvyBridge-EP U-Box uncore PMU ++ * ++ * Copyright (c) 2014 Google Inc. All rights reserved ++ * Contributed by Stephane Eranian ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to deal ++ * in the Software without restriction, including without limitation the rights ++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies ++ * of the Software, and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in all ++ * copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, ++ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A ++ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++/* private headers */ ++#include "pfmlib_priv.h" ++#include "pfmlib_intel_x86_priv.h" ++#include "pfmlib_intel_snbep_unc_priv.h" ++#include "events/intel_ivbep_unc_ubo_events.h" ++ ++pfmlib_pmu_t intel_ivbep_unc_ubo_support = { ++ .desc = "Intel Ivy Bridge-EP U-Box uncore", ++ .name = "ivbep_unc_ubo", ++ .perf_name = "uncore_ubox", ++ .pmu = PFM_PMU_INTEL_IVBEP_UNC_UBOX, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_ivbep_unc_u_pe), ++ .type = PFM_PMU_TYPE_UNCORE, ++ .num_cntrs = 2, ++ .num_fixed_cntrs = 1, ++ .max_encoding = 1, ++ .pe = intel_ivbep_unc_u_pe, ++ .atdesc = snbep_unc_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK, ++ .pmu_detect = pfm_intel_ivbep_unc_detect, ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), ++ PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_intel_snbep_unc.c b/lib/pfmlib_intel_snbep_unc.c +index 7ca86ca..8fb6472 100644 +--- a/lib/pfmlib_intel_snbep_unc.c ++++ b/lib/pfmlib_intel_snbep_unc.c +@@ -39,9 +39,10 @@ const pfmlib_attr_desc_t snbep_unc_mods[]={ + PFM_ATTR_I("t", "threshold in range [0-31]"), /* threshold */ + PFM_ATTR_I("tf", "thread id filter [0-1]"), /* thread id */ + PFM_ATTR_I("cf", "core id filter [0-7]"), /* core id */ +- PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask */ ++ PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask filter0 */ + PFM_ATTR_I("ff", "frequency >= 100Mhz * [0-255]"),/* freq filter */ + PFM_ATTR_I("addr", "physical address matcher [40 bits]"),/* address matcher */ ++ PFM_ATTR_I("nf", "node id bitmask filter [0-255]"),/* nodeid mask filter1 */ + PFM_ATTR_NULL + }; + +@@ -65,6 +66,26 @@ pfm_intel_snbep_unc_detect(void *this) + return PFM_SUCCESS; + } + ++int ++pfm_intel_ivbep_unc_detect(void *this) ++{ ++ int ret; ++ ++ ret = pfm_intel_x86_detect(); ++ if (ret != PFM_SUCCESS) ++ ++ if (pfm_intel_x86_cfg.family != 6) ++ return PFM_ERR_NOTSUPP; ++ ++ switch(pfm_intel_x86_cfg.model) { ++ case 62: /* SandyBridge-EP */ ++ break; ++ default: ++ return PFM_ERR_NOTSUPP; ++ } ++ return PFM_SUCCESS; ++} ++ + static void + display_com(void *this, pfmlib_event_desc_t *e, void *val) + { +@@ -113,7 +134,7 @@ int + snbep_unc_add_defaults(void *this, pfmlib_event_desc_t *e, + unsigned int msk, + uint64_t *umask, +- pfm_snbep_unc_reg_t *filter, ++ pfm_snbep_unc_reg_t *filters, + unsigned int max_grpid) + { + const intel_x86_entry_t *pe = this_pe(this); +@@ -167,7 +188,9 @@ snbep_unc_add_defaults(void *this, pfmlib_event_desc_t *e, + * ucode must reflect actual code + */ + *umask |= ent->umasks[idx].ucode >> 8; +- filter->val |= pe[e->event].umasks[idx].ufilters[0]; ++ ++ filters[0].val |= pe[e->event].umasks[idx].ufilters[0]; ++ filters[1].val |= pe[e->event].umasks[idx].ufilters[1]; + + e->attrs[k].id = j; /* pattrs index */ + e->attrs[k].ival = 0; +@@ -211,7 +234,7 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + int umodmsk = 0, modmsk_r = 0; + int pcu_filt_band = -1; + pfm_snbep_unc_reg_t reg; +- pfm_snbep_unc_reg_t filter; ++ pfm_snbep_unc_reg_t filters[INTEL_X86_MAX_FILTERS]; + pfm_snbep_unc_reg_t addr; + pfm_event_attr_info_t *a; + uint64_t val, umask1, umask2; +@@ -224,8 +247,8 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + + memset(grpcounts, 0, sizeof(grpcounts)); + memset(ncombo, 0, sizeof(ncombo)); ++ memset(filters, 0, sizeof(filters)); + +- filter.val = 0; + addr.val = 0; + + pe = this_pe(this); +@@ -310,10 +333,12 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + last_grpid = grpid; + + um = pe[e->event].umasks[a->idx].ucode; +- filter.val |= pe[e->event].umasks[a->idx].ufilters[0]; ++ filters[0].val |= pe[e->event].umasks[a->idx].ufilters[0]; ++ filters[1].val |= pe[e->event].umasks[a->idx].ufilters[1]; + + um >>= 8; + umask2 |= um; ++ + ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid; + + /* PCU occ event */ +@@ -377,30 +402,38 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + } + reg.cbo.unc_tid = 1; + has_cbo_tid = 1; +- filter.cbo_filt.tid = ival; ++ filters[0].cbo_filt.tid = ival; + umodmsk |= _SNBEP_UNC_ATTR_TF; + break; + case SNBEP_UNC_ATTR_CF: /* core id */ + if (ival > 7) + return PFM_ERR_ATTR_VAL; + reg.cbo.unc_tid = 1; +- filter.cbo_filt.cid = ival; ++ filters[0].cbo_filt.cid = ival; + has_cbo_tid = 1; + umodmsk |= _SNBEP_UNC_ATTR_CF; + break; +- case SNBEP_UNC_ATTR_NF: /* node id */ ++ case SNBEP_UNC_ATTR_NF: /* node id filter0 */ + if (ival > 255 || ival == 0) { + DPRINT("invalid nf, 0 < nf < 256\n"); + return PFM_ERR_ATTR_VAL; + } +- filter.cbo_filt.nid = ival; ++ filters[0].cbo_filt.nid = ival; + umodmsk |= _SNBEP_UNC_ATTR_NF; + break; ++ case SNBEP_UNC_ATTR_NF1: /* node id filter1 */ ++ if (ival > 255 || ival == 0) { ++ DPRINT("invalid nf, 0 < nf < 256\n"); ++ return PFM_ERR_ATTR_VAL; ++ } ++ filters[1].ivbep_cbo_filt1.nid = ival; ++ umodmsk |= _SNBEP_UNC_ATTR_NF1; ++ break; + case SNBEP_UNC_ATTR_FF: /* freq band filter */ + if (ival > 255) + return PFM_ERR_ATTR_VAL; + pcu_filt_band = get_pcu_filt_band(this, reg); +- filter.val = ival << (pcu_filt_band * 8); ++ filters[0].val = ival << (pcu_filt_band * 8); + umodmsk |= _SNBEP_UNC_ATTR_FF; + break; + case SNBEP_UNC_ATTR_A: /* addr filter */ +@@ -421,7 +454,7 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + if (pe[e->event].numasks && (ugrpmsk != grpmsk || ugrpmsk == 0)) { + uint64_t um = 0; + ugrpmsk ^= grpmsk; +- ret = snbep_unc_add_defaults(this, e, ugrpmsk, &um, &filter, max_grpid); ++ ret = snbep_unc_add_defaults(this, e, ugrpmsk, &um, filters, max_grpid); + if (ret != PFM_SUCCESS) + return ret; + umask2 |= um; +@@ -434,6 +467,10 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + DPRINT("using nf= on an umask which does not require it\n"); + return PFM_ERR_ATTR; + } ++ if (!(modmsk_r & _SNBEP_UNC_ATTR_NF1) && (umodmsk & _SNBEP_UNC_ATTR_NF1)) { ++ DPRINT("using nf= on an umask which does not require it\n"); ++ return PFM_ERR_ATTR; ++ } + + if (modmsk_r && !(umodmsk & modmsk_r)) { + DPRINT("required modifiers missing: 0x%x\n", modmsk_r); +@@ -452,6 +489,7 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + else if (a->type == PFM_ATTR_RAW_UMASK) + evt_strcat(e->fstr, ":0x%x", a->idx); + } ++ DPRINT("umask2=0x%"PRIx64" umask1=0x%"PRIx64"\n", umask2, umask1); + e->count = 0; + reg.val |= (umask1 | umask2) << 8; + +@@ -460,8 +498,10 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + /* + * handles C-box filter + */ +- if (filter.val || has_cbo_tid) +- e->codes[e->count++] = filter.val; ++ if (filters[0].val || filters[1].val || has_cbo_tid) ++ e->codes[e->count++] = filters[0].val; ++ if (filters[1].val) ++ e->codes[e->count++] = filters[1].val; + + /* HA address matcher */ + if (addr.val) +@@ -500,10 +540,15 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.cbo.unc_tid); + break; + case SNBEP_UNC_ATTR_FF: +- evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, (filter.val >> (pcu_filt_band*8)) & 0xff); ++ evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, (filters[0].val >> (pcu_filt_band*8)) & 0xff); + break; + case SNBEP_UNC_ATTR_NF: +- evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filter.cbo_filt.nid); ++ if (modmsk_r & _SNBEP_UNC_ATTR_NF) ++ evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[0].cbo_filt.nid); ++ break; ++ case SNBEP_UNC_ATTR_NF1: ++ if (modmsk_r & _SNBEP_UNC_ATTR_NF1) ++ evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[1].ivbep_cbo_filt1.nid); + break; + case SNBEP_UNC_ATTR_A: + evt_strcat(e->fstr, ":%s=0x%lx", snbep_unc_mods[idx].name, +diff --git a/lib/pfmlib_intel_snbep_unc_perf_event.c b/lib/pfmlib_intel_snbep_unc_perf_event.c +index e6cc625..2b06cb2 100644 +--- a/lib/pfmlib_intel_snbep_unc_perf_event.c ++++ b/lib/pfmlib_intel_snbep_unc_perf_event.c +@@ -83,14 +83,21 @@ pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e) + + attr->config = reg.val; + +- /* +- * various filters +- */ +- if (e->count == 2) +- attr->config1 = e->codes[1]; +- +- if (e->count == 3) +- attr->config2 = e->codes[2]; ++ if (is_cbo_filt_event(this, reg) && e->count > 1) { ++ if (e->count >= 2) ++ attr->config1 = e->codes[1]; ++ if (e->count >= 3) ++ attr->config1 |= e->codes[2] << 32; ++ } else { ++ /* ++ * various filters ++ */ ++ if (e->count >= 2) ++ attr->config1 = e->codes[1]; ++ ++ if (e->count >= 3) ++ attr->config2 = e->codes[2]; ++ } + + /* + * uncore measures at all priv levels +diff --git a/lib/pfmlib_intel_snbep_unc_priv.h b/lib/pfmlib_intel_snbep_unc_priv.h +index 3631930..d93b5f8 100644 +--- a/lib/pfmlib_intel_snbep_unc_priv.h ++++ b/lib/pfmlib_intel_snbep_unc_priv.h +@@ -1,5 +1,5 @@ + /* +- * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge-EP common definitions ++ * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge/IvyBridge-EP common definitions + * + * Copyright (c) 2012 Google, Inc + * Contributed by Stephane Eranian +@@ -28,6 +28,7 @@ + * Intel x86 specific pmu flags (pmu->flags 16 MSB) + */ + #define INTEL_PMU_FL_UNC_OCC 0x10000 /* PMU has occupancy counter filters */ ++#define INTEL_PMU_FL_UNC_CBO 0x20000 /* PMU is Cbox */ + + + #define SNBEP_UNC_ATTR_E 0 +@@ -36,9 +37,10 @@ + #define SNBEP_UNC_ATTR_T5 3 + #define SNBEP_UNC_ATTR_TF 4 + #define SNBEP_UNC_ATTR_CF 5 +-#define SNBEP_UNC_ATTR_NF 6 ++#define SNBEP_UNC_ATTR_NF 6 /* for filter0 */ + #define SNBEP_UNC_ATTR_FF 7 + #define SNBEP_UNC_ATTR_A 8 ++#define SNBEP_UNC_ATTR_NF1 9 /* for filter1 */ + + #define _SNBEP_UNC_ATTR_I (1 << SNBEP_UNC_ATTR_I) + #define _SNBEP_UNC_ATTR_E (1 << SNBEP_UNC_ATTR_E) +@@ -49,41 +51,79 @@ + #define _SNBEP_UNC_ATTR_NF (1 << SNBEP_UNC_ATTR_NF) + #define _SNBEP_UNC_ATTR_FF (1 << SNBEP_UNC_ATTR_FF) + #define _SNBEP_UNC_ATTR_A (1 << SNBEP_UNC_ATTR_A) ++#define _SNBEP_UNC_ATTR_NF1 (1 << SNBEP_UNC_ATTR_NF1) ++ ++#define SNBEP_UNC_IRP_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + + #define SNBEP_UNC_R3QPI_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + ++#define IVBEP_UNC_R3QPI_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ + #define SNBEP_UNC_R2PCIE_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + ++#define IVBEP_UNC_R2PCIE_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ + #define SNBEP_UNC_QPI_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + ++#define IVBEP_UNC_QPI_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ + #define SNBEP_UNC_UBO_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + ++#define IVBEP_UNC_UBO_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ ++ + #define SNBEP_UNC_PCU_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5) + ++#define IVBEP_UNC_PCU_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5) ++ + #define SNBEP_UNC_PCU_BAND_ATTRS \ + (SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) + ++#define IVBEP_UNC_PCU_BAND_ATTRS \ ++ (IVBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) ++ + #define SNBEP_UNC_IMC_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +-#define SNBEP_UNC_CBO_ATTRS \ ++#define IVBEP_UNC_IMC_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ ++#define SNBEP_UNC_CBO_ATTRS \ + (_SNBEP_UNC_ATTR_I |\ + _SNBEP_UNC_ATTR_E |\ + _SNBEP_UNC_ATTR_T8 |\ + _SNBEP_UNC_ATTR_CF |\ + _SNBEP_UNC_ATTR_TF) + ++#define IVBEP_UNC_CBO_ATTRS \ ++ (_SNBEP_UNC_ATTR_E |\ ++ _SNBEP_UNC_ATTR_T8 |\ ++ _SNBEP_UNC_ATTR_CF |\ ++ _SNBEP_UNC_ATTR_TF) ++ + #define SNBEP_UNC_CBO_NID_ATTRS \ + (SNBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF) + ++#define IVBEP_UNC_CBO_NID_ATTRS \ ++ (IVBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF1) ++ + #define SNBEP_UNC_HA_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + ++#define IVBEP_UNC_HA_ATTRS \ ++ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) ++ + #define SNBEP_UNC_HA_OPC_ATTRS \ + (SNBEP_UNC_HA_ATTRS|_SNBEP_UNC_ATTR_A) + +@@ -133,6 +173,24 @@ typedef union { + } pcu; /* covers pcu */ + struct { + unsigned long unc_event:8; /* event code */ ++ unsigned long unc_res1:6; /* reserved */ ++ unsigned long unc_occ:2; /* occ select */ ++ unsigned long unc_res2:1; /* reserved */ ++ unsigned long unc_rst:1; /* reset */ ++ unsigned long unc_edge:1; /* edge detec */ ++ unsigned long unc_res3:1; /* reserved */ ++ unsigned long unc_ov_en:1; /* overflow enable */ ++ unsigned long unc_sel_ext:1; /* event_sel extension */ ++ unsigned long unc_en:1; /* enable */ ++ unsigned long unc_res4:1; /* reserved */ ++ unsigned long unc_thres:5; /* threshold */ ++ unsigned long unc_res5:1; /* reserved */ ++ unsigned long unc_occ_inv:1; /* occupancy invert */ ++ unsigned long unc_occ_edge:1; /* occupancy edge detect */ ++ unsigned long unc_res6:32; /* reserved */ ++ } ivbep_pcu; /* covers ivb-ep pcu */ ++ struct { ++ unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit maks */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ +@@ -158,6 +216,23 @@ typedef union { + unsigned long res4:32; + } cbo_filt; /* cbox filter */ + struct { ++ unsigned long tid:1; ++ unsigned long cid:4; ++ unsigned long res0:12; ++ unsigned long state:6; ++ unsigned long res1:9; ++ unsigned long res2:32; ++ } ivbep_cbo_filt0; /* ivbep cbox filter0 */ ++ struct { ++ unsigned long nid:16; ++ unsigned long res0:4; ++ unsigned long opc:9; ++ unsigned long res1:1; ++ unsigned long nc:1; ++ unsigned long isoc:1; ++ unsigned long res2:32; ++ } ivbep_cbo_filt1; /* ivbep cbox filter1 */ ++ struct { + unsigned long filt0:8; /* band0 freq filter */ + unsigned long filt1:8; /* band1 freq filter */ + unsigned long filt2:8; /* band2 freq filter */ +@@ -175,13 +250,43 @@ typedef union { + unsigned long res1:26; /* reserved */ + unsigned long res2:32; /* reserved */ + } ha_opc; ++ struct { ++ unsigned long unc_event:8; /* event code */ ++ unsigned long unc_umask:8; /* unit mask */ ++ unsigned long unc_res1:1; /* reserved */ ++ unsigned long unc_rst:1; /* reset */ ++ unsigned long unc_edge:1; /* edge detec */ ++ unsigned long unc_res2:3; /* reserved */ ++ unsigned long unc_en:1; /* enable */ ++ unsigned long unc_res3:1; /* reserved */ ++ unsigned long unc_thres:8; /* counter mask */ ++ unsigned long unc_res4:32; /* reserved */ ++ } irp; /* covers irp */ + } pfm_snbep_unc_reg_t; + + extern void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e); + extern int pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e); + extern const pfmlib_attr_desc_t snbep_unc_mods[]; + extern int pfm_intel_snbep_unc_detect(void *this); ++extern int pfm_intel_ivbep_unc_detect(void *this); + extern int pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); + extern int pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx); + extern int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfm_event_attr_info_t *info); ++ ++static inline int ++is_cbo_filt_event(void *this, pfm_intel_x86_reg_t reg) ++{ ++ pfmlib_pmu_t *pmu = this; ++ uint64_t sel = reg.sel_event_select; ++ /* ++ * umask bit 0 must be 1 (OPCODE) ++ * TOR_INSERT: event code 0x35 ++ * TOR_OCCUPANCY: event code 0x36 ++ * LLC_LOOKUP : event code 0x34 ++ */ ++ return (pmu->flags & INTEL_PMU_FL_UNC_CBO) ++ && (reg.sel_unit_mask & 0x1) ++ && (sel == 0x35 || sel == 0x36 || sel == 0x34); ++} ++ + #endif /* __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ */ +diff --git a/lib/pfmlib_intel_x86_priv.h b/lib/pfmlib_intel_x86_priv.h +index 95a7565..3b077b1 100644 +--- a/lib/pfmlib_intel_x86_priv.h ++++ b/lib/pfmlib_intel_x86_priv.h +@@ -34,7 +34,7 @@ + * maximum number of unit masks groups per event + */ + #define INTEL_X86_NUM_GRP 8 +-#define INTEL_X86_MAX_FILTERS 2 ++#define INTEL_X86_MAX_FILTERS 3 + + /* + * unit mask description +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index e1a2458..2b5d33e 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -267,6 +267,41 @@ extern pfmlib_pmu_t intel_snbep_unc_ubo_support; + extern pfmlib_pmu_t intel_snbep_unc_r2pcie_support; + extern pfmlib_pmu_t intel_snbep_unc_r3qpi0_support; + extern pfmlib_pmu_t intel_snbep_unc_r3qpi1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb0_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb2_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb3_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb4_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb5_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb6_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb7_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb8_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb9_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb10_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb11_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb12_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb13_support; ++extern pfmlib_pmu_t intel_ivbep_unc_cb14_support; ++extern pfmlib_pmu_t intel_ivbep_unc_ha0_support; ++extern pfmlib_pmu_t intel_ivbep_unc_ha1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc0_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc2_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc3_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc4_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc5_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc6_support; ++extern pfmlib_pmu_t intel_ivbep_unc_imc7_support; ++extern pfmlib_pmu_t intel_ivbep_unc_pcu_support; ++extern pfmlib_pmu_t intel_ivbep_unc_qpi0_support; ++extern pfmlib_pmu_t intel_ivbep_unc_qpi1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_qpi2_support; ++extern pfmlib_pmu_t intel_ivbep_unc_ubo_support; ++extern pfmlib_pmu_t intel_ivbep_unc_r2pcie_support; ++extern pfmlib_pmu_t intel_ivbep_unc_r3qpi0_support; ++extern pfmlib_pmu_t intel_ivbep_unc_r3qpi1_support; ++extern pfmlib_pmu_t intel_ivbep_unc_r3qpi2_support; ++extern pfmlib_pmu_t intel_ivbep_unc_irp_support; + extern pfmlib_pmu_t intel_knc_support; + extern pfmlib_pmu_t intel_slm_support; + extern pfmlib_pmu_t power4_support; +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index d0a6666..2edacd5 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1251,7 +1251,7 @@ static const test_event_t x86_test_events[]={ + .count = 2, + .codes[0] = 0x334, + .codes[1] = 0x7c0000, +- .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:i=0:t=0:tf=0:nf=0", ++ .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:i=0:t=0:tf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", +@@ -1294,7 +1294,7 @@ static const test_event_t x86_test_events[]={ + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1035, +- .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:i=0:t=0:tf=0:nf=0", ++ .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:i=0:t=0:tf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF", +@@ -1302,7 +1302,7 @@ static const test_event_t x86_test_events[]={ + .count = 2, + .codes[0] = 0x135, + .codes[1] = 0xca000000, +- .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:i=0:t=0:tf=0:nf=0", ++ .fstr = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:i=0:t=0:tf=0", + }, + { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", +@@ -2185,7 +2185,513 @@ static const test_event_t x86_test_events[]={ + .name = "slm::no_alloc_cycles:any:t=1", + .ret = PFM_ERR_ATTR + }, ++ { SRC_LINE, ++ .name = "ivbep_unc_irp::unc_i_clockticks", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x0, ++ .fstr = "ivbep_unc_irp::UNC_I_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_irp::unc_i_tickles:lost_ownership", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x116, ++ .fstr = "ivbep_unc_irp::UNC_I_TICKLES:LOST_OWNERSHIP:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_irp::unc_i_transactions:reads", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x115, ++ .fstr = "ivbep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_irp::unc_i_transactions:reads:c=1:i", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_irp::unc_i_transactions:reads:t=6", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x6000115, ++ .fstr = "ivbep_unc_irp::UNC_I_TRANSACTIONS:READS:e=0:t=6", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo1::UNC_C_CLOCKTICKS:u", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x00, ++ .fstr = "ivbep_unc_cbo0::UNC_C_CLOCKTICKS", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x334, ++ .codes[1] = 0x7e0000, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x1134, ++ .codes[1] = 0x7e0000, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIF:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:nf=3", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x5134, ++ .codes[1] = 0x7e0000, ++ .codes[2] = 0x3, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:NID:STATE_MESIF:e=0:t=0:tf=0:nf=3", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M:tid=1", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:WRITE", ++ .ret = PFM_ERR_FEATCOMB, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:nf=3:tf=1:e:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x10c4534, ++ .codes[1] = 0x7e0001, ++ .codes[2] = 0x3, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_LOOKUP:WRITE:NID:STATE_MESIF:e=1:t=1:tf=1:nf=3", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS", ++ .ret = PFM_ERR_UMASK, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:NID", ++ .ret = PFM_ERR_UMASK, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:NID:nf=1", ++ .ret = PFM_ERR_UMASK, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x137, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x537, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:nf=1", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x4537, ++ .codes[1] = 0x0, ++ .codes[2] = 0x1, ++ .fstr = "ivbep_unc_cbo0::UNC_C_LLC_VICTIMS:STATE_M:STATE_S:NID:e=0:t=0:tf=0:nf=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE", ++ .ret = PFM_ERR_UMASK, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:WB", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1035, ++ .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:WB:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x135, ++ .codes[1] = 0x0, ++ .codes[2] = 0x19400000ull, ++ .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPCODE:OPC_PCIWILF:nf=1", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:nf=1", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x4135, ++ .codes[1] = 0x0, ++ .codes[2] = 0x19e00001ull, ++ .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_PCIRDCUR:e=0:t=0:tf=0:nf=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:OPC_RFO:NID_OPCODE:nf=1", ++ .ret = PFM_SUCCESS, ++ .count = 3, ++ .codes[0] = 0x4135, ++ .codes[1] = 0x0, ++ .codes[2] = 0x18000001ull, ++ .fstr = "ivbep_unc_cbo0::UNC_C_TOR_INSERTS:NID_OPCODE:OPC_RFO:e=0:t=0:tf=0:nf=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8a36, ++ .fstr = "ivbep_unc_cbo0::UNC_C_TOR_OCCUPANCY:MISS_REMOTE:e=0:t=0:tf=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x0, ++ .fstr = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1000000, ++ .fstr = "ivbep_unc_pcu::UNC_P_CLOCKTICKS:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x70, ++ .fstr = "ivbep_unc_pcu::UNC_P_CORE0_TRANSITION_CYCLES:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0xb, ++ .codes[1] = 0x20, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:t=0:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:ff=16", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0xc, ++ .codes[1] = 0x1000, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND1_CYCLES:e=0:t=0:ff=16", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:ff=8", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0xd, ++ .codes[1] = 0x80000, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND2_CYCLES:e=0:t=0:ff=8", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:ff=40", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0xe, ++ .codes[1] = 0x28000000, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND3_CYCLES:e=0:t=0:ff=40", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x4000b, ++ .codes[1] = 0x20, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:t=0:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:t=24", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x1800000b, ++ .codes[1] = 0x20, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=0:t=24:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:ff=32:e:t=4", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x404000b, ++ .codes[1] = 0x20, ++ .fstr = "ivbep_unc_pcu::UNC_P_FREQ_BAND0_CYCLES:e=1:t=4:ff=32", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x4080, ++ .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:t=0" ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8080, ++ .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C3:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "IVBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0xc080, ++ .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:t=0" ++ }, ++ { SRC_LINE, ++ .name = "IVBEP_UNC_PCU::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:t=6", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x6004080, ++ .fstr = "ivbep_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C0:e=0:t=6" ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE10", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x42, ++ .fstr = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE10:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE14", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x46, ++ .fstr = "ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE14:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ha0::UNC_H_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x0, ++ .fstr = "ivbep_unc_ha0::UNC_H_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ha1::UNC_H_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x0, ++ .fstr = "ivbep_unc_ha1::UNC_H_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ha1::UNC_H_REQUESTS:READS:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1000301, ++ .fstr = "ivbep_unc_ha1::UNC_H_REQUESTS:READS:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ha0::UNC_H_IMC_WRITES:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1000f1a, ++ .fstr = "ivbep_unc_ha0::UNC_H_IMC_WRITES:ALL:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ha0::UNC_H_IMC_READS:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1000117, ++ .fstr = "ivbep_unc_ha0::UNC_H_IMC_READS:NORMAL:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0xff, ++ .fstr = "ivbep_unc_imc0::UNC_M_CLOCKTICKS", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_CLOCKTICKS:t=1", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_DCLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x00, ++ .fstr = "ivbep_unc_imc0::UNC_M_DCLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc4::UNC_M_DCLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x00, ++ .fstr = "ivbep_unc_imc4::UNC_M_DCLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_CAS_COUNT:RD", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x0304, ++ .fstr = "ivbep_unc_imc0::UNC_M_CAS_COUNT:RD:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x183, ++ .fstr = "ivbep_unc_imc0::UNC_M_POWER_CKE_CYCLES:RANK0:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_CAS_COUNT:WR", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0xc04, ++ .fstr = "ivbep_unc_imc0::UNC_M_CAS_COUNT:WR:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1b0, ++ .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK0:BANK0:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x80b4, ++ .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x10080b4, ++ .fstr = "ivbep_unc_imc0::UNC_M_RD_CAS_RANK4:BANK7:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x14, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x201, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:DATA:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:t=1", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1000101, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G0:IDLE:e=0:t=1", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x200, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G0:DATA:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x200602, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_RXL_FLITS_G1:HOM:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x200600, ++ .fstr = "ivbep_unc_qpi0::UNC_Q_TXL_FLITS_G1:HOM:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_ubo::UNC_U_LOCK_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x44, ++ .fstr = "ivbep_unc_ubo::UNC_U_LOCK_CYCLES:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r2pcie::UNC_R2_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1, ++ .fstr = "ivbep_unc_r2pcie::UNC_R2_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r2pcie::UNC_R2_RING_AD_USED:CW", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x3307, ++ .fstr = "ivbep_unc_r2pcie::UNC_R2_RING_AD_USED:CW:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r3qpi0::UNC_R3_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1, ++ .fstr = "ivbep_unc_r3qpi0::UNC_R3_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x25, ++ .fstr = "ivbep_unc_r3qpi0::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r3qpi1::UNC_R3_CLOCKTICKS", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x1, ++ .fstr = "ivbep_unc_r3qpi1::UNC_R3_CLOCKTICKS:e=0:t=0", ++ }, ++ { SRC_LINE, ++ .name = "ivbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x25, ++ .fstr = "ivbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", ++ }, + }; ++ + #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) + + static int + +commit b4b234e6191fc2a9add4d4088a4e7ba2178ec881 +Author: Stephane Eranian +Date: Wed Mar 12 23:41:42 2014 +0100 + + update event table + + - added missin INT_MISC event + - added DSB2MITE_SWITCHES:PENALTY_CYCLES + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_ivb_events.h b/lib/events/intel_ivb_events.h +index 28e0216..4e1b600 100644 +--- a/lib/events/intel_ivb_events.h ++++ b/lib/events/intel_ivb_events.h +@@ -286,7 +286,12 @@ static const intel_x86_umask_t ivb_cpu_clk_unhalted[]={ + static const intel_x86_umask_t ivb_dsb2mite_switches[]={ + { .uname = "COUNT", + .udesc = "Number of DSB to MITE switches", +- .ucode = 0x100, ++ .ucode = 0x0100, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "PENALTY_CYCLES", ++ .udesc = "Number of DSB to MITE switch true penalty cycles", ++ .ucode = 0x0200, + .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + }; +@@ -1652,6 +1657,20 @@ static const intel_x86_umask_t ivb_lsd[]={ + }, + }; + ++static const intel_x86_umask_t ivb_int_misc[]={ ++ { .uname = "RECOVERY_CYCLES", ++ .udesc = "Number of cycles waiting for Machine Clears except JEClear", ++ .ucode = 0x300, ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "RECOVERY_STALLS_COUNT", ++ .udesc = "Number of occurrences waiting for Machine Clears", ++ .ucode = 0x300 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ ++ .uflags = INTEL_X86_NCOMBO, ++ .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, ++ }, ++}; ++ + static const intel_x86_entry_t intel_ivb_pe[]={ + { .name = "ARITH", + .desc = "Counts arithmetic multiply operations", +@@ -2297,6 +2316,15 @@ static const intel_x86_entry_t intel_ivb_pe[]={ + .ngrp = 1, + .umasks = ivb_lsd, + }, ++ { .name = "INT_MISC", ++ .desc = "Miscellaneous interruptions", ++ .code = 0xd, ++ .cntmsk = 0xff, ++ .ngrp = 1, ++ .modmsk = INTEL_V3_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(ivb_int_misc), ++ .umasks = ivb_int_misc ++ }, + { .name = "OFFCORE_RESPONSE_0", + .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", + .modmsk = INTEL_V3_ATTRS, + +commit a2e7213dc9e0a3f6736e6149a21cee089a604714 +Author: Stephane Eranian +Date: Wed Mar 12 23:42:32 2014 +0100 + + add DSB2MITE_SWITCHES event + + Was missing and is public. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 0491fdd..78b2800 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -1737,6 +1737,14 @@ static const intel_x86_umask_t hsw_lsd[]={ + }, + }; + ++static const intel_x86_umask_t hsw_dsb2mite_switches[]={ ++ { .uname = "PENALTY_CYCLES", ++ .udesc = "Number of DSB to MITE switch true penalty cycles", ++ .ucode = 0x0200, ++ .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++}; ++ + static const intel_x86_entry_t intel_hsw_pe[]={ + { .name = "UNHALTED_CORE_CYCLES", + .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", +@@ -2301,6 +2309,15 @@ static const intel_x86_entry_t intel_hsw_pe[]={ + .ngrp = 1, + .umasks = hsw_page_walker_loads, + }, ++{ .name = "DSB2MITE_SWITCHES", ++ .desc = "Number of DSB to MITE switches", ++ .modmsk = INTEL_V4_ATTRS, ++ .cntmsk = 0xff, ++ .code = 0xab, ++ .numasks = LIBPFM_ARRAY_SIZE(hsw_dsb2mite_switches), ++ .ngrp = 1, ++ .umasks = hsw_dsb2mite_switches, ++}, + { .name = "OFFCORE_RESPONSE_0", + .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", + .modmsk = INTEL_V4_ATTRS, + +commit e48874920d8efe93c3167afe6d17cbc282937eb4 +Author: Steve Kaufmann +Date: Fri Apr 11 10:14:04 2014 +0200 + + fix more spelling mistakes + + This patch fixes spelling mistakes in event description tables. + + Signed-off-by: Steve Kaufmann + +diff --git a/lib/events/amd64_events_fam11h.h b/lib/events/amd64_events_fam11h.h +index 5760e26..b53e7f6 100644 +--- a/lib/events/amd64_events_fam11h.h ++++ b/lib/events/amd64_events_fam11h.h +@@ -1033,7 +1033,7 @@ static const amd64_entry_t amd64_fam11h_pe[]={ + .umasks = amd64_fam11h_system_read_responses, + }, + { .name = "QUADWORDS_WRITTEN_TO_SYSTEM", +- .desc = "Quawords Written to System", ++ .desc = "Quadwords Written to System", + .modmsk = AMD64_FAM10H_ATTRS, + .code = 0x6d, + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_quadwords_written_to_system), +diff --git a/lib/events/amd64_events_fam14h.h b/lib/events/amd64_events_fam14h.h +index 0cf11a9..905094a 100644 +--- a/lib/events/amd64_events_fam14h.h ++++ b/lib/events/amd64_events_fam14h.h +@@ -1076,7 +1076,7 @@ static const amd64_entry_t amd64_fam14h_pe[]={ + .code = 0x22, + }, + { .name = "RSQ_FULL", +- .desc = "Number of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cacge and waiting on a refill", ++ .desc = "Number of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cache and waiting on a refill", + .modmsk = AMD64_FAM10H_ATTRS, + .code = 0x23, + }, +diff --git a/lib/events/intel_coreduo_events.h b/lib/events/intel_coreduo_events.h +index 9e0cb5e..33531cf 100644 +--- a/lib/events/intel_coreduo_events.h ++++ b/lib/events/intel_coreduo_events.h +@@ -525,7 +525,7 @@ static const intel_x86_entry_t intel_coreduo_pe[]={ + .umasks = coreduo_l2_ads, + }, + { .name = "DBUS_BUSY", +- .desc = "Core cycle during which data buswas busy (increments by 4)", ++ .desc = "Core cycle during which data bus was busy (increments by 4)", + .modmsk = INTEL_X86_ATTRS, + .cntmsk = 0x3, + .code = 0x22, +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 78b2800..fee2a65 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -410,12 +410,12 @@ static const intel_x86_umask_t hsw_idq[]={ + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS_DSB_UOPS", +- .udesc = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", ++ .udesc = "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + .ucode = 0x1000, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS_MITE_UOPS", +- .udesc = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", ++ .udesc = "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + .ucode = 0x2000, + .uflags = INTEL_X86_NCOMBO, + }, +@@ -446,14 +446,14 @@ static const intel_x86_umask_t hsw_idq[]={ + .modhw = _INTEL_X86_ATTR_C, + }, + { .uname = "MS_DSB_UOPS_CYCLES", +- .udesc = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", ++ .udesc = "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + .ucode = 0x1000 | (1 << INTEL_X86_CMASK_BIT), /* cnt=1 */ + .uequiv = "MS_DSB_UOPS:c=1", + .uflags = INTEL_X86_NCOMBO, + .modhw = _INTEL_X86_ATTR_C, + }, + { .uname = "MS_DSB_OCCUR", +- .udesc = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", ++ .udesc = "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", + .ucode = 0x1000 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ + .uequiv = "MS_DSB_UOPS:c=1:e=1", + .uflags = INTEL_X86_NCOMBO, +diff --git a/lib/events/intel_ivbep_unc_cbo_events.h b/lib/events/intel_ivbep_unc_cbo_events.h +index ee8959f..318521d 100644 +--- a/lib/events/intel_ivbep_unc_cbo_events.h ++++ b/lib/events/intel_ivbep_unc_cbo_events.h +@@ -228,7 +228,7 @@ static const intel_x86_umask_t ivbep_unc_c_llc_victims[]={ + + static const intel_x86_umask_t ivbep_unc_c_ring_ad_used[]={ + { .uname = "UP_VR0_EVEN", +- .udesc = "Up and Even ring polarity filter on virutal ring 0", ++ .udesc = "Up and Even ring polarity filter on virtual ring 0", + .ucode = 0x100, + }, + { .uname = "UP_VR0_ODD", +@@ -244,7 +244,7 @@ static const intel_x86_umask_t ivbep_unc_c_ring_ad_used[]={ + .ucode = 0x800, + }, + { .uname = "UP_VR1_EVEN", +- .udesc = "Up and Even ring polarity filter on virutal ring 1", ++ .udesc = "Up and Even ring polarity filter on virtual ring 1", + .ucode = 0x1000, + }, + { .uname = "UP_VR1_ODD", +@@ -786,7 +786,7 @@ static const intel_x86_umask_t ivbep_unc_c_misc[]={ + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_HIT_S", +- .udesc = "Counts the number of times that an RFO hits in S state. This is usfeul for determining if it might be good for a workload to use RSPIWB instead of RSPSWB", ++ .udesc = "Counts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWB", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +@@ -827,7 +827,7 @@ static const intel_x86_entry_t intel_ivbep_unc_c_pe[]={ + .umasks = ivbep_unc_c_llc_victims, + }, + { .name = "UNC_C_MISC", +- .desc = "Miscelleanous C-Box events", ++ .desc = "Miscellaneous C-Box events", + .modmsk = IVBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x39, +diff --git a/lib/events/intel_ivbep_unc_ha_events.h b/lib/events/intel_ivbep_unc_ha_events.h +index 58f0e06..d92ca9e 100644 +--- a/lib/events/intel_ivbep_unc_ha_events.h ++++ b/lib/events/intel_ivbep_unc_ha_events.h +@@ -568,11 +568,11 @@ static const intel_x86_umask_t ivbep_unc_h_snp_resp_recv_local[]={ + + static const intel_x86_umask_t ivbep_unc_h_tracker_cycles_full[]={ + { .uname = "GP", +- .udesc = "Number of cycles when the general purpose (GP) HA trakcer pool is completely used. It will not return valid count when BT is disabled", ++ .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used. It will not return valid count when BT is disabled", + .ucode = 0x100, + }, + { .uname = "ALL", +- .udesc = "Number of cycles when the general purpose (GP) HA trakcer pool is completely used including reserved HT entries. It will not return vaid count when BT is disabled", ++ .udesc = "Number of cycles when the general purpose (GP) HA tracker pool is completely used including reserved HT entries. It will not return vaid count when BT is disabled", + .ucode = 0x200, + .uflags = INTEL_X86_DFL, + }, +diff --git a/lib/events/intel_ivbep_unc_imc_events.h b/lib/events/intel_ivbep_unc_imc_events.h +index ac8ef41..473afc4 100644 +--- a/lib/events/intel_ivbep_unc_imc_events.h ++++ b/lib/events/intel_ivbep_unc_imc_events.h +@@ -80,7 +80,7 @@ static const intel_x86_umask_t ivbep_unc_m_dram_refresh[]={ + + static const intel_x86_umask_t ivbep_unc_m_major_modes[]={ + { .uname = "ISOCH", +- .udesc = "Counts cycles in ISOCH Major maode", ++ .udesc = "Counts cycles in ISOCH Major mode", + .ucode = 0x800, + }, + { .uname = "PARTIAL", +diff --git a/lib/events/intel_ivbep_unc_irp_events.h b/lib/events/intel_ivbep_unc_irp_events.h +index 86b5168..19c8512 100644 +--- a/lib/events/intel_ivbep_unc_irp_events.h ++++ b/lib/events/intel_ivbep_unc_irp_events.h +@@ -33,7 +33,7 @@ static const intel_x86_umask_t ivbep_unc_i_address_match[]={ + .ucode = 0x100, + }, + { .uname = "MERGE_COUNT", +- .udesc = "Number of times when two reuqests to the same address from the same source are received back to back, it is possible to merge them", ++ .udesc = "Number of times when two requests to the same address from the same source are received back to back, it is possible to merge them", + .ucode = 0x200, + }, + }; +diff --git a/lib/events/intel_ivbep_unc_r2pcie_events.h b/lib/events/intel_ivbep_unc_r2pcie_events.h +index 59d96b9..081aaf2 100644 +--- a/lib/events/intel_ivbep_unc_r2pcie_events.h ++++ b/lib/events/intel_ivbep_unc_r2pcie_events.h +@@ -188,7 +188,7 @@ static const intel_x86_entry_t intel_ivbep_unc_r2_pe[]={ + .umasks = ivbep_unc_r2_rxr_ak_bounces + }, + { .name = "UNC_R2_RXR_OCCUPANCY", +- .desc = "Ingress occpancy accumulator", ++ .desc = "Ingress occupancy accumulator", + .code = 0x13, + .cntmsk = 0x1, + .modmsk = IVBEP_UNC_R2PCIE_ATTRS, +diff --git a/lib/events/intel_p6_events.h b/lib/events/intel_p6_events.h +index f8a83a8..6964eff 100644 +--- a/lib/events/intel_p6_events.h ++++ b/lib/events/intel_p6_events.h +@@ -216,7 +216,7 @@ static const intel_x86_entry_t intel_p6_pe[]={ + .code = 0x85, + }, + { .name = "IFU_MEM_STALL", +- .desc = "Number of cycles instruction fetch is stalled for any reason. Includs IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", ++ .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", + .modmsk = INTEL_X86_ATTRS, + .cntmsk = 0x3, + .code = 0x86, +diff --git a/lib/events/intel_pii_events.h b/lib/events/intel_pii_events.h +index 5846c64..5c614c0 100644 +--- a/lib/events/intel_pii_events.h ++++ b/lib/events/intel_pii_events.h +@@ -180,7 +180,7 @@ static const intel_x86_entry_t intel_pii_pe[]={ + .code = 0x85, + }, + { .name = "IFU_MEM_STALL", +- .desc = "Number of cycles instruction fetch is stalled for any reason. Includs IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", ++ .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", + .modmsk = INTEL_X86_ATTRS, + .cntmsk = 0x3, + .code = 0x86, +diff --git a/lib/events/intel_pm_events.h b/lib/events/intel_pm_events.h +index e32a883..1bbefdb 100644 +--- a/lib/events/intel_pm_events.h ++++ b/lib/events/intel_pm_events.h +@@ -283,7 +283,7 @@ static const intel_x86_entry_t intel_pm_pe[]={ + .code = 0x85, + }, + { .name = "IFU_MEM_STALL", +- .desc = "Number of cycles instruction fetch is stalled for any reason. Includs IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", ++ .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", + .modmsk = INTEL_X86_ATTRS, + .cntmsk = 0x3, + .code = 0x86, +diff --git a/lib/events/intel_ppro_events.h b/lib/events/intel_ppro_events.h +index 0555652..d0b9df6 100644 +--- a/lib/events/intel_ppro_events.h ++++ b/lib/events/intel_ppro_events.h +@@ -121,7 +121,7 @@ static const intel_x86_entry_t intel_ppro_pe[]={ + .code = 0x85, + }, + { .name = "IFU_MEM_STALL", +- .desc = "Number of cycles instruction fetch is stalled for any reason. Includs IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", ++ .desc = "Number of cycles instruction fetch is stalled for any reason. Includes IFU cache misses, ITLB misses, ITLB faults, and other minor stalls", + .modmsk = INTEL_X86_ATTRS, + .cntmsk = 0x3, + .code = 0x86, +diff --git a/lib/events/intel_slm_events.h b/lib/events/intel_slm_events.h +index 558dbf8..c7b5ce7 100644 +--- a/lib/events/intel_slm_events.h ++++ b/lib/events/intel_slm_events.h +@@ -97,7 +97,7 @@ static const intel_x86_umask_t slm_inst_retired[]={ + + static const intel_x86_umask_t slm_l2_reject_xq[]={ + { .uname = "ALL", +- .udesc = "Number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions fro mthe L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)", ++ .udesc = "Number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)", + .ucode = 0x000, + .uflags= INTEL_X86_DFL, + }, +diff --git a/lib/events/intel_snbep_unc_cbo_events.h b/lib/events/intel_snbep_unc_cbo_events.h +index 40d3e37..ae10b61 100644 +--- a/lib/events/intel_snbep_unc_cbo_events.h ++++ b/lib/events/intel_snbep_unc_cbo_events.h +@@ -580,7 +580,7 @@ static const intel_x86_umask_t snbep_unc_c_txr_inserts[]={ + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_CACHE", +- .udesc = "Counts the number of ring transactions from Cachebo ton IV ring", ++ .udesc = "Counts the number of ring transactions from Cachebo to IV ring", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, +@@ -701,7 +701,7 @@ static const intel_x86_entry_t intel_snbep_unc_c_pe[]={ + .code = 0x07, + }, + { .name = "UNC_C_RXR_EXT_STARVED", +- .desc = "Ingress arbiter blockig cycles", ++ .desc = "Ingress arbiter blocking cycles", + .modmsk = SNBEP_UNC_CBO_ATTRS, + .cntmsk = 0x3, + .code = 0x12, +diff --git a/lib/events/intel_snbep_unc_imc_events.h b/lib/events/intel_snbep_unc_imc_events.h +index e2494b2..b49487c 100644 +--- a/lib/events/intel_snbep_unc_imc_events.h ++++ b/lib/events/intel_snbep_unc_imc_events.h +@@ -78,7 +78,7 @@ static const intel_x86_umask_t snbep_unc_m_dram_refresh[]={ + + static const intel_x86_umask_t snbep_unc_m_major_modes[]={ + { .uname = "ISOCH", +- .udesc = "Counts cycles in ISOCH Major maode", ++ .udesc = "Counts cycles in ISOCH Major mode", + .ucode = 0x800, + .uflags = INTEL_X86_NCOMBO, + }, + +commit 42c3455dd1a51804c854d7ce651434df7701f4c2 +Author: Stephane Eranian +Date: Wed Apr 16 17:49:58 2014 +0200 + + add Intel Haswell event alias for MEM_LOAD_UOPS_L3_* + + To be more consistent with IvyBridge: + + MEM_LOAD_UOPS_LLC_HIT_RETIRED = MEM_LOAD_UOPS_L3_HIT_RETIRED + MEM_LOAD_UOPS_LLC_MISS_RETIRED = MEM_LOAD_UOPS_L3_MISS_RETIRED + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index fee2a65..8706634 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -2095,6 +2095,17 @@ static const intel_x86_entry_t intel_hsw_pe[]={ + .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_hit_retired), + .umasks = hsw_mem_load_uops_l3_hit_retired + }, ++ { .name = "MEM_LOAD_UOPS_LLC_HIT_RETIRED", ++ .desc = "L3 hit load uops retired (Precise Event)", ++ .equiv = "MEM_LOAD_UOPS_L3_HIT_RETIRED", ++ .code = 0xd2, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .flags = INTEL_X86_PEBS, ++ .modmsk = INTEL_V4_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_hit_retired), ++ .umasks = hsw_mem_load_uops_l3_hit_retired ++ }, + { .name = "MEM_LOAD_UOPS_L3_MISS_RETIRED", + .desc = "Load uops retired that missed the L3 (Precise Event)", + .code = 0xd3, +@@ -2105,6 +2116,17 @@ static const intel_x86_entry_t intel_hsw_pe[]={ + .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_miss_retired), + .umasks = hsw_mem_load_uops_l3_miss_retired + }, ++ { .name = "MEM_LOAD_UOPS_LLC_MISS_RETIRED", ++ .desc = "Load uops retired that missed the L3 (Precise Event)", ++ .equiv = "MEM_LOAD_UOPS_L3_MISS_RETIRED", ++ .code = 0xd3, ++ .cntmsk = 0xf, ++ .ngrp = 1, ++ .flags = INTEL_X86_PEBS, ++ .modmsk = INTEL_V4_ATTRS, ++ .numasks = LIBPFM_ARRAY_SIZE(hsw_mem_load_uops_l3_miss_retired), ++ .umasks = hsw_mem_load_uops_l3_miss_retired ++ }, + { .name = "MEM_LOAD_UOPS_RETIRED", + .desc = "Retired load uops (Precise Event)", + .code = 0xd1, + +commit 89daf8f981e8ba70447cd16fca4f5715dbb99b14 +Author: Stephane Eranian +Date: Thu Apr 17 16:39:43 2014 +0200 + + Add Intel Haswell L1D_PEND_MISS.EDGE alias + + Alias to L1D_PEND_MISS.OCCURRENCES to be consistent with IvyBridge + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 8706634..8ec1165 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -578,6 +578,14 @@ static const intel_x86_umask_t hsw_l1d_pend_miss[]={ + .uflags = INTEL_X86_NCOMBO, + .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, + }, ++ { .uname = "EDGE", ++ .udesc = "Number L1D miss outstanding", ++ .ucode = 0x100 | INTEL_X86_MOD_EDGE | (1 << INTEL_X86_CMASK_BIT), /* edge=1 cnt=1 */ ++ .uequiv = "PENDING:c=1:e=1", ++ .ucntmsk = 0x4, ++ .uflags = INTEL_X86_NCOMBO, ++ .modhw = _INTEL_X86_ATTR_E | _INTEL_X86_ATTR_C, ++ }, + }; + + static const intel_x86_umask_t hsw_l2_demand_rqsts[]={ + +commit 1c324233cc97f99195557a1c4658c93f4939cd96 +Author: Steve Kaufmann +Date: Thu Apr 17 16:43:31 2014 +0200 + + more spelling fixes + + In man pages this time. + + Signed-off-by: Steve Kaufmann + +diff --git a/docs/man3/libpfm_amd64_fam15h.3 b/docs/man3/libpfm_amd64_fam15h.3 +index 84ae455..ac594c2 100644 +--- a/docs/man3/libpfm_amd64_fam15h.3 ++++ b/docs/man3/libpfm_amd64_fam15h.3 +@@ -12,7 +12,7 @@ libpfm_amd64_fam15h - support for AMD64 Family 15h processors + .sp + .SH DESCRIPTION + The library supports AMD Family 15h processors core PMU in both 32 and 64-bit modes. The +-uncore PMU (Northbridge) is also supported as a separate PMU model. ++uncore (NorthBridge) PMU is also supported as a separate PMU model. + + .SH MODIFIERS + The following modifiers are supported on AMD64 Family 15h core PMU: +diff --git a/docs/man3/libpfm_intel_ivb_unc.3 b/docs/man3/libpfm_intel_ivb_unc.3 +index 1e9921f..5176ee7 100644 +--- a/docs/man3/libpfm_intel_ivb_unc.3 ++++ b/docs/man3/libpfm_intel_ivb_unc.3 +@@ -13,7 +13,7 @@ The library supports the Intel Ivy Bridge client part (model 58) uncore PMU. + The support is currently limited to the Coherency Box, so called C-Box for up + to 4 physical cores. + +-Each physical core has an associated C-Box which it uses to communictate with ++Each physical core has an associated C-Box which it uses to communicate with + the L3 cache. The C-boxes all support the same set of events. However, Core 0 + C-box (snb_unc_cbo0) supports an additional uncore clock ticks event: \fBUNC_CLOCKTICKS\fR. + +diff --git a/docs/man3/libpfm_intel_ivbep_unc_cbo.3 b/docs/man3/libpfm_intel_ivbep_unc_cbo.3 +index e417a46..b6023b7 100644 +--- a/docs/man3/libpfm_intel_ivbep_unc_cbo.3 ++++ b/docs/man3/libpfm_intel_ivbep_unc_cbo.3 +@@ -36,11 +36,11 @@ the threshold. This is an integer modifier with values in the range [0:255]. + Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. + Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. + The node filter is an 8-bit max bitmask. A node corresponds to a processor +-socket. The legal values therefore depdend on the underlying hardware configuration. For ++socket. The legal values therefore depend on the underlying hardware configuration. For + dual-socket systems, the bitmask has two valid bits [0:1]. + .TP + .B cf +-Core Filter. This is a 3-bit filter which is used to filter based on phyiscal core origin ++Core Filter. This is a 3-bit filter which is used to filter based on physical core origin + of the C-Box request. Possible values are 0-7. If the filter is not specified, then no + filtering takes place. + .TP +@@ -53,7 +53,7 @@ specified, then no filtering takes place. + + Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction + type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. +-Second, the opcode to match on must be selected via a second umasks amongs the OPC_* umasks. ++Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. + For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO + transactions. + +diff --git a/docs/man3/libpfm_intel_ivbep_unc_pcu.3 b/docs/man3/libpfm_intel_ivbep_unc_pcu.3 +index 65ec6a3..399824c 100644 +--- a/docs/man3/libpfm_intel_ivbep_unc_pcu.3 ++++ b/docs/man3/libpfm_intel_ivbep_unc_pcu.3 +@@ -26,7 +26,7 @@ the threshold. This is an integer modifier with values in the range [0:15]. + .B ff + Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. + The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +-multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are + counted. + + .SH Frequency band filtering +diff --git a/docs/man3/libpfm_intel_ivbep_unc_ubo.3 b/docs/man3/libpfm_intel_ivbep_unc_ubo.3 +index 2c4a6c1..8b4024d 100644 +--- a/docs/man3/libpfm_intel_ivbep_unc_ubo.3 ++++ b/docs/man3/libpfm_intel_ivbep_unc_ubo.3 +@@ -36,7 +36,7 @@ modifier (t) with a value greater or equal to one. This is a boolean modifier. + .B ff + Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. + The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +-multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are + counted. + + .SH Frequency band filtering +diff --git a/docs/man3/libpfm_intel_rapl.3 b/docs/man3/libpfm_intel_rapl.3 +index cf7835c..d5e6227 100644 +--- a/docs/man3/libpfm_intel_rapl.3 ++++ b/docs/man3/libpfm_intel_rapl.3 +@@ -10,7 +10,7 @@ libpfm_intel_rapl - support for Intel RAPL PMU + .sp + .SH DESCRIPTION + The library supports the Intel Running Average Power Limit (RAPL) +-energy consomption counters. This is a socket-level set of counters ++energy consumption counters. This is a socket-level set of counters + which reports energy consumption in Joules. There are up to 3 counters + each measuring only one event. The following events are defined: + .TP +diff --git a/docs/man3/libpfm_intel_snb_unc.3 b/docs/man3/libpfm_intel_snb_unc.3 +index 9591832..c0ba38d 100644 +--- a/docs/man3/libpfm_intel_snb_unc.3 ++++ b/docs/man3/libpfm_intel_snb_unc.3 +@@ -13,7 +13,7 @@ The library supports the Intel Sandy Bridge client part (model 42) uncore PMU. + The support is currently limited to the Coherency Box, so called C-Box for up + to 4 physical cores. + +-Each physical core has an associated C-Box which it uses to communictate with ++Each physical core has an associated C-Box which it uses to communicate with + the L3 cache. The C-boxes all support the same set of events. However, Core 0 + C-box (snb_unc_cbo0) supports an additional uncore clock ticks event: \fBUNC_CLOCKTICKS\fR. + +diff --git a/docs/man3/libpfm_intel_snbep_unc_cbo.3 b/docs/man3/libpfm_intel_snbep_unc_cbo.3 +index 24fd517..6281ed1 100644 +--- a/docs/man3/libpfm_intel_snbep_unc_cbo.3 ++++ b/docs/man3/libpfm_intel_snbep_unc_cbo.3 +@@ -40,11 +40,11 @@ the threshold. This is an integer modifier with values in the range [0:255]. + Node filter. Certain events, such as UNC_C_LLC_LOOKUP, UNC_C_LLC_VICTIMS, provide a \fBNID\fR umask. + Sometimes the \fBNID\fR is combined with other filtering capabilities, such as opcodes. + The node filter is an 8-bit max bitmask. A node corresponds to a processor +-socket. The legal values therefore depdend on the underlying hardware configuration. For ++socket. The legal values therefore depend on the underlying hardware configuration. For + dual-socket systems, the bitmask has two valid bits [0:1]. + .TP + .B cf +-Core Filter. This is a 3-bit filter which is used to filter based on phyiscal core origin ++Core Filter. This is a 3-bit filter which is used to filter based on physical core origin + of the C-Box request. Possible values are 0-7. If the filter is not specified, then no + filtering takes place. + .TP +@@ -57,7 +57,7 @@ specified, then no filtering takes place. + + Certain events, such as UNC_C_TOR_INSERTS supports opcode matching on the C-BOX transaction + type. To use this feature, first an opcode matching umask must be selected, e.g., MISS_OPCODE. +-Second, the opcode to match on must be selected via a second umasks amongs the OPC_* umasks. ++Second, the opcode to match on must be selected via a second umask among the OPC_* umasks. + For instance, UNC_C_TOR_INSERTS:OPCODE:OPC_RFO, counts the number of TOR insertions for RFO + transactions. + +diff --git a/docs/man3/libpfm_intel_snbep_unc_pcu.3 b/docs/man3/libpfm_intel_snbep_unc_pcu.3 +index 47ea498..9675cd5 100644 +--- a/docs/man3/libpfm_intel_snbep_unc_pcu.3 ++++ b/docs/man3/libpfm_intel_snbep_unc_pcu.3 +@@ -31,7 +31,7 @@ the threshold. This is an integer modifier with values in the range [0:15]. + .B ff + Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. + The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +-multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are + counted. + + .SH Frequency band filtering +diff --git a/docs/man3/libpfm_intel_snbep_unc_ubo.3 b/docs/man3/libpfm_intel_snbep_unc_ubo.3 +index afd246e..97b5fa8 100644 +--- a/docs/man3/libpfm_intel_snbep_unc_ubo.3 ++++ b/docs/man3/libpfm_intel_snbep_unc_ubo.3 +@@ -41,7 +41,7 @@ modifier (t) with a value greater or equal to one. This is a boolean modifier. + .B ff + Enable frequency band filtering. This modifier applies only to the UNC_P_FREQ_BANDx_CYCLES events, where x is [0-3]. + The modifiers expects an integer in the range [0-255]. The value is interpreted as a frequency value to be +-multipled by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are ++multiplied by 100Mhz. Thus if the value is 32, then all cycles where the processor is running at 3.2GHz and more are + counted. + + .SH Frequency band filtering +diff --git a/docs/man3/libpfm_perf_event_raw.3 b/docs/man3/libpfm_perf_event_raw.3 +index 2f8b535..fa1f70f 100644 +--- a/docs/man3/libpfm_perf_event_raw.3 ++++ b/docs/man3/libpfm_perf_event_raw.3 +@@ -22,7 +22,7 @@ The syntax is very simple: rX. X is the hexadecimal 64-bit value for the event. + It may include event filters on some PMU models. The hexadecimal number is passed + without the 0x prefix, e.g., r01c4. + +-The library's standard perf_events attributes are supported oby this PMU model. ++The library's standard perf_events attributes are supported by this PMU model. + They are separated with colons as is customary with the library. + + .SH MODIFIERS +@@ -59,7 +59,7 @@ event should be sampled 100 times per second on average. There is no default val + .TP + .B excl + The associated event is the only event measured on the PMU. This applies only to hardware +-events. This atrtribute requires admin privileges. Default is off. ++events. This attribute requires admin privileges. Default is off. + .TP + .B precise + Enables precise sampling mode. This option is only valid on sampling events. This is an +diff --git a/docs/man3/pfm_find_event.3 b/docs/man3/pfm_find_event.3 +index 0ac2a42..7a52c41 100644 +--- a/docs/man3/pfm_find_event.3 ++++ b/docs/man3/pfm_find_event.3 +@@ -16,7 +16,7 @@ and try to find the matching event. + + The event string is a structured string and it is composed as follows: + .TP +-.B [pmu_name::]event_name[:unit_mask][:modifer|:modifier=val] ++.B [pmu_name::]event_name[:unit_mask][:modifier|:modifier=val] + .PP + + The various components are separated by \fB:\fR or \fB::\fR, they +@@ -24,7 +24,7 @@ are defined as follows: + + .TP + .B pmu_name +-This is an optional prefix to designte a specific PMU model. With the ++This is an optional prefix to designate a specific PMU model. With the + prefix the event which matches the event_name is used. In case multiple + PMU models are activated, there may be conflict with identical event + names to mean the same or different things. In that case, it is necessary +diff --git a/docs/man3/pfm_get_event_next.3 b/docs/man3/pfm_get_event_next.3 +index 3a14af6..386ac03 100644 +--- a/docs/man3/pfm_get_event_next.3 ++++ b/docs/man3/pfm_get_event_next.3 +@@ -25,7 +25,7 @@ when encoding events. + + To iterate over a list of events for a given PMU model, all that is + needed is an initial identifier for the PMU. The first event identifier +-is usually obainted via \fBpfm_get_pmu_info()\fR. ++is usually obtained via \fBpfm_get_pmu_info()\fR. + + The \fBpfm_get_event_next()\fR function returns the identifier of + next supported event after the one passed in \fBidx\fR. This iterator + +commit 285a80941e04e17f66c3322a2741bb27766a0373 +Author: Stephane Eranian +Date: Fri Apr 18 14:54:54 2014 +0200 + + add more HSW umask aliases to match IVB + + Ths patch adds some more umask aliases + to the following events to maintain compat + with IvyBridge: + - L2_RQSTS + - BR_MISP_EXEC + - BR_MISP_RETIRED + - BR_INST_RETIRED + - BR_INST_EXEC + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 8ec1165..b4e7c00 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -38,11 +38,24 @@ static const intel_x86_umask_t hsw_br_inst_exec[]={ + .ucode = 0x4100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "NONTAKEN_COND", ++ .udesc = "All macro conditional nontaken branch instructions", ++ .ucode = 0x4100, ++ .uequiv = "NONTAKEN_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ + { .uname = "TAKEN_CONDITIONAL", + .udesc = "Taken speculative and retired macro-conditional branches", + .ucode = 0x8100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "TAKEN_COND", ++ .udesc = "Taken speculative and retired macro-conditional branches", ++ .ucode = 0x8100, ++ .uequiv = "TAKEN_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "TAKEN_DIRECT_JUMP", + .udesc = "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + .ucode = 0x8200, +@@ -68,6 +81,18 @@ static const intel_x86_umask_t hsw_br_inst_exec[]={ + .ucode = 0xc100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "ALL_COND", ++ .udesc = "Speculative and retired macro-conditional branches", ++ .ucode = 0xc100, ++ .uequiv = "ALL_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, ++ { .uname = "ANY_COND", ++ .udesc = "Speculative and retired macro-conditional branches", ++ .ucode = 0xc100, ++ .uequiv = "ALL_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "ALL_DIRECT_JMP", + .udesc = "Speculative and retired macro-unconditional branches excluding calls and indirects", + .ucode = 0xc200, +@@ -106,6 +131,12 @@ static const intel_x86_umask_t hsw_br_inst_retired[]={ + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, + }, ++ { .uname = "COND", ++ .udesc = "Counts all taken and not taken macro conditional branch instructions", ++ .ucode = 0x100, ++ .uequiv = "CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, ++ }, + { .uname = "NEAR_CALL", + .udesc = "Counts all macro direct and indirect near calls", + .ucode = 0x200, +@@ -144,11 +175,23 @@ static const intel_x86_umask_t hsw_br_misp_exec[]={ + .ucode = 0x4100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "NONTAKEN_COND", ++ .udesc = "Not taken speculative and retired mispredicted macro conditional branches", ++ .ucode = 0x4100, ++ .uequiv = "NONTAKEN_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "TAKEN_CONDITIONAL", + .udesc = "Taken speculative and retired mispredicted macro conditional branches", + .ucode = 0x8100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "TAKEN_COND", ++ .udesc = "Taken speculative and retired mispredicted macro conditional branches", ++ .ucode = 0x8100, ++ .uequiv = "TAKEN_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "TAKEN_INDIRECT_JUMP_NON_CALL_RET", + .udesc = "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + .ucode = 0x8400, +@@ -164,6 +207,12 @@ static const intel_x86_umask_t hsw_br_misp_exec[]={ + .ucode = 0xc100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "ANY_COND", ++ .udesc = "Speculative and retired mispredicted macro conditional branches", ++ .ucode = 0xc100, ++ .uequiv = "ALL_CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "ALL_INDIRECT_JUMP_NON_CALL_RET", + .udesc = "All mispredicted indirect branches that are not calls nor returns", + .ucode = 0xc400, +@@ -187,6 +236,12 @@ static const intel_x86_umask_t hsw_br_misp_retired[]={ + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, + }, ++ { .uname = "COND", ++ .udesc = "All mispredicted macro conditional branch instructions", ++ .ucode = 0x100, ++ .uequiv = "CONDITIONAL", ++ .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, ++ }, + { .uname = "ALL_BRANCHES", + .udesc = "All mispredicted macro branches (architectural event)", + .ucode = 0x0, /* architectural encoding */ +@@ -654,11 +709,23 @@ static const intel_x86_umask_t hsw_l2_rqsts[]={ + .ucode = 0x2200, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "RFO_MISS", ++ .udesc = "RFO requests that miss L2 cache", ++ .ucode = 0x2200, ++ .uequiv = "DEMAND_RFO_MISS", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "DEMAND_RFO_HIT", + .udesc = "RFO requests that hit L2 cache", + .ucode = 0x4200, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "RFO_HIT", ++ .udesc = "RFO requests that hit L2 cache", ++ .ucode = 0x4200, ++ .uequiv = "DEMAND_RFO_HIT", ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "CODE_RD_MISS", + .udesc = "L2 cache misses when fetching instructions", + .ucode = 0x2400, + +commit 92a7428d9153d652456d8728e6c8a67f0d375280 +Author: Stephane Eranian +Date: Mon May 12 21:19:58 2014 +0200 + + add missing Haswell cpu_clk_unhalted:ref_p + + Add missing cpu_clk_unhalted:ref_p as an alias + cpu_clk_unhalted:ref_xclk. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index b4e7c00..028f295 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -279,6 +279,12 @@ static const intel_x86_umask_t hsw_cpu_clk_thread_unhalted[]={ + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "REF_P", ++ .udesc = "Cycles when the core is unhalted (count at 100 Mhz)", ++ .ucode = 0x100, ++ .uequiv = "REF_XCLK", ++ .uflags= INTEL_X86_NCOMBO, ++ }, + { .uname = "THREAD_P", + .udesc = "Cycles when thread is not halted", + .ucode = 0x000, + +commit 58e7a3c6b29f121e9eaf0faf35304957e1d48fdf +Author: Stephane Eranian +Date: Tue Jun 10 21:31:30 2014 +0200 + + remove duplicated ivbep_unc_pcu::UNC_P_DEMOTIONS_CORE14 + + Remove duplicated UNC_P_DEMOTIONS_CORE14 + + Reported-by: James Ralph + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_ivbep_unc_pcu_events.h b/lib/events/intel_ivbep_unc_pcu_events.h +index 14188e5..05b0118 100644 +--- a/lib/events/intel_ivbep_unc_pcu_events.h ++++ b/lib/events/intel_ivbep_unc_pcu_events.h +@@ -338,12 +338,6 @@ static const intel_x86_entry_t intel_ivbep_unc_p_pe[]={ + .cntmsk = 0xf, + .modmsk = IVBEP_UNC_PCU_ATTRS, + }, +- { .name = "UNC_P_DEMOTIONS_CORE14", +- .desc = "Core 14 C State Demotions", +- .code = 0x2d, +- .cntmsk = 0xf, +- .modmsk = IVBEP_UNC_PCU_ATTRS, +- }, + { .name = "UNC_P_FREQ_BAND0_CYCLES", + .desc = "Frequency Residency", + .code = 0xb, + +commit e1d5a2359c6b161a5e5242fe0bfd69f2bce77f2a +Author: Gary Mohr +Date: Sun Jun 15 09:40:09 2014 +0200 + + Fix NID filter for SNB-EP Cbox LLC_LOOKUP, LLC_VICTIMS + + This patch fixes NID management for SNB-EP Cbox + LLC_VICTIMS and LLC_LOOKUP events. + + This patch also adds UNC_C_LLC_LOOKUP:ANY. + + The validation test suite is updated accordingly. + + Signed-off-by: Gary Mohr + +diff --git a/lib/events/intel_snbep_unc_cbo_events.h b/lib/events/intel_snbep_unc_cbo_events.h +index ae10b61..430a47c 100644 +--- a/lib/events/intel_snbep_unc_cbo_events.h ++++ b/lib/events/intel_snbep_unc_cbo_events.h +@@ -162,6 +162,12 @@ + } + + static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ ++ { .uname = "ANY", ++ .udesc = "Any request", ++ .grpid = 0, ++ .uflags = INTEL_X86_NCOMBO, ++ .ucode = 0x1f00, ++ }, + { .uname = "DATA_READ", + .udesc = "Data read requests", + .grpid = 0, +@@ -181,7 +187,7 @@ static const intel_x86_umask_t snbep_unc_c_llc_lookup[]={ + .ucode = 0x900, + }, + { .uname = "NID", +- .udesc = "Match a given RTID destination NID", ++ .udesc = "Match a given RTID destination NID (must provide nf=X modifier)", + .uflags = INTEL_X86_NCOMBO | INTEL_X86_GRP_DFL_NONE, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .grpid = 1, +@@ -208,7 +214,9 @@ static const intel_x86_umask_t snbep_unc_c_llc_victims[]={ + .ucode = 0x800, + }, + { .uname = "NID", +- .udesc = "Victimized Lines matching the NID filter", ++ .udesc = "Victimized Lines matching the NID filter (must provide nf=X modifier)", ++ .uflags = INTEL_X86_NCOMBO, ++ .umodmsk_req = _SNBEP_UNC_ATTR_NF, + .ucode = 0x4000, + }, + }; +@@ -438,7 +446,7 @@ static const intel_x86_umask_t snbep_unc_c_tor_inserts[]={ + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NID_ALL", +- .udesc = "Number of NID-matched transactions inserted into the TOR", ++ .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", + .ucode = 0x4800, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF, +@@ -633,9 +641,10 @@ static const intel_x86_entry_t intel_snbep_unc_c_pe[]={ + }, + { .name = "UNC_C_LLC_VICTIMS", + .desc = "Lines victimized", +- .modmsk = SNBEP_UNC_CBO_ATTRS, ++ .modmsk = SNBEP_UNC_CBO_NID_ATTRS, + .cntmsk = 0x3, + .code = 0x37, ++ .flags = INTEL_X86_NO_AUTOENCODE, + .numasks = LIBPFM_ARRAY_SIZE(snbep_unc_c_llc_victims), + .ngrp = 1, + .umasks = snbep_unc_c_llc_victims, +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index 2edacd5..b5da6a6 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -1254,6 +1254,14 @@ static const test_event_t x86_test_events[]={ + .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:STATE_MESIF:e=0:i=0:t=0:tf=0", + }, + { SRC_LINE, ++ .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x1f34, ++ .codes[1] = 0x7c0000, ++ .fstr = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:ANY:STATE_MESIF:e=0:i=0:t=0:tf=0", ++ }, ++ { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:DATA_READ:nf=1", + .ret = PFM_ERR_ATTR, + }, +@@ -1262,6 +1270,10 @@ static const test_event_t x86_test_events[]={ + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, ++ .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, + .name = "snbep_unc_cbo0::UNC_C_LLC_LOOKUP:NID:STATE_M", + .ret = PFM_ERR_ATTR, + }, + +commit 9d96dfd265971c66ee7de876b3bcbaf1c05d6291 +Author: Stephane Eranian +Date: Sun Jun 15 09:47:44 2014 +0200 + + Fix IVB-EP Cbox descrptions for LLC_VICTIMS and LLC_LOOKUP + + To add explicit language to umasks depending on the nf=X filter. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_ivbep_unc_cbo_events.h b/lib/events/intel_ivbep_unc_cbo_events.h +index 318521d..3827e03 100644 +--- a/lib/events/intel_ivbep_unc_cbo_events.h ++++ b/lib/events/intel_ivbep_unc_cbo_events.h +@@ -187,7 +187,7 @@ static const intel_x86_umask_t ivbep_unc_c_llc_lookup[]={ + .ucode = 0x1100, + }, + { .uname = "NID", +- .udesc = "Match a given RTID destination NID", ++ .udesc = "Match a given RTID destination NID (must provide nf=X modifier)", + .umodmsk_req = _SNBEP_UNC_ATTR_NF1, + .grpid = 1, + .ucode = 0x4100, +@@ -218,7 +218,7 @@ static const intel_x86_umask_t ivbep_unc_c_llc_victims[]={ + .grpid = 0, + }, + { .uname = "NID", +- .udesc = "Victimized Lines matching the NID filter", ++ .udesc = "Victimized Lines matching the NID filter (must provide nf=X modifier)", + .ucode = 0x4000, + .uflags = INTEL_X86_GRP_DFL_NONE, + .umodmsk_req = _SNBEP_UNC_ATTR_NF1, +@@ -536,7 +536,7 @@ static const intel_x86_umask_t ivbep_unc_c_tor_inserts[]={ + .uflags = INTEL_X86_NCOMBO | INTEL_X86_EXCL_GRP_GT, + }, + { .uname = "NID_ALL", +- .udesc = "Number of NID-matched transactions inserted into the TOR", ++ .udesc = "Number of NID-matched transactions inserted into the TOR (must provide nf=X modifier)", + .ucode = 0x4800, + .grpid = 0, + .umodmsk_req = _SNBEP_UNC_ATTR_NF1, + +commit 9926c1c21c23c14b0ab496a871e65028aeb103d7 +Author: Stephane Eranian +Date: Mon Jun 23 22:41:38 2014 +0200 + + add Intel Haswell CYCLE_ACTIVITY:STALLS_L1D_PENDING + + Event missing from table. Count the number of stall + cycles due to pending L1D load cache misses. + See SDM Vol3b. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 028f295..c51120c 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -310,6 +310,12 @@ static const intel_x86_umask_t hsw_cycle_activity[]={ + .ucntmsk= 0x4, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "STALL_L1D_PENDING", ++ .udesc = "Executions stalls due to pending L1D load cache misses", ++ .ucode = 0x0c00 | (0xc << INTEL_X86_CMASK_BIT), ++ .ucntmsk= 0x4, ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "STALLS_L2_PENDING", + .udesc = "Execution stalls due to L2 pending loads (must use with HT off only)", + .ucode = 0x0500 | (0x5 << INTEL_X86_CMASK_BIT), + +commit 69ef1478d2c68ed32b2709fefd1169e1ff93dd7f +Author: Stephane Eranian +Date: Tue Jul 22 23:06:24 2014 +0200 + + add ivb::BR_MISP_EXEC:TAKEN_RETURN_NEAR + + As an alias to ivb::BR_MISP_EXEC:TAKEN_NEAR_RETURN + to be consistent with SNB. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_ivb_events.h b/lib/events/intel_ivb_events.h +index 4e1b600..dac8163 100644 +--- a/lib/events/intel_ivb_events.h ++++ b/lib/events/intel_ivb_events.h +@@ -170,6 +170,12 @@ static const intel_x86_umask_t ivb_br_misp_exec[]={ + .ucode = 0x8800, + .uflags= INTEL_X86_NCOMBO, + }, ++ { .uname = "TAKEN_RETURN_NEAR", ++ .udesc = "All taken mispredicted indirect branches that have a return mnemonic", ++ .ucode = 0x8800, ++ .uequiv ="TAKEN_NEAR_RETURN", ++ .uflags= INTEL_X86_NCOMBO, ++ }, + { .uname = "TAKEN_DIRECT_NEAR_CALL", + .udesc = "All taken mispredicted non-indirect calls", + .ucode = 0x9000, + +commit 60cdc9bfae9e9c7d5294010fa135cccc9d014d10 +Author: James Ralph +Date: Wed Jul 23 09:52:26 2014 +0200 + + add RAPL support for more Haswell models + + This patch adds RAPL support for Haswell models: + - 60 + - 69 + - 71 + + Signed-off-by: James Ralph + +diff --git a/lib/pfmlib_intel_rapl.c b/lib/pfmlib_intel_rapl.c +index 1215731..4eb67ef 100644 +--- a/lib/pfmlib_intel_rapl.c ++++ b/lib/pfmlib_intel_rapl.c +@@ -83,7 +83,10 @@ pfm_rapl_detect(void *this) + switch(pfm_intel_x86_cfg.model) { + case 42: /* Sandy Bridge */ + case 58: /* Ivy Bridge */ ++ case 60: /* Haswell */ ++ case 69: /* Haswell */ + case 70: /* Haswell */ ++ case 71: /* Haswell */ + /* already setup by default */ + break; + case 45: /* Sandy Bridg-EP */ + +commit 56976f3b1b419fd82016b815f32d62b456e7f121 +Author: Gary Mohr +Date: Wed Sep 3 12:13:22 2014 +0200 + + various fixes uncovered by Coverity + + This patch fixes: + - AMD64: broken model detection for model 5 and 4 + - common: useless assignment in event parsing code + + problems identified by running the coverity tool. + + Signed-off-by: Gary Mohr + +diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c +index 31e2181..98f55b8 100644 +--- a/lib/pfmlib_amd64.c ++++ b/lib/pfmlib_amd64.c +@@ -112,10 +112,14 @@ amd64_get_revision(pfm_amd64_config_t *cfg) + if (cfg->family == 15) { + switch (cfg->model >> 4) { + case 0: +- if (cfg->model == 5 && cfg->stepping < 2) ++ if (cfg->model == 5 && cfg->stepping < 2) { + rev = PFM_PMU_AMD64_K8_REVB; +- if (cfg->model == 4 && cfg->stepping == 0) ++ break; ++ } ++ if (cfg->model == 4 && cfg->stepping == 0) { + rev = PFM_PMU_AMD64_K8_REVB; ++ break; ++ } + rev = PFM_PMU_AMD64_K8_REVC; + break; + case 1: +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index f4bdb78..fbb420e 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -945,7 +945,7 @@ found_attr: + if (type != PFM_ATTR_UMASK && type != PFM_ATTR_RAW_UMASK && !has_val) { + if (type != PFM_ATTR_MOD_BOOL) + return PFM_ERR_ATTR_VAL; +- has_val = 1; s = yes; /* no const */ ++ s = yes; /* no const */ + goto handle_bool; + } + + +commit 14b358a6c1f19bb5ab2697e9a76d84a7a8a19b0a +Author: Stephane Eranian +Date: Thu Sep 11 15:37:33 2014 +0200 + + update Intel Haswell event table + + Based on published HSW table from download.01.org: + + - add missing EPT_* umask to PAGE_WALKER_LOADS + - fix counter constraint on PAGE_WALKER_LOADS + - add EPT:CYCLES event + - add MACHINE_CLEARS:CYCLES + - add CYCLE_ACTIVITY:CYCLES_NO_EXECUTE + - remove MEM_UOPS_RETIRED:LOCK_STORE + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index c51120c..0b8f524 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -322,6 +322,12 @@ static const intel_x86_umask_t hsw_cycle_activity[]={ + .ucntmsk= 0xf, + .uflags = INTEL_X86_NCOMBO, + }, ++ { .uname = "CYCLES_NO_EXECUTE", ++ .udesc = "Cycles during which no instructions were executed in the execution stage of the pipeline", ++ .ucode = 0x0400 | (0x4 << INTEL_X86_CMASK_BIT), ++ .ucntmsk= 0xf, ++ .uflags = INTEL_X86_NCOMBO, ++ }, + }; + + static const intel_x86_umask_t hsw_dtlb_load_misses[]={ +@@ -904,6 +910,11 @@ static const intel_x86_umask_t hsw_longest_lat_cache[]={ + }; + + static const intel_x86_umask_t hsw_machine_clears[]={ ++ { .uname = "CYCLES", ++ .udesc = "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes", ++ .ucode = 0x100, ++ .uflags = INTEL_X86_NCOMBO, ++ }, + { .uname = "MEMORY_ORDERING", + .udesc = "Number of Memory Ordering Machine Clears detected", + .ucode = 0x200, +@@ -1020,11 +1031,6 @@ static const intel_x86_umask_t hsw_mem_uops_retired[]={ + .ucode = 0x2100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, + }, +- { .uname = "LOCK_STORES", +- .udesc = "Store uops with locked access retired", +- .ucode = 0x2200, +- .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS, +- }, + { .uname = "SPLIT_LOADS", + .udesc = "Line-splitted load uops retired", + .ucode = 0x4100, +@@ -1804,6 +1810,36 @@ static const intel_x86_umask_t hsw_page_walker_loads[]={ + .ucode = 0x2400, + .uflags= INTEL_X86_NCOMBO, + }, ++ { .uname = "EPT_DTLB_L1", ++ .udesc = "Number of extended page table walks from the DTLB that hit in the L1D and line fill buffer", ++ .ucode = 0x4100, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_ITLB_L1", ++ .udesc = "Number of extended page table walks from the ITLB that hit in the L1D and line fill buffer", ++ .ucode = 0x8100, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_DTLB_L2", ++ .udesc = "Number of extended page table walks from the DTLB that hit in the L2", ++ .ucode = 0x4200, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_ITLB_L2", ++ .udesc = "Number of extended page table walks from the ITLB that hit in the L2", ++ .ucode = 0x8200, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_DTLB_L3", ++ .udesc = "Number of extended page table walks from the DTLB that hit in the L3", ++ .ucode = 0x4400, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_ITLB_L3", ++ .udesc = "Number of extended page table walks from the ITLB that hit in the L3", ++ .ucode = 0x8400, ++ .uflags= INTEL_X86_NCOMBO, ++ }, + { .uname = "DTLB_MEMORY", + .udesc = "Number of DTLB page walker loads that hit memory", + .ucode = 0x1800, +@@ -1814,6 +1850,16 @@ static const intel_x86_umask_t hsw_page_walker_loads[]={ + .ucode = 0x2800, + .uflags= INTEL_X86_NCOMBO, + }, ++ { .uname = "EPT_DTLB_MEMORY", ++ .udesc = "Number of extended page table walks from the DTLB that hit memory", ++ .ucode = 0x4800, ++ .uflags= INTEL_X86_NCOMBO, ++ }, ++ { .uname = "EPT_ITLB_MEMORY", ++ .udesc = "Number of extended page table walks from the ITLB that hit memory", ++ .ucode = 0x8800, ++ .uflags= INTEL_X86_NCOMBO, ++ }, + }; + + static const intel_x86_umask_t hsw_lsd[]={ +@@ -1832,6 +1878,14 @@ static const intel_x86_umask_t hsw_dsb2mite_switches[]={ + }, + }; + ++static const intel_x86_umask_t hsw_ept[]={ ++ { .uname = "CYCLES", ++ .udesc = "Cycles for an extended page table walk", ++ .ucode = 0x0200, ++ .uflags= INTEL_X86_NCOMBO | INTEL_X86_DFL, ++ }, ++}; ++ + static const intel_x86_entry_t intel_hsw_pe[]={ + { .name = "UNHALTED_CORE_CYCLES", + .desc = "Count core clock cycles whenever the clock signal on the specific core is running (not halted)", +@@ -2412,21 +2466,30 @@ static const intel_x86_entry_t intel_hsw_pe[]={ + { .name = "PAGE_WALKER_LOADS", + .desc = "Page walker loads", + .modmsk = INTEL_V4_ATTRS, +- .cntmsk = 0xff, ++ .cntmsk = 0xf, + .code = 0xbc, + .numasks = LIBPFM_ARRAY_SIZE(hsw_page_walker_loads), + .ngrp = 1, + .umasks = hsw_page_walker_loads, + }, +-{ .name = "DSB2MITE_SWITCHES", +- .desc = "Number of DSB to MITE switches", +- .modmsk = INTEL_V4_ATTRS, +- .cntmsk = 0xff, +- .code = 0xab, +- .numasks = LIBPFM_ARRAY_SIZE(hsw_dsb2mite_switches), +- .ngrp = 1, +- .umasks = hsw_dsb2mite_switches, +-}, ++ { .name = "DSB2MITE_SWITCHES", ++ .desc = "Number of DSB to MITE switches", ++ .modmsk = INTEL_V4_ATTRS, ++ .cntmsk = 0xff, ++ .code = 0xab, ++ .numasks = LIBPFM_ARRAY_SIZE(hsw_dsb2mite_switches), ++ .ngrp = 1, ++ .umasks = hsw_dsb2mite_switches, ++ }, ++ { .name = "EPT", ++ .desc = "Extended page table", ++ .modmsk = INTEL_V4_ATTRS, ++ .cntmsk = 0xff, ++ .code = 0x4f, ++ .numasks = LIBPFM_ARRAY_SIZE(hsw_ept), ++ .ngrp = 1, ++ .umasks = hsw_ept, ++ }, + { .name = "OFFCORE_RESPONSE_0", + .desc = "Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)", + .modmsk = INTEL_V4_ATTRS, + +commit 98c00b8e690bd0f317a169b57aa0e3a51495768c +Author: Stephane Eranian +Date: Thu Sep 11 17:30:07 2014 +0200 + + add support for Intel Haswell-EP + + This patch adds core PMU support for Intel Haswell-EP + processors. + + Based on information from download.01.org/perfmon/HSX + + Signed-off-by: Stephane Eranian + +diff --git a/docs/man3/libpfm_intel_hsw.3 b/docs/man3/libpfm_intel_hsw.3 +index fb36acf..f67db2b 100644 +--- a/docs/man3/libpfm_intel_hsw.3 ++++ b/docs/man3/libpfm_intel_hsw.3 +@@ -7,9 +7,11 @@ libpfm_intel_hsw - support for Intel Haswell core PMU + .sp + .B PMU name: hsw + .B PMU desc: Intel Haswell ++.B PMU name: hsw_ep ++.B PMU desc: Intel Haswell-EP + .sp + .SH DESCRIPTION +-The library supports the Intel Haswell core PMU. It should be noted that ++The library supports the Intel Haswell and Haswell-EP core PMU. It should be noted that + this PMU model only covers each core's PMU and not the socket level + PMU. + +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +index 0169511..43ec178 100644 +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -242,6 +242,8 @@ typedef enum { + PFM_PMU_INTEL_IVBEP_UNC_R3QPI2, /* Intel IvyBridge-EP R3QPI 2 uncore */ + PFM_PMU_INTEL_IVBEP_UNC_IRP, /* Intel IvyBridge-EP IRP uncore */ + ++ PFM_PMU_INTEL_HSW_EP, /* Intel Haswell EP */ ++ + /* MUST ADD NEW PMU MODELS HERE */ + + PFM_PMU_MAX /* end marker */ +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index 0b8f524..a17d15f 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -961,6 +961,24 @@ static const intel_x86_umask_t hsw_mem_load_uops_l3_miss_retired[]={ + .ucode = 0x100, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_PEBS | INTEL_X86_DFL, + }, ++ { .uname = "REMOTE_DRAM", ++ .udesc = "Number of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)", ++ .ucode = 0x400, ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, ++ }, ++ { .uname = "REMOTE_HITM", ++ .udesc = "Number of retired load uops whose data sources was remote HITM (Precise Event)", ++ .ucode = 0x1000, ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, ++ }, ++ { .uname = "REMOTE_FWD", ++ .udesc = "Load uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)", ++ .ucode = 0x2000, ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .uflags= INTEL_X86_NCOMBO | INTEL_X86_PEBS, ++ }, + }; + + static const intel_x86_umask_t hsw_mem_load_uops_retired[]={ +@@ -1500,34 +1518,157 @@ static const intel_x86_umask_t hsw_offcore_response[]={ + { .uname = "LLC_HITM", + .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", + .ucode = 1ULL << (18+8), ++ .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, + { .uname = "LLC_HITE", + .udesc = "Supplier: counts L3 hits in E-state", + .ucode = 1ULL << (19+8), ++ .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, + { .uname = "LLC_HITS", + .udesc = "Supplier: counts L3 hits in S-state", + .ucode = 1ULL << (20+8), ++ .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, + { .uname = "LLC_HITF", + .udesc = "Supplier: counts L3 hits in F-state", + .ucode = 1ULL << (21+8), +- .grpid = 1, +- }, +- { .uname = "LLC_MISS_LOCAL", +- .udesc = "Supplier: counts L3 misses to local DRAM", +- .ucode = 1ULL << (22+8), ++ .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, + { .uname = "LLC_HITMESF", + .udesc = "Supplier: counts L3 hits in any state (M, E, S, F)", + .ucode = 0xfULL << (18+8), + .uequiv = "LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITF", ++ .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, ++ { .uname = "LLC_HIT", ++ .udesc = "Alias for LLC_HITMESF", ++ .ucode = 0xfULL << (18+8), ++ .uequiv = "LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITF", ++ .umodel = PFM_PMU_INTEL_HSW, ++ .grpid = 1, ++ }, ++ { .uname = "LLC_MISS_LOCAL", ++ .udesc = "Supplier: counts L3 misses to local DRAM", ++ .ucode = 1ULL << (22+8), ++ .umodel = PFM_PMU_INTEL_HSW, ++ .grpid = 1, ++ }, ++ { .uname = "L3_HITM", ++ .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", ++ .ucode = 1ULL << (18+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_HITE", ++ .udesc = "Supplier: counts L3 hits in E-state", ++ .ucode = 1ULL << (19+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_HITS", ++ .udesc = "Supplier: counts L3 hits in S-state", ++ .ucode = 1ULL << (20+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_HITF", ++ .udesc = "Supplier: counts L3 hits in F-state", ++ .ucode = 1ULL << (21+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_HIT", ++ .udesc = "Supplier: counts L3 hits in M, E, S, F state", ++ .ucode = 0xfULL << (18+8), ++ .uequiv = "L3_HITM:L3_HITE:L3_HITS:L3_HITF", ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L4_HIT_LOCAL_L4", ++ .udesc = "Supplier: counts L4 hits to local L4 cache", ++ .ucode = 0x1ULL << (22+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L4_HIT_REMOTE_HOP0_L4", ++ .udesc = "Supplier: counts L4 hits to remote L4 cache with 0 hop", ++ .ucode = 0x1ULL << (23+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L4_HIT_REMOTE_HOP1_L4", ++ .udesc = "Supplier: counts L4 hits to remote L4 cache with 1 hop", ++ .ucode = 0x1ULL << (24+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L4_HIT_REMOTE_HOP2P_L4", ++ .udesc = "Supplier: counts L4 hits to remote L4 cache with 2P hops", ++ .ucode = 0x1ULL << (25+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L4_HIT", ++ .udesc = "Supplier: counts L4 hits", ++ .ucode = 0xfULL << (22+8), ++ .uequiv = "L4_HIT_LOCAL_L4:L4_HIT_REMOTE_HOP0_L4:L4_HIT_REMOTE_HOP1_L4:L4_HIT_REMOTE_HOP2P_L4", ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "LLC_MISS_LOCAL", ++ .udesc = "Supplier: counts L3 misses to local DRAM", ++ .ucode = 1ULL << (22+8), ++ .umodel = PFM_PMU_INTEL_HSW, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS_LOCAL", ++ .udesc = "Supplier: counts L3 misses to local DRAM", ++ .ucode = 1ULL << (26+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS_REMOTE_HOP0_DRAM", ++ .udesc = "Supplier: counts L3 misses to remote DRAM with 0 hop", ++ .ucode = 0x1ULL << (27+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS_REMOTE_HOP1_DRAM", ++ .udesc = "Supplier: counts L3 misses to remote DRAM with 1 hop", ++ .ucode = 0x1ULL << (28+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS_REMOTE_HOP2P_DRAM", ++ .udesc = "Supplier: counts L3 misses to remote DRAM with 2P hops", ++ .ucode = 0x1ULL << (29+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS", ++ .udesc = "Supplier: counts L3 misses to local or remote DRAM", ++ .ucode = 0xfULL << (26+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "L3_MISS_REMOTE_DRAM", ++ .udesc = "Supplier: counts L3 misses to remote DRAM", ++ .ucode = 0x3ULL << (27+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, ++ { .uname = "SPL_HIT", ++ .udesc = "Supplier: counts L3 misses to remote DRAM", ++ .ucode = 0x1ULL << (30+8), ++ .umodel = PFM_PMU_INTEL_HSW_EP, ++ .grpid = 1, ++ }, + { .uname = "SNP_NONE", + .udesc = "Snoop: counts number of times no snoop-related information is available", + .ucode = 1ULL << (31+8), +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index fbb420e..81903ff 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -98,6 +98,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &intel_ivb_unc_cbo3_support, + &intel_ivb_ep_support, + &intel_hsw_support, ++ &intel_hsw_ep_support, + &intel_rapl_support, + &intel_snbep_unc_cb0_support, + &intel_snbep_unc_cb1_support, +diff --git a/lib/pfmlib_intel_hsw.c b/lib/pfmlib_intel_hsw.c +index f4975f6..1feae63 100644 +--- a/lib/pfmlib_intel_hsw.c ++++ b/lib/pfmlib_intel_hsw.c +@@ -40,7 +40,6 @@ pfm_hsw_detect(void *this) + + switch (pfm_intel_x86_cfg.model) { + case 60: /* Haswell */ +- case 63: /* Haswell */ + case 69: /* Haswell */ + case 70: /* Haswell */ + case 71: /* Haswell */ +@@ -52,6 +51,27 @@ pfm_hsw_detect(void *this) + } + + static int ++pfm_hsw_ep_detect(void *this) ++{ ++ int ret; ++ ++ ret = pfm_intel_x86_detect(); ++ if (ret != PFM_SUCCESS) ++ return ret; ++ ++ if (pfm_intel_x86_cfg.family != 6) ++ return PFM_ERR_NOTSUPP; ++ ++ switch (pfm_intel_x86_cfg.model) { ++ case 63: /* Haswell EP */ ++ break; ++ default: ++ return PFM_ERR_NOTSUPP; ++ } ++ return PFM_SUCCESS; ++} ++ ++static int + pfm_hsw_init(void *this) + { + pfm_intel_x86_cfg.arch_version = 4; +@@ -86,3 +106,32 @@ pfmlib_pmu_t intel_hsw_support={ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, + .can_auto_encode = pfm_intel_x86_can_auto_encode, + }; ++ ++pfmlib_pmu_t intel_hsw_ep_support={ ++ .desc = "Intel Haswell EP", ++ .name = "hsw_ep", ++ .pmu = PFM_PMU_INTEL_HSW_EP, ++ .pme_count = LIBPFM_ARRAY_SIZE(intel_hsw_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .supported_plm = INTEL_X86_PLM, ++ .num_cntrs = 8, /* consider with HT off by default */ ++ .num_fixed_cntrs = 3, ++ .max_encoding = 2, /* offcore_response */ ++ .pe = intel_hsw_pe, ++ .atdesc = intel_x86_mods, ++ .flags = PFMLIB_PMU_FL_RAW_UMASK ++ | INTEL_X86_PMU_FL_ECMASK, ++ .pmu_detect = pfm_hsw_ep_detect, ++ .pmu_init = pfm_hsw_init, ++ .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding), ++ .get_event_first = pfm_intel_x86_get_event_first, ++ .get_event_next = pfm_intel_x86_get_event_next, ++ .event_is_valid = pfm_intel_x86_event_is_valid, ++ .validate_table = pfm_intel_x86_validate_table, ++ .get_event_info = pfm_intel_x86_get_event_info, ++ .get_event_attr_info = pfm_intel_x86_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs), ++ .get_event_nattrs = pfm_intel_x86_get_event_nattrs, ++ .can_auto_encode = pfm_intel_x86_can_auto_encode, ++}; +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index aa974e0..129a815 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -246,6 +246,7 @@ extern pfmlib_pmu_t intel_ivb_unc_cbo2_support; + extern pfmlib_pmu_t intel_ivb_unc_cbo3_support; + extern pfmlib_pmu_t intel_ivb_ep_support; + extern pfmlib_pmu_t intel_hsw_support; ++extern pfmlib_pmu_t intel_hsw_ep_support; + extern pfmlib_pmu_t intel_rapl_support; + extern pfmlib_pmu_t intel_snbep_unc_cb0_support; + extern pfmlib_pmu_t intel_snbep_unc_cb1_support; +diff --git a/tests/validate_x86.c b/tests/validate_x86.c +index b5da6a6..743cc14 100644 +--- a/tests/validate_x86.c ++++ b/tests/validate_x86.c +@@ -2702,8 +2702,110 @@ static const test_event_t x86_test_events[]={ + .codes[0] = 0x25, + .fstr = "ivbep_unc_r3qpi1::UNC_R3_TXR_CYCLES_FULL:e=0:t=0", + }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=3:u", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5101cd, ++ .codes[1] = 3, ++ .fstr = "hsw_ep::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=1000000", ++ .ret = PFM_ERR_ATTR_VAL, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_trans_retired:load_latency", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301cd, ++ .codes[1] = 3, ++ .fstr = "hsw_ep::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:t=0:ldlat=3:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_trans_retired:load_latency:ldlat=1000000", ++ .ret = PFM_ERR_ATTR_VAL, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_trans_retired:latency_above_threshold:ldlat=2:intx=0:intxcp=0", ++ .ret = PFM_ERR_ATTR_VAL, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::inst_Retired:any_p:intx", ++ .count = 1, ++ .codes[0] = 0x1005300c0, ++ .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::inst_Retired:any_p:intx:intxcp", ++ .count = 1, ++ .codes[0] = 0x3005300c0, ++ .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=1:intxcp=1", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::inst_Retired:any_p:intx=0:intxcp", ++ .count = 1, ++ .codes[0] = 0x2005300c0, ++ .fstr = "hsw_ep::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=1", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::cycle_activity:cycles_l2_pending", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x15301a3, ++ .fstr = "hsw_ep::CYCLE_ACTIVITY:CYCLES_L2_PENDING:k=1:u=1:e=0:i=0:t=0:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::cycle_activity:cycles_l2_pending:c=8", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::hle_retired:aborted", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x5304c8, ++ .fstr = "hsw_ep::HLE_RETIRED:ABORTED:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::mem_load_uops_l3_miss_retired:remote_dram", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x5304d3, ++ .fstr = "hsw_ep::MEM_LOAD_UOPS_L3_MISS_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::offcore_response_0:any_data:L3_miss_local", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1] = 0x3f84000091ull, ++ .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD:L3_MISS_LOCAL:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::offcore_response_0:any_data:LLC_miss_local", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::offcore_response_0:any_data:LLC_miss_remote", ++ .ret = PFM_ERR_ATTR, ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::offcore_response_0:any_data:L3_HIT", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] =0x5301b7, ++ .codes[1] =0x3f803c0091ull, ++ .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD:L3_HITM:L3_HITE:L3_HITS:L3_HITF:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", ++ }, ++ { SRC_LINE, ++ .name = "hsw_ep::offcore_response_0:any_data:L4_HIT", ++ .ret = PFM_SUCCESS, ++ .count = 2, ++ .codes[0] = 0x5301b7, ++ .codes[1] =0x3f83c00091ull, ++ .fstr = "hsw_ep::OFFCORE_RESPONSE_0:DMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RD:L4_HIT_LOCAL_L4:L4_HIT_REMOTE_HOP0_L4:L4_HIT_REMOTE_HOP1_L4:L4_HIT_REMOTE_HOP2P_L4:SNP_ANY:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0", ++ }, + }; +- + #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t)) + + static int + +commit 70ecfb02bf0e8c94b6ee5694626ca269bfbed4d2 +Author: Stephane Eranian +Date: Thu Sep 11 17:50:32 2014 +0200 + + remove duplicated offcore_Response:LLC_MISS_LOCAL from Haswell offcore + + The umask was present twice in the event table. + + Signed-off-by: Stephane Eranian + +diff --git a/lib/events/intel_hsw_events.h b/lib/events/intel_hsw_events.h +index a17d15f..0087f01 100644 +--- a/lib/events/intel_hsw_events.h ++++ b/lib/events/intel_hsw_events.h +@@ -1553,12 +1553,6 @@ static const intel_x86_umask_t hsw_offcore_response[]={ + .umodel = PFM_PMU_INTEL_HSW, + .grpid = 1, + }, +- { .uname = "LLC_MISS_LOCAL", +- .udesc = "Supplier: counts L3 misses to local DRAM", +- .ucode = 1ULL << (22+8), +- .umodel = PFM_PMU_INTEL_HSW, +- .grpid = 1, +- }, + { .uname = "L3_HITM", + .udesc = "Supplier: counts L3 hits in M-state (initial lookup)", + .ucode = 1ULL << (18+8), diff --git a/SOURCES/libpfm-haswell.patch b/SOURCES/libpfm-haswell.patch deleted file mode 100644 index cb0fd4d..0000000 --- a/SOURCES/libpfm-haswell.patch +++ /dev/null @@ -1,26 +0,0 @@ -commit 4b0a11762f62f7763be31ade2d70ff0ae5f80fd4 -Author: Vince Weaver -Date: Fri Dec 6 10:17:18 2013 -0500 - - add missing Intel Haswell model numbers - - This patch adds support for a few more Haswell - models: 63, 69, 70, 71. - - Signed-off-by: Vince Weaver - -diff --git a/lib/pfmlib_intel_hsw.c b/lib/pfmlib_intel_hsw.c -index 7d01ff1..f4975f6 100644 ---- a/lib/pfmlib_intel_hsw.c -+++ b/lib/pfmlib_intel_hsw.c -@@ -40,6 +40,10 @@ pfm_hsw_detect(void *this) - - switch (pfm_intel_x86_cfg.model) { - case 60: /* Haswell */ -+ case 63: /* Haswell */ -+ case 69: /* Haswell */ -+ case 70: /* Haswell */ -+ case 71: /* Haswell */ - break; - default: - return PFM_ERR_NOTSUPP; diff --git a/SOURCES/libpfm-power8.patch b/SOURCES/libpfm-power8.patch index 1177a5b..e1dfc16 100644 --- a/SOURCES/libpfm-power8.patch +++ b/SOURCES/libpfm-power8.patch @@ -1169,3 +1169,7714 @@ index d90f015..8e203d4 100644 extern pfmlib_pmu_t torrent_support; extern pfmlib_pmu_t sparc_support; extern pfmlib_pmu_t sparc_ultra12_support; +commit 506db47a2f0c232f123bdfef0cd281e09bf9f6e3 +Author: Carl Love +Date: Thu May 15 15:07:34 2014 -0700 + + Update IBM Power8 event list + + The list of available Power 8 performance counter events has been updated. + There are a number of new events that have been added to the list with a + few corrections to existing events. + + Signed-off-by: Carl Love + +diff --git a/lib/events/power8_events.h b/lib/events/power8_events.h +index 25945f3..3437602 100644 +--- a/lib/events/power8_events.h ++++ b/lib/events/power8_events.h +@@ -23,481 +23,1380 @@ Author: Carl Love + * http://www.power.org/documentation + */ + +-#define POWER8_PME_PM_1PLUS_PPC_CMPL 0 +-#define POWER8_PME_PM_1PLUS_PPC_DISP 1 +-#define POWER8_PME_PM_ANY_THRD_RUN_CYC 2 +-#define POWER8_PME_PM_BR_MPRED_CMPL 3 +-#define POWER8_PME_PM_BR_TAKEN_CMPL 4 +-#define POWER8_PME_PM_CYC 5 +-#define POWER8_PME_PM_DATA_FROM_L2MISS 6 +-#define POWER8_PME_PM_DATA_FROM_L3MISS 7 +-#define POWER8_PME_PM_DATA_FROM_MEM 8 +-#define POWER8_PME_PM_DTLB_MISS 9 +-#define POWER8_PME_PM_EXT_INT 10 +-#define POWER8_PME_PM_FLOP 11 +-#define POWER8_PME_PM_FLUSH 12 +-#define POWER8_PME_PM_GCT_NOSLOT_CYC 13 +-#define POWER8_PME_PM_IERAT_MISS 14 +-#define POWER8_PME_PM_INST_DISP 15 +-#define POWER8_PME_PM_INST_FROM_L3MISS 16 +-#define POWER8_PME_PM_ITLB_MISS 17 +-#define POWER8_PME_PM_L1_DCACHE_RELOAD_VALID 18 +-#define POWER8_PME_PM_L1_ICACHE_MISS 19 +-#define POWER8_PME_PM_LD_MISS_L1 20 +-#define POWER8_PME_PM_LSU_DERAT_MISS 21 +-#define POWER8_PME_PM_MRK_BR_MPRED_CMPL 22 +-#define POWER8_PME_PM_MRK_BR_TAKEN_CMPL 23 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS 24 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS 25 +-#define POWER8_PME_PM_MRK_DATA_FROM_MEM 26 +-#define POWER8_PME_PM_MRK_DERAT_MISS 27 +-#define POWER8_PME_PM_MRK_DTLB_MISS 28 +-#define POWER8_PME_PM_MRK_INST_CMPL 29 +-#define POWER8_PME_PM_MRK_INST_DISP 30 +-#define POWER8_PME_PM_MRK_INST_FROM_L3MISS 31 +-#define POWER8_PME_PM_MRK_L1_ICACHE_MISS 32 +-#define POWER8_PME_PM_MRK_L1_RELOAD_VALID 33 +-#define POWER8_PME_PM_MRK_LD_MISS_L1 34 +-#define POWER8_PME_PM_MRK_ST_CMPL 35 +-#define POWER8_PME_PM_RUN_CYC 36 +-#define POWER8_PME_PM_RUN_INST_CMPL 37 +-#define POWER8_PME_PM_RUN_PURR 38 +-#define POWER8_PME_PM_ST_FIN 39 +-#define POWER8_PME_PM_ST_MISS_L1 40 +-#define POWER8_PME_PM_TB_BIT_TRANS 41 +-#define POWER8_PME_PM_THRD_CONC_RUN_INST 42 +-#define POWER8_PME_PM_THRESH_EXC_1024 43 +-#define POWER8_PME_PM_THRESH_EXC_128 44 +-#define POWER8_PME_PM_THRESH_EXC_2048 45 +-#define POWER8_PME_PM_THRESH_EXC_256 46 +-#define POWER8_PME_PM_THRESH_EXC_32 47 +-#define POWER8_PME_PM_THRESH_EXC_4096 48 +-#define POWER8_PME_PM_THRESH_EXC_512 49 +-#define POWER8_PME_PM_THRESH_EXC_64 50 +-#define POWER8_PME_PM_THRESH_MET 51 +-#define POWER8_PME_PM_BR_2PATH 52 +-#define POWER8_PME_PM_BR_CMPL 53 +-#define POWER8_PME_PM_BR_MRK_2PATH 54 +-#define POWER8_PME_PM_CMPLU_STALL 55 +-#define POWER8_PME_PM_CMPLU_STALL_BRU 56 +-#define POWER8_PME_PM_CMPLU_STALL_BRU_CRU 57 +-#define POWER8_PME_PM_CMPLU_STALL_COQ_FULL 58 +-#define POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS 59 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 60 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 61 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 62 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS 63 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM 64 +-#define POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE 65 +-#define POWER8_PME_PM_CMPLU_STALL_ERAT_MISS 66 +-#define POWER8_PME_PM_CMPLU_STALL_FLUSH 67 +-#define POWER8_PME_PM_CMPLU_STALL_FXLONG 68 +-#define POWER8_PME_PM_CMPLU_STALL_FXU 69 +-#define POWER8_PME_PM_CMPLU_STALL_HWSYNC 70 +-#define POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH 71 +-#define POWER8_PME_PM_CMPLU_STALL_LSU 72 +-#define POWER8_PME_PM_CMPLU_STALL_LWSYNC 73 +-#define POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY 74 +-#define POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH 75 +-#define POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL 76 +-#define POWER8_PME_PM_CMPLU_STALL_REJECT 77 +-#define POWER8_PME_PM_CMPLU_STALL_REJECT_LHS 78 +-#define POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL 79 +-#define POWER8_PME_PM_CMPLU_STALL_SCALAR 80 +-#define POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG 81 +-#define POWER8_PME_PM_CMPLU_STALL_STORE 82 +-#define POWER8_PME_PM_CMPLU_STALL_ST_FWD 83 +-#define POWER8_PME_PM_CMPLU_STALL_THRD 84 +-#define POWER8_PME_PM_CMPLU_STALL_VECTOR 85 +-#define POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG 86 +-#define POWER8_PME_PM_CMPLU_STALL_VSU 87 +-#define POWER8_PME_PM_DATA_FROM_L2 88 +-#define POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT 89 +-#define POWER8_PME_PM_DATA_FROM_L3 90 +-#define POWER8_PME_PM_DATA_FROM_L3MISS_MOD 91 +-#define POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT 92 +-#define POWER8_PME_PM_DATA_FROM_LMEM 93 +-#define POWER8_PME_PM_DATA_FROM_MEMORY 94 +-#define POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF 95 +-#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED 96 +-#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS 97 +-#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ 98 +-#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER 99 +-#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ 100 +-#define POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS 101 +-#define POWER8_PME_PM_GCT_NOSLOT_IC_MISS 102 +-#define POWER8_PME_PM_GRP_DISP 103 +-#define POWER8_PME_PM_GRP_MRK 104 +-#define POWER8_PME_PM_HV_CYC 105 +-#define POWER8_PME_PM_INST_CMPL 106 +-#define POWER8_PME_PM_IOPS_CMPL 107 +-#define POWER8_PME_PM_LD_CMPL 108 +-#define POWER8_PME_PM_LD_L3MISS_PEND_CYC 109 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2 110 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC 111 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2_CYC 112 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 113 +-#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 114 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3 115 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC 116 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3_CYC 117 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 118 +-#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 119 +-#define POWER8_PME_PM_MRK_DATA_FROM_LL4 120 +-#define POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC 121 +-#define POWER8_PME_PM_MRK_DATA_FROM_LMEM 122 +-#define POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC 123 +-#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY 124 +-#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC 125 +-#define POWER8_PME_PM_MRK_GRP_CMPL 126 +-#define POWER8_PME_PM_MRK_INST_DECODED 127 +-#define POWER8_PME_PM_MRK_L2_RC_DISP 128 +-#define POWER8_PME_PM_MRK_LD_MISS_L1_CYC 129 +-#define POWER8_PME_PM_MRK_STALL_CMPLU_CYC 130 +-#define POWER8_PME_PM_NEST_REF_CLK 131 +-#define POWER8_PME_PM_PMC1_OVERFLOW 132 +-#define POWER8_PME_PM_PMC2_OVERFLOW 133 +-#define POWER8_PME_PM_PMC3_OVERFLOW 134 +-#define POWER8_PME_PM_PMC4_OVERFLOW 135 +-#define POWER8_PME_PM_PMC6_OVERFLOW 136 +-#define POWER8_PME_PM_PPC_CMPL 137 +-#define POWER8_PME_PM_THRD_ALL_RUN_CYC 138 +-#define POWER8_PME_PM_THRESH_NOT_MET 139 ++#define POWER8_PME_PM_1LPAR_CYC 0 ++#define POWER8_PME_PM_1PLUS_PPC_CMPL 1 ++#define POWER8_PME_PM_1PLUS_PPC_DISP 2 ++#define POWER8_PME_PM_2LPAR_CYC 3 ++#define POWER8_PME_PM_4LPAR_CYC 4 ++#define POWER8_PME_PM_ALL_CHIP_PUMP_CPRED 5 ++#define POWER8_PME_PM_ALL_GRP_PUMP_CPRED 6 ++#define POWER8_PME_PM_ALL_GRP_PUMP_MPRED 7 ++#define POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY 8 ++#define POWER8_PME_PM_ALL_PUMP_CPRED 9 ++#define POWER8_PME_PM_ALL_PUMP_MPRED 10 ++#define POWER8_PME_PM_ALL_SYS_PUMP_CPRED 11 ++#define POWER8_PME_PM_ALL_SYS_PUMP_MPRED 12 ++#define POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY 13 ++#define POWER8_PME_PM_ANY_THRD_RUN_CYC 14 ++#define POWER8_PME_PM_BACK_BR_CMPL 15 ++#define POWER8_PME_PM_BANK_CONFLICT 16 ++#define POWER8_PME_PM_BRU_FIN 17 ++#define POWER8_PME_PM_BR_2PATH 18 ++#define POWER8_PME_PM_BR_BC_8 19 ++#define POWER8_PME_PM_BR_BC_8_CONV 20 ++#define POWER8_PME_PM_BR_CMPL 21 ++#define POWER8_PME_PM_BR_MPRED_CCACHE 22 ++#define POWER8_PME_PM_BR_MPRED_CMPL 23 ++#define POWER8_PME_PM_BR_MPRED_CR 24 ++#define POWER8_PME_PM_BR_MPRED_LSTACK 25 ++#define POWER8_PME_PM_BR_MPRED_TA 26 ++#define POWER8_PME_PM_BR_MRK_2PATH 27 ++#define POWER8_PME_PM_BR_PRED_BR0 28 ++#define POWER8_PME_PM_BR_PRED_BR1 29 ++#define POWER8_PME_PM_BR_PRED_BR_CMPL 30 ++#define POWER8_PME_PM_BR_PRED_CCACHE_BR0 31 ++#define POWER8_PME_PM_BR_PRED_CCACHE_BR1 32 ++#define POWER8_PME_PM_BR_PRED_CCACHE_CMPL 33 ++#define POWER8_PME_PM_BR_PRED_CR_BR0 34 ++#define POWER8_PME_PM_BR_PRED_CR_BR1 35 ++#define POWER8_PME_PM_BR_PRED_CR_CMPL 36 ++#define POWER8_PME_PM_BR_PRED_LSTACK_BR0 37 ++#define POWER8_PME_PM_BR_PRED_LSTACK_BR1 38 ++#define POWER8_PME_PM_BR_PRED_LSTACK_CMPL 39 ++#define POWER8_PME_PM_BR_PRED_TA_BR0 40 ++#define POWER8_PME_PM_BR_PRED_TA_BR1 41 ++#define POWER8_PME_PM_BR_PRED_TA_CMPL 42 ++#define POWER8_PME_PM_BR_TAKEN_CMPL 43 ++#define POWER8_PME_PM_BR_UNCOND_BR0 44 ++#define POWER8_PME_PM_BR_UNCOND_BR1 45 ++#define POWER8_PME_PM_BR_UNCOND_CMPL 46 ++#define POWER8_PME_PM_CASTOUT_ISSUED 47 ++#define POWER8_PME_PM_CASTOUT_ISSUED_GPR 48 ++#define POWER8_PME_PM_CHIP_PUMP_CPRED 49 ++#define POWER8_PME_PM_CLB_HELD 50 ++#define POWER8_PME_PM_CMPLU_STALL 51 ++#define POWER8_PME_PM_CMPLU_STALL_BRU 52 ++#define POWER8_PME_PM_CMPLU_STALL_BRU_CRU 53 ++#define POWER8_PME_PM_CMPLU_STALL_COQ_FULL 54 ++#define POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS 55 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 56 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 57 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 58 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS 59 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM 60 ++#define POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE 61 ++#define POWER8_PME_PM_CMPLU_STALL_ERAT_MISS 62 ++#define POWER8_PME_PM_CMPLU_STALL_FLUSH 63 ++#define POWER8_PME_PM_CMPLU_STALL_FXLONG 64 ++#define POWER8_PME_PM_CMPLU_STALL_FXU 65 ++#define POWER8_PME_PM_CMPLU_STALL_HWSYNC 66 ++#define POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH 67 ++#define POWER8_PME_PM_CMPLU_STALL_LSU 68 ++#define POWER8_PME_PM_CMPLU_STALL_LWSYNC 69 ++#define POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY 70 ++#define POWER8_PME_PM_CMPLU_STALL_NO_NTF 71 ++#define POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH 72 ++#define POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL 73 ++#define POWER8_PME_PM_CMPLU_STALL_REJECT 74 ++#define POWER8_PME_PM_CMPLU_STALL_REJECT_LHS 75 ++#define POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL 76 ++#define POWER8_PME_PM_CMPLU_STALL_SCALAR 77 ++#define POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG 78 ++#define POWER8_PME_PM_CMPLU_STALL_STORE 79 ++#define POWER8_PME_PM_CMPLU_STALL_ST_FWD 80 ++#define POWER8_PME_PM_CMPLU_STALL_THRD 81 ++#define POWER8_PME_PM_CMPLU_STALL_VECTOR 82 ++#define POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG 83 ++#define POWER8_PME_PM_CMPLU_STALL_VSU 84 ++#define POWER8_PME_PM_CO0_ALLOC 85 ++#define POWER8_PME_PM_CO0_BUSY 86 ++#define POWER8_PME_PM_CO_DISP_FAIL 87 ++#define POWER8_PME_PM_CO_TM_SC_FOOTPRINT 88 ++#define POWER8_PME_PM_CO_USAGE 89 ++#define POWER8_PME_PM_CRU_FIN 90 ++#define POWER8_PME_PM_CYC 91 ++#define POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED 92 ++#define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD 93 ++#define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR 94 ++#define POWER8_PME_PM_DATA_ALL_FROM_DL4 95 ++#define POWER8_PME_PM_DATA_ALL_FROM_DMEM 96 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2 97 ++#define POWER8_PME_PM_DATA_ALL_FROM_L21_MOD 98 ++#define POWER8_PME_PM_DATA_ALL_FROM_L21_SHR 99 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD 100 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST 101 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER 102 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF 103 ++#define POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT 104 ++#define POWER8_PME_PM_DATA_ALL_FROM_L3 105 ++#define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD 106 ++#define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR 107 ++#define POWER8_PME_PM_DATA_ALL_FROM_L31_MOD 108 ++#define POWER8_PME_PM_DATA_ALL_FROM_L31_SHR 109 ++#define POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD 110 ++#define POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT 111 ++#define POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF 112 ++#define POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT 113 ++#define POWER8_PME_PM_DATA_ALL_FROM_LL4 114 ++#define POWER8_PME_PM_DATA_ALL_FROM_LMEM 115 ++#define POWER8_PME_PM_DATA_ALL_FROM_MEMORY 116 ++#define POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE 117 ++#define POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE 118 ++#define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD 119 ++#define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR 120 ++#define POWER8_PME_PM_DATA_ALL_FROM_RL4 121 ++#define POWER8_PME_PM_DATA_ALL_FROM_RMEM 122 ++#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED 123 ++#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED 124 ++#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY 125 ++#define POWER8_PME_PM_DATA_ALL_PUMP_CPRED 126 ++#define POWER8_PME_PM_DATA_ALL_PUMP_MPRED 127 ++#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED 128 ++#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED 129 ++#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY 130 ++#define POWER8_PME_PM_DATA_CHIP_PUMP_CPRED 131 ++#define POWER8_PME_PM_DATA_FROM_DL2L3_MOD 132 ++#define POWER8_PME_PM_DATA_FROM_DL2L3_SHR 133 ++#define POWER8_PME_PM_DATA_FROM_DL4 134 ++#define POWER8_PME_PM_DATA_FROM_DMEM 135 ++#define POWER8_PME_PM_DATA_FROM_L2 136 ++#define POWER8_PME_PM_DATA_FROM_L21_MOD 137 ++#define POWER8_PME_PM_DATA_FROM_L21_SHR 138 ++#define POWER8_PME_PM_DATA_FROM_L2MISS 139 ++#define POWER8_PME_PM_DATA_FROM_L2MISS_MOD 140 ++#define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 141 ++#define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 142 ++#define POWER8_PME_PM_DATA_FROM_L2_MEPF 143 ++#define POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT 144 ++#define POWER8_PME_PM_DATA_FROM_L3 145 ++#define POWER8_PME_PM_DATA_FROM_L31_ECO_MOD 146 ++#define POWER8_PME_PM_DATA_FROM_L31_ECO_SHR 147 ++#define POWER8_PME_PM_DATA_FROM_L31_MOD 148 ++#define POWER8_PME_PM_DATA_FROM_L31_SHR 149 ++#define POWER8_PME_PM_DATA_FROM_L3MISS 150 ++#define POWER8_PME_PM_DATA_FROM_L3MISS_MOD 151 ++#define POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT 152 ++#define POWER8_PME_PM_DATA_FROM_L3_MEPF 153 ++#define POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT 154 ++#define POWER8_PME_PM_DATA_FROM_LL4 155 ++#define POWER8_PME_PM_DATA_FROM_LMEM 156 ++#define POWER8_PME_PM_DATA_FROM_MEM 157 ++#define POWER8_PME_PM_DATA_FROM_MEMORY 158 ++#define POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE 159 ++#define POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE 160 ++#define POWER8_PME_PM_DATA_FROM_RL2L3_MOD 161 ++#define POWER8_PME_PM_DATA_FROM_RL2L3_SHR 162 ++#define POWER8_PME_PM_DATA_FROM_RL4 163 ++#define POWER8_PME_PM_DATA_FROM_RMEM 164 ++#define POWER8_PME_PM_DATA_GRP_PUMP_CPRED 165 ++#define POWER8_PME_PM_DATA_GRP_PUMP_MPRED 166 ++#define POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY 167 ++#define POWER8_PME_PM_DATA_PUMP_CPRED 168 ++#define POWER8_PME_PM_DATA_PUMP_MPRED 169 ++#define POWER8_PME_PM_DATA_SYS_PUMP_CPRED 170 ++#define POWER8_PME_PM_DATA_SYS_PUMP_MPRED 171 ++#define POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY 172 ++#define POWER8_PME_PM_DATA_TABLEWALK_CYC 173 ++#define POWER8_PME_PM_DC_COLLISIONS 174 ++#define POWER8_PME_PM_DC_PREF_STREAM_ALLOC 175 ++#define POWER8_PME_PM_DC_PREF_STREAM_CONF 176 ++#define POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF 177 ++#define POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF 178 ++#define POWER8_PME_PM_DERAT_MISS_16G 179 ++#define POWER8_PME_PM_DERAT_MISS_16M 180 ++#define POWER8_PME_PM_DERAT_MISS_4K 181 ++#define POWER8_PME_PM_DERAT_MISS_64K 182 ++#define POWER8_PME_PM_DFU 183 ++#define POWER8_PME_PM_DFU_DCFFIX 184 ++#define POWER8_PME_PM_DFU_DENBCD 185 ++#define POWER8_PME_PM_DFU_MC 186 ++#define POWER8_PME_PM_DISP_CLB_HELD_BAL 187 ++#define POWER8_PME_PM_DISP_CLB_HELD_RES 188 ++#define POWER8_PME_PM_DISP_CLB_HELD_SB 189 ++#define POWER8_PME_PM_DISP_CLB_HELD_SYNC 190 ++#define POWER8_PME_PM_DISP_CLB_HELD_TLBIE 191 ++#define POWER8_PME_PM_DISP_HELD 192 ++#define POWER8_PME_PM_DISP_HELD_IQ_FULL 193 ++#define POWER8_PME_PM_DISP_HELD_MAP_FULL 194 ++#define POWER8_PME_PM_DISP_HELD_SRQ_FULL 195 ++#define POWER8_PME_PM_DISP_HELD_SYNC_HOLD 196 ++#define POWER8_PME_PM_DISP_HOLD_GCT_FULL 197 ++#define POWER8_PME_PM_DISP_WT 198 ++#define POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD 199 ++#define POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR 200 ++#define POWER8_PME_PM_DPTEG_FROM_DL4 201 ++#define POWER8_PME_PM_DPTEG_FROM_DMEM 202 ++#define POWER8_PME_PM_DPTEG_FROM_L2 203 ++#define POWER8_PME_PM_DPTEG_FROM_L21_MOD 204 ++#define POWER8_PME_PM_DPTEG_FROM_L21_SHR 205 ++#define POWER8_PME_PM_DPTEG_FROM_L2MISS 206 ++#define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 207 ++#define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 208 ++#define POWER8_PME_PM_DPTEG_FROM_L2_MEPF 209 ++#define POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 210 ++#define POWER8_PME_PM_DPTEG_FROM_L3 211 ++#define POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD 212 ++#define POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR 213 ++#define POWER8_PME_PM_DPTEG_FROM_L31_MOD 214 ++#define POWER8_PME_PM_DPTEG_FROM_L31_SHR 215 ++#define POWER8_PME_PM_DPTEG_FROM_L3MISS 216 ++#define POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 217 ++#define POWER8_PME_PM_DPTEG_FROM_L3_MEPF 218 ++#define POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 219 ++#define POWER8_PME_PM_DPTEG_FROM_LL4 220 ++#define POWER8_PME_PM_DPTEG_FROM_LMEM 221 ++#define POWER8_PME_PM_DPTEG_FROM_MEMORY 222 ++#define POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 223 ++#define POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 224 ++#define POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD 225 ++#define POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR 226 ++#define POWER8_PME_PM_DPTEG_FROM_RL4 227 ++#define POWER8_PME_PM_DPTEG_FROM_RMEM 228 ++#define POWER8_PME_PM_DSLB_MISS 229 ++#define POWER8_PME_PM_DTLB_MISS 230 ++#define POWER8_PME_PM_DTLB_MISS_16G 231 ++#define POWER8_PME_PM_DTLB_MISS_16M 232 ++#define POWER8_PME_PM_DTLB_MISS_4K 233 ++#define POWER8_PME_PM_DTLB_MISS_64K 234 ++#define POWER8_PME_PM_EAT_FORCE_MISPRED 235 ++#define POWER8_PME_PM_EAT_FULL_CYC 236 ++#define POWER8_PME_PM_EE_OFF_EXT_INT 237 ++#define POWER8_PME_PM_EXT_INT 238 ++#define POWER8_PME_PM_FAV_TBEGIN 239 ++#define POWER8_PME_PM_FLOP 240 ++#define POWER8_PME_PM_FLOP_SUM_SCALAR 241 ++#define POWER8_PME_PM_FLOP_SUM_VEC 242 ++#define POWER8_PME_PM_FLUSH 243 ++#define POWER8_PME_PM_FLUSH_BR_MPRED 244 ++#define POWER8_PME_PM_FLUSH_COMPLETION 245 ++#define POWER8_PME_PM_FLUSH_DISP 246 ++#define POWER8_PME_PM_FLUSH_DISP_SB 247 ++#define POWER8_PME_PM_FLUSH_DISP_SYNC 248 ++#define POWER8_PME_PM_FLUSH_DISP_TLBIE 249 ++#define POWER8_PME_PM_FLUSH_LSU 250 ++#define POWER8_PME_PM_FLUSH_PARTIAL 251 ++#define POWER8_PME_PM_FPU0_FCONV 252 ++#define POWER8_PME_PM_FPU0_FEST 253 ++#define POWER8_PME_PM_FPU0_FRSP 254 ++#define POWER8_PME_PM_FPU1_FCONV 255 ++#define POWER8_PME_PM_FPU1_FEST 256 ++#define POWER8_PME_PM_FPU1_FRSP 257 ++#define POWER8_PME_PM_FREQ_DOWN 258 ++#define POWER8_PME_PM_FREQ_UP 259 ++#define POWER8_PME_PM_FUSION_TOC_GRP0_1 260 ++#define POWER8_PME_PM_FUSION_TOC_GRP0_2 261 ++#define POWER8_PME_PM_FUSION_TOC_GRP0_3 262 ++#define POWER8_PME_PM_FUSION_TOC_GRP1_1 263 ++#define POWER8_PME_PM_FUSION_VSX_GRP0_1 264 ++#define POWER8_PME_PM_FUSION_VSX_GRP0_2 265 ++#define POWER8_PME_PM_FUSION_VSX_GRP0_3 266 ++#define POWER8_PME_PM_FUSION_VSX_GRP1_1 267 ++#define POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE 268 ++#define POWER8_PME_PM_FXU0_FIN 269 ++#define POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE 270 ++#define POWER8_PME_PM_FXU1_FIN 271 ++#define POWER8_PME_PM_FXU_BUSY 272 ++#define POWER8_PME_PM_FXU_IDLE 273 ++#define POWER8_PME_PM_GCT_EMPTY_CYC 274 ++#define POWER8_PME_PM_GCT_MERGE 275 ++#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED 276 ++#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS 277 ++#define POWER8_PME_PM_GCT_NOSLOT_CYC 278 ++#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ 279 ++#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP 280 ++#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER 281 ++#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ 282 ++#define POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS 283 ++#define POWER8_PME_PM_GCT_NOSLOT_IC_MISS 284 ++#define POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES 285 ++#define POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES 286 ++#define POWER8_PME_PM_GCT_UTIL_18_ENTRIES 287 ++#define POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES 288 ++#define POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES 289 ++#define POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES 290 ++#define POWER8_PME_PM_GRP_BR_MPRED_NONSPEC 291 ++#define POWER8_PME_PM_GRP_CMPL 292 ++#define POWER8_PME_PM_GRP_DISP 293 ++#define POWER8_PME_PM_GRP_IC_MISS_NONSPEC 294 ++#define POWER8_PME_PM_GRP_MRK 295 ++#define POWER8_PME_PM_GRP_NON_FULL_GROUP 296 ++#define POWER8_PME_PM_GRP_PUMP_CPRED 297 ++#define POWER8_PME_PM_GRP_PUMP_MPRED 298 ++#define POWER8_PME_PM_GRP_PUMP_MPRED_RTY 299 ++#define POWER8_PME_PM_GRP_TERM_2ND_BRANCH 300 ++#define POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR 301 ++#define POWER8_PME_PM_GRP_TERM_NOINST 302 ++#define POWER8_PME_PM_GRP_TERM_OTHER 303 ++#define POWER8_PME_PM_GRP_TERM_SLOT_LIMIT 304 ++#define POWER8_PME_PM_HV_CYC 305 ++#define POWER8_PME_PM_IBUF_FULL_CYC 306 ++#define POWER8_PME_PM_IC_DEMAND_CYC 307 ++#define POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 308 ++#define POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT 309 ++#define POWER8_PME_PM_IC_DEMAND_REQ 310 ++#define POWER8_PME_PM_IC_INVALIDATE 311 ++#define POWER8_PME_PM_IC_PREF_CANCEL_HIT 312 ++#define POWER8_PME_PM_IC_PREF_CANCEL_L2 313 ++#define POWER8_PME_PM_IC_PREF_CANCEL_PAGE 314 ++#define POWER8_PME_PM_IC_PREF_REQ 315 ++#define POWER8_PME_PM_IC_PREF_WRITE 316 ++#define POWER8_PME_PM_IC_RELOAD_PRIVATE 317 ++#define POWER8_PME_PM_IERAT_RELOAD 318 ++#define POWER8_PME_PM_IERAT_RELOAD_16M 319 ++#define POWER8_PME_PM_IERAT_RELOAD_4K 320 ++#define POWER8_PME_PM_IERAT_RELOAD_64K 321 ++#define POWER8_PME_PM_IFETCH_THROTTLE 322 ++#define POWER8_PME_PM_IFU_L2_TOUCH 323 ++#define POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED 324 ++#define POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD 325 ++#define POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR 326 ++#define POWER8_PME_PM_INST_ALL_FROM_DL4 327 ++#define POWER8_PME_PM_INST_ALL_FROM_DMEM 328 ++#define POWER8_PME_PM_INST_ALL_FROM_L2 329 ++#define POWER8_PME_PM_INST_ALL_FROM_L21_MOD 330 ++#define POWER8_PME_PM_INST_ALL_FROM_L21_SHR 331 ++#define POWER8_PME_PM_INST_ALL_FROM_L2MISS 332 ++#define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST 333 ++#define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER 334 ++#define POWER8_PME_PM_INST_ALL_FROM_L2_MEPF 335 ++#define POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT 336 ++#define POWER8_PME_PM_INST_ALL_FROM_L3 337 ++#define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD 338 ++#define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR 339 ++#define POWER8_PME_PM_INST_ALL_FROM_L31_MOD 340 ++#define POWER8_PME_PM_INST_ALL_FROM_L31_SHR 341 ++#define POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD 342 ++#define POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT 343 ++#define POWER8_PME_PM_INST_ALL_FROM_L3_MEPF 344 ++#define POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT 345 ++#define POWER8_PME_PM_INST_ALL_FROM_LL4 346 ++#define POWER8_PME_PM_INST_ALL_FROM_LMEM 347 ++#define POWER8_PME_PM_INST_ALL_FROM_MEMORY 348 ++#define POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE 349 ++#define POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE 350 ++#define POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD 351 ++#define POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR 352 ++#define POWER8_PME_PM_INST_ALL_FROM_RL4 353 ++#define POWER8_PME_PM_INST_ALL_FROM_RMEM 354 ++#define POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED 355 ++#define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED 356 ++#define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY 357 ++#define POWER8_PME_PM_INST_ALL_PUMP_CPRED 358 ++#define POWER8_PME_PM_INST_ALL_PUMP_MPRED 359 ++#define POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED 360 ++#define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED 361 ++#define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY 362 ++#define POWER8_PME_PM_INST_CHIP_PUMP_CPRED 363 ++#define POWER8_PME_PM_INST_CMPL 364 ++#define POWER8_PME_PM_INST_DISP 365 ++#define POWER8_PME_PM_INST_FROM_DL2L3_MOD 366 ++#define POWER8_PME_PM_INST_FROM_DL2L3_SHR 367 ++#define POWER8_PME_PM_INST_FROM_DL4 368 ++#define POWER8_PME_PM_INST_FROM_DMEM 369 ++#define POWER8_PME_PM_INST_FROM_L1 370 ++#define POWER8_PME_PM_INST_FROM_L2 371 ++#define POWER8_PME_PM_INST_FROM_L21_MOD 372 ++#define POWER8_PME_PM_INST_FROM_L21_SHR 373 ++#define POWER8_PME_PM_INST_FROM_L2MISS 374 ++#define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 375 ++#define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 376 ++#define POWER8_PME_PM_INST_FROM_L2_MEPF 377 ++#define POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT 378 ++#define POWER8_PME_PM_INST_FROM_L3 379 ++#define POWER8_PME_PM_INST_FROM_L31_ECO_MOD 380 ++#define POWER8_PME_PM_INST_FROM_L31_ECO_SHR 381 ++#define POWER8_PME_PM_INST_FROM_L31_MOD 382 ++#define POWER8_PME_PM_INST_FROM_L31_SHR 383 ++#define POWER8_PME_PM_INST_FROM_L3MISS 384 ++#define POWER8_PME_PM_INST_FROM_L3MISS_MOD 385 ++#define POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT 386 ++#define POWER8_PME_PM_INST_FROM_L3_MEPF 387 ++#define POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT 388 ++#define POWER8_PME_PM_INST_FROM_LL4 389 ++#define POWER8_PME_PM_INST_FROM_LMEM 390 ++#define POWER8_PME_PM_INST_FROM_MEMORY 391 ++#define POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE 392 ++#define POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE 393 ++#define POWER8_PME_PM_INST_FROM_RL2L3_MOD 394 ++#define POWER8_PME_PM_INST_FROM_RL2L3_SHR 395 ++#define POWER8_PME_PM_INST_FROM_RL4 396 ++#define POWER8_PME_PM_INST_FROM_RMEM 397 ++#define POWER8_PME_PM_INST_GRP_PUMP_CPRED 398 ++#define POWER8_PME_PM_INST_GRP_PUMP_MPRED 399 ++#define POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY 400 ++#define POWER8_PME_PM_INST_IMC_MATCH_CMPL 401 ++#define POWER8_PME_PM_INST_IMC_MATCH_DISP 402 ++#define POWER8_PME_PM_INST_PUMP_CPRED 403 ++#define POWER8_PME_PM_INST_PUMP_MPRED 404 ++#define POWER8_PME_PM_INST_SYS_PUMP_CPRED 405 ++#define POWER8_PME_PM_INST_SYS_PUMP_MPRED 406 ++#define POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY 407 ++#define POWER8_PME_PM_IOPS_CMPL 408 ++#define POWER8_PME_PM_IOPS_DISP 409 ++#define POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD 410 ++#define POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR 411 ++#define POWER8_PME_PM_IPTEG_FROM_DL4 412 ++#define POWER8_PME_PM_IPTEG_FROM_DMEM 413 ++#define POWER8_PME_PM_IPTEG_FROM_L2 414 ++#define POWER8_PME_PM_IPTEG_FROM_L21_MOD 415 ++#define POWER8_PME_PM_IPTEG_FROM_L21_SHR 416 ++#define POWER8_PME_PM_IPTEG_FROM_L2MISS 417 ++#define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST 418 ++#define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER 419 ++#define POWER8_PME_PM_IPTEG_FROM_L2_MEPF 420 ++#define POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 421 ++#define POWER8_PME_PM_IPTEG_FROM_L3 422 ++#define POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD 423 ++#define POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR 424 ++#define POWER8_PME_PM_IPTEG_FROM_L31_MOD 425 ++#define POWER8_PME_PM_IPTEG_FROM_L31_SHR 426 ++#define POWER8_PME_PM_IPTEG_FROM_L3MISS 427 ++#define POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 428 ++#define POWER8_PME_PM_IPTEG_FROM_L3_MEPF 429 ++#define POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 430 ++#define POWER8_PME_PM_IPTEG_FROM_LL4 431 ++#define POWER8_PME_PM_IPTEG_FROM_LMEM 432 ++#define POWER8_PME_PM_IPTEG_FROM_MEMORY 433 ++#define POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 434 ++#define POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 435 ++#define POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD 436 ++#define POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR 437 ++#define POWER8_PME_PM_IPTEG_FROM_RL4 438 ++#define POWER8_PME_PM_IPTEG_FROM_RMEM 439 ++#define POWER8_PME_PM_ISIDE_DISP 440 ++#define POWER8_PME_PM_ISIDE_DISP_FAIL 441 ++#define POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER 442 ++#define POWER8_PME_PM_ISIDE_L2MEMACC 443 ++#define POWER8_PME_PM_ISIDE_MRU_TOUCH 444 ++#define POWER8_PME_PM_ISLB_MISS 445 ++#define POWER8_PME_PM_ISU_REF_FX0 446 ++#define POWER8_PME_PM_ISU_REF_FX1 447 ++#define POWER8_PME_PM_ISU_REF_FXU 448 ++#define POWER8_PME_PM_ISU_REF_LS0 449 ++#define POWER8_PME_PM_ISU_REF_LS1 450 ++#define POWER8_PME_PM_ISU_REF_LS2 451 ++#define POWER8_PME_PM_ISU_REF_LS3 452 ++#define POWER8_PME_PM_ISU_REJECTS_ALL 453 ++#define POWER8_PME_PM_ISU_REJECT_RES_NA 454 ++#define POWER8_PME_PM_ISU_REJECT_SAR_BYPASS 455 ++#define POWER8_PME_PM_ISU_REJECT_SRC_NA 456 ++#define POWER8_PME_PM_ISU_REJ_VS0 457 ++#define POWER8_PME_PM_ISU_REJ_VS1 458 ++#define POWER8_PME_PM_ISU_REJ_VSU 459 ++#define POWER8_PME_PM_ISYNC 460 ++#define POWER8_PME_PM_ITLB_MISS 461 ++#define POWER8_PME_PM_L1MISS_LAT_EXC_1024 462 ++#define POWER8_PME_PM_L1MISS_LAT_EXC_2048 463 ++#define POWER8_PME_PM_L1MISS_LAT_EXC_256 464 ++#define POWER8_PME_PM_L1MISS_LAT_EXC_32 465 ++#define POWER8_PME_PM_L1PF_L2MEMACC 466 ++#define POWER8_PME_PM_L1_DCACHE_RELOADED_ALL 467 ++#define POWER8_PME_PM_L1_DCACHE_RELOAD_VALID 468 ++#define POWER8_PME_PM_L1_DEMAND_WRITE 469 ++#define POWER8_PME_PM_L1_ICACHE_MISS 470 ++#define POWER8_PME_PM_L1_ICACHE_RELOADED_ALL 471 ++#define POWER8_PME_PM_L1_ICACHE_RELOADED_PREF 472 ++#define POWER8_PME_PM_L2_CASTOUT_MOD 473 ++#define POWER8_PME_PM_L2_CASTOUT_SHR 474 ++#define POWER8_PME_PM_L2_CHIP_PUMP 475 ++#define POWER8_PME_PM_L2_DC_INV 476 ++#define POWER8_PME_PM_L2_DISP_ALL_L2MISS 477 ++#define POWER8_PME_PM_L2_GROUP_PUMP 478 ++#define POWER8_PME_PM_L2_GRP_GUESS_CORRECT 479 ++#define POWER8_PME_PM_L2_GRP_GUESS_WRONG 480 ++#define POWER8_PME_PM_L2_IC_INV 481 ++#define POWER8_PME_PM_L2_INST 482 ++#define POWER8_PME_PM_L2_INST_MISS 483 ++#define POWER8_PME_PM_L2_LD 484 ++#define POWER8_PME_PM_L2_LD_DISP 485 ++#define POWER8_PME_PM_L2_LD_HIT 486 ++#define POWER8_PME_PM_L2_LD_MISS 487 ++#define POWER8_PME_PM_L2_LOC_GUESS_CORRECT 488 ++#define POWER8_PME_PM_L2_LOC_GUESS_WRONG 489 ++#define POWER8_PME_PM_L2_RCLD_DISP 490 ++#define POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR 491 ++#define POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER 492 ++#define POWER8_PME_PM_L2_RCST_DISP 493 ++#define POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR 494 ++#define POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER 495 ++#define POWER8_PME_PM_L2_RC_ST_DONE 496 ++#define POWER8_PME_PM_L2_RTY_LD 497 ++#define POWER8_PME_PM_L2_RTY_ST 498 ++#define POWER8_PME_PM_L2_SN_M_RD_DONE 499 ++#define POWER8_PME_PM_L2_SN_M_WR_DONE 500 ++#define POWER8_PME_PM_L2_SN_SX_I_DONE 501 ++#define POWER8_PME_PM_L2_ST 502 ++#define POWER8_PME_PM_L2_ST_DISP 503 ++#define POWER8_PME_PM_L2_ST_HIT 504 ++#define POWER8_PME_PM_L2_ST_MISS 505 ++#define POWER8_PME_PM_L2_SYS_GUESS_CORRECT 506 ++#define POWER8_PME_PM_L2_SYS_GUESS_WRONG 507 ++#define POWER8_PME_PM_L2_SYS_PUMP 508 ++#define POWER8_PME_PM_L2_TM_REQ_ABORT 509 ++#define POWER8_PME_PM_L2_TM_ST_ABORT_SISTER 510 ++#define POWER8_PME_PM_L3_CINJ 511 ++#define POWER8_PME_PM_L3_CI_HIT 512 ++#define POWER8_PME_PM_L3_CI_MISS 513 ++#define POWER8_PME_PM_L3_CI_USAGE 514 ++#define POWER8_PME_PM_L3_CO 515 ++#define POWER8_PME_PM_L3_CO0_ALLOC 516 ++#define POWER8_PME_PM_L3_CO0_BUSY 517 ++#define POWER8_PME_PM_L3_CO_L31 518 ++#define POWER8_PME_PM_L3_CO_LCO 519 ++#define POWER8_PME_PM_L3_CO_MEM 520 ++#define POWER8_PME_PM_L3_CO_MEPF 521 ++#define POWER8_PME_PM_L3_GRP_GUESS_CORRECT 522 ++#define POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH 523 ++#define POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW 524 ++#define POWER8_PME_PM_L3_HIT 525 ++#define POWER8_PME_PM_L3_L2_CO_HIT 526 ++#define POWER8_PME_PM_L3_L2_CO_MISS 527 ++#define POWER8_PME_PM_L3_LAT_CI_HIT 528 ++#define POWER8_PME_PM_L3_LAT_CI_MISS 529 ++#define POWER8_PME_PM_L3_LD_HIT 530 ++#define POWER8_PME_PM_L3_LD_MISS 531 ++#define POWER8_PME_PM_L3_LD_PREF 532 ++#define POWER8_PME_PM_L3_LOC_GUESS_CORRECT 533 ++#define POWER8_PME_PM_L3_LOC_GUESS_WRONG 534 ++#define POWER8_PME_PM_L3_MISS 535 ++#define POWER8_PME_PM_L3_P0_CO_L31 536 ++#define POWER8_PME_PM_L3_P0_CO_MEM 537 ++#define POWER8_PME_PM_L3_P0_CO_RTY 538 ++#define POWER8_PME_PM_L3_P0_GRP_PUMP 539 ++#define POWER8_PME_PM_L3_P0_LCO_DATA 540 ++#define POWER8_PME_PM_L3_P0_LCO_NO_DATA 541 ++#define POWER8_PME_PM_L3_P0_LCO_RTY 542 ++#define POWER8_PME_PM_L3_P0_NODE_PUMP 543 ++#define POWER8_PME_PM_L3_P0_PF_RTY 544 ++#define POWER8_PME_PM_L3_P0_SN_HIT 545 ++#define POWER8_PME_PM_L3_P0_SN_INV 546 ++#define POWER8_PME_PM_L3_P0_SN_MISS 547 ++#define POWER8_PME_PM_L3_P0_SYS_PUMP 548 ++#define POWER8_PME_PM_L3_P1_CO_L31 549 ++#define POWER8_PME_PM_L3_P1_CO_MEM 550 ++#define POWER8_PME_PM_L3_P1_CO_RTY 551 ++#define POWER8_PME_PM_L3_P1_GRP_PUMP 552 ++#define POWER8_PME_PM_L3_P1_LCO_DATA 553 ++#define POWER8_PME_PM_L3_P1_LCO_NO_DATA 554 ++#define POWER8_PME_PM_L3_P1_LCO_RTY 555 ++#define POWER8_PME_PM_L3_P1_NODE_PUMP 556 ++#define POWER8_PME_PM_L3_P1_PF_RTY 557 ++#define POWER8_PME_PM_L3_P1_SN_HIT 558 ++#define POWER8_PME_PM_L3_P1_SN_INV 559 ++#define POWER8_PME_PM_L3_P1_SN_MISS 560 ++#define POWER8_PME_PM_L3_P1_SYS_PUMP 561 ++#define POWER8_PME_PM_L3_PF0_ALLOC 562 ++#define POWER8_PME_PM_L3_PF0_BUSY 563 ++#define POWER8_PME_PM_L3_PF_HIT_L3 564 ++#define POWER8_PME_PM_L3_PF_MISS_L3 565 ++#define POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE 566 ++#define POWER8_PME_PM_L3_PF_OFF_CHIP_MEM 567 ++#define POWER8_PME_PM_L3_PF_ON_CHIP_CACHE 568 ++#define POWER8_PME_PM_L3_PF_ON_CHIP_MEM 569 ++#define POWER8_PME_PM_L3_PF_USAGE 570 ++#define POWER8_PME_PM_L3_PREF_ALL 571 ++#define POWER8_PME_PM_L3_RD0_ALLOC 572 ++#define POWER8_PME_PM_L3_RD0_BUSY 573 ++#define POWER8_PME_PM_L3_RD_USAGE 574 ++#define POWER8_PME_PM_L3_SN0_ALLOC 575 ++#define POWER8_PME_PM_L3_SN0_BUSY 576 ++#define POWER8_PME_PM_L3_SN_USAGE 577 ++#define POWER8_PME_PM_L3_ST_PREF 578 ++#define POWER8_PME_PM_L3_SW_PREF 579 ++#define POWER8_PME_PM_L3_SYS_GUESS_CORRECT 580 ++#define POWER8_PME_PM_L3_SYS_GUESS_WRONG 581 ++#define POWER8_PME_PM_L3_TRANS_PF 582 ++#define POWER8_PME_PM_L3_WI0_ALLOC 583 ++#define POWER8_PME_PM_L3_WI0_BUSY 584 ++#define POWER8_PME_PM_L3_WI_USAGE 585 ++#define POWER8_PME_PM_LARX_FIN 586 ++#define POWER8_PME_PM_LD_CMPL 587 ++#define POWER8_PME_PM_LD_L3MISS_PEND_CYC 588 ++#define POWER8_PME_PM_LD_MISS_L1 589 ++#define POWER8_PME_PM_LD_REF_L1 590 ++#define POWER8_PME_PM_LD_REF_L1_LSU0 591 ++#define POWER8_PME_PM_LD_REF_L1_LSU1 592 ++#define POWER8_PME_PM_LD_REF_L1_LSU2 593 ++#define POWER8_PME_PM_LD_REF_L1_LSU3 594 ++#define POWER8_PME_PM_LINK_STACK_INVALID_PTR 595 ++#define POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED 596 ++#define POWER8_PME_PM_LS0_ERAT_MISS_PREF 597 ++#define POWER8_PME_PM_LS0_L1_PREF 598 ++#define POWER8_PME_PM_LS0_L1_SW_PREF 599 ++#define POWER8_PME_PM_LS1_ERAT_MISS_PREF 600 ++#define POWER8_PME_PM_LS1_L1_PREF 601 ++#define POWER8_PME_PM_LS1_L1_SW_PREF 602 ++#define POWER8_PME_PM_LSU0_FLUSH_LRQ 603 ++#define POWER8_PME_PM_LSU0_FLUSH_SRQ 604 ++#define POWER8_PME_PM_LSU0_FLUSH_ULD 605 ++#define POWER8_PME_PM_LSU0_FLUSH_UST 606 ++#define POWER8_PME_PM_LSU0_L1_CAM_CANCEL 607 ++#define POWER8_PME_PM_LSU0_LARX_FIN 608 ++#define POWER8_PME_PM_LSU0_LMQ_LHR_MERGE 609 ++#define POWER8_PME_PM_LSU0_NCLD 610 ++#define POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT 611 ++#define POWER8_PME_PM_LSU0_REJECT 612 ++#define POWER8_PME_PM_LSU0_SRQ_STFWD 613 ++#define POWER8_PME_PM_LSU0_STORE_REJECT 614 ++#define POWER8_PME_PM_LSU0_TMA_REQ_L2 615 ++#define POWER8_PME_PM_LSU0_TM_L1_HIT 616 ++#define POWER8_PME_PM_LSU0_TM_L1_MISS 617 ++#define POWER8_PME_PM_LSU1_FLUSH_LRQ 618 ++#define POWER8_PME_PM_LSU1_FLUSH_SRQ 619 ++#define POWER8_PME_PM_LSU1_FLUSH_ULD 620 ++#define POWER8_PME_PM_LSU1_FLUSH_UST 621 ++#define POWER8_PME_PM_LSU1_L1_CAM_CANCEL 622 ++#define POWER8_PME_PM_LSU1_LARX_FIN 623 ++#define POWER8_PME_PM_LSU1_LMQ_LHR_MERGE 624 ++#define POWER8_PME_PM_LSU1_NCLD 625 ++#define POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT 626 ++#define POWER8_PME_PM_LSU1_REJECT 627 ++#define POWER8_PME_PM_LSU1_SRQ_STFWD 628 ++#define POWER8_PME_PM_LSU1_STORE_REJECT 629 ++#define POWER8_PME_PM_LSU1_TMA_REQ_L2 630 ++#define POWER8_PME_PM_LSU1_TM_L1_HIT 631 ++#define POWER8_PME_PM_LSU1_TM_L1_MISS 632 ++#define POWER8_PME_PM_LSU2_FLUSH_LRQ 633 ++#define POWER8_PME_PM_LSU2_FLUSH_SRQ 634 ++#define POWER8_PME_PM_LSU2_FLUSH_ULD 635 ++#define POWER8_PME_PM_LSU2_L1_CAM_CANCEL 636 ++#define POWER8_PME_PM_LSU2_LARX_FIN 637 ++#define POWER8_PME_PM_LSU2_LDF 638 ++#define POWER8_PME_PM_LSU2_LDX 639 ++#define POWER8_PME_PM_LSU2_LMQ_LHR_MERGE 640 ++#define POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT 641 ++#define POWER8_PME_PM_LSU2_REJECT 642 ++#define POWER8_PME_PM_LSU2_SRQ_STFWD 643 ++#define POWER8_PME_PM_LSU2_TMA_REQ_L2 644 ++#define POWER8_PME_PM_LSU2_TM_L1_HIT 645 ++#define POWER8_PME_PM_LSU2_TM_L1_MISS 646 ++#define POWER8_PME_PM_LSU3_FLUSH_LRQ 647 ++#define POWER8_PME_PM_LSU3_FLUSH_SRQ 648 ++#define POWER8_PME_PM_LSU3_FLUSH_ULD 649 ++#define POWER8_PME_PM_LSU3_L1_CAM_CANCEL 650 ++#define POWER8_PME_PM_LSU3_LARX_FIN 651 ++#define POWER8_PME_PM_LSU3_LDF 652 ++#define POWER8_PME_PM_LSU3_LDX 653 ++#define POWER8_PME_PM_LSU3_LMQ_LHR_MERGE 654 ++#define POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT 655 ++#define POWER8_PME_PM_LSU3_REJECT 656 ++#define POWER8_PME_PM_LSU3_SRQ_STFWD 657 ++#define POWER8_PME_PM_LSU3_TMA_REQ_L2 658 ++#define POWER8_PME_PM_LSU3_TM_L1_HIT 659 ++#define POWER8_PME_PM_LSU3_TM_L1_MISS 660 ++#define POWER8_PME_PM_LSU_DERAT_MISS 661 ++#define POWER8_PME_PM_LSU_ERAT_MISS_PREF 662 ++#define POWER8_PME_PM_LSU_FIN 663 ++#define POWER8_PME_PM_LSU_FLUSH_UST 664 ++#define POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC 665 ++#define POWER8_PME_PM_LSU_FX_FIN 666 ++#define POWER8_PME_PM_LSU_L1_PREF 667 ++#define POWER8_PME_PM_LSU_L1_SW_PREF 668 ++#define POWER8_PME_PM_LSU_LDF 669 ++#define POWER8_PME_PM_LSU_LDX 670 ++#define POWER8_PME_PM_LSU_LMQ_FULL_CYC 671 ++#define POWER8_PME_PM_LSU_LMQ_S0_ALLOC 672 ++#define POWER8_PME_PM_LSU_LMQ_S0_VALID 673 ++#define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 674 ++#define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 675 ++#define POWER8_PME_PM_LSU_LRQ_S0_ALLOC 676 ++#define POWER8_PME_PM_LSU_LRQ_S0_VALID 677 ++#define POWER8_PME_PM_LSU_LRQ_S43_ALLOC 678 ++#define POWER8_PME_PM_LSU_LRQ_S43_VALID 679 ++#define POWER8_PME_PM_LSU_MRK_DERAT_MISS 680 ++#define POWER8_PME_PM_LSU_NCLD 681 ++#define POWER8_PME_PM_LSU_NCST 682 ++#define POWER8_PME_PM_LSU_REJECT 683 ++#define POWER8_PME_PM_LSU_REJECT_ERAT_MISS 684 ++#define POWER8_PME_PM_LSU_REJECT_LHS 685 ++#define POWER8_PME_PM_LSU_REJECT_LMQ_FULL 686 ++#define POWER8_PME_PM_LSU_SET_MPRED 687 ++#define POWER8_PME_PM_LSU_SRQ_EMPTY_CYC 688 ++#define POWER8_PME_PM_LSU_SRQ_FULL_CYC 689 ++#define POWER8_PME_PM_LSU_SRQ_S0_ALLOC 690 ++#define POWER8_PME_PM_LSU_SRQ_S0_VALID 691 ++#define POWER8_PME_PM_LSU_SRQ_S39_ALLOC 692 ++#define POWER8_PME_PM_LSU_SRQ_S39_VALID 693 ++#define POWER8_PME_PM_LSU_SRQ_SYNC 694 ++#define POWER8_PME_PM_LSU_SRQ_SYNC_CYC 695 ++#define POWER8_PME_PM_LSU_STORE_REJECT 696 ++#define POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC 697 ++#define POWER8_PME_PM_LWSYNC 698 ++#define POWER8_PME_PM_LWSYNC_HELD 699 ++#define POWER8_PME_PM_MEM_CO 700 ++#define POWER8_PME_PM_MEM_LOC_THRESH_IFU 701 ++#define POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH 702 ++#define POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED 703 ++#define POWER8_PME_PM_MEM_PREF 704 ++#define POWER8_PME_PM_MEM_READ 705 ++#define POWER8_PME_PM_MEM_RWITM 706 ++#define POWER8_PME_PM_MRK_BACK_BR_CMPL 707 ++#define POWER8_PME_PM_MRK_BRU_FIN 708 ++#define POWER8_PME_PM_MRK_BR_CMPL 709 ++#define POWER8_PME_PM_MRK_BR_MPRED_CMPL 710 ++#define POWER8_PME_PM_MRK_BR_TAKEN_CMPL 711 ++#define POWER8_PME_PM_MRK_CRU_FIN 712 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD 713 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 714 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR 715 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 716 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL4 717 ++#define POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC 718 ++#define POWER8_PME_PM_MRK_DATA_FROM_DMEM 719 ++#define POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC 720 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2 721 ++#define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD 722 ++#define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 723 ++#define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR 724 ++#define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 725 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS 726 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC 727 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_CYC 728 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 729 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 730 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 731 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 732 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF 733 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 734 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 735 ++#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 736 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3 737 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD 738 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC 739 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR 740 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC 741 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD 742 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 743 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR 744 ++#define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 745 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS 746 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC 747 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_CYC 748 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 749 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 750 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF 751 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 752 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 753 ++#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 754 ++#define POWER8_PME_PM_MRK_DATA_FROM_LL4 755 ++#define POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC 756 ++#define POWER8_PME_PM_MRK_DATA_FROM_LMEM 757 ++#define POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC 758 ++#define POWER8_PME_PM_MRK_DATA_FROM_MEM 759 ++#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY 760 ++#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC 761 ++#define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 762 ++#define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 763 ++#define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 764 ++#define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 765 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD 766 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 767 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR 768 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 769 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL4 770 ++#define POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC 771 ++#define POWER8_PME_PM_MRK_DATA_FROM_RMEM 772 ++#define POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC 773 ++#define POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV 774 ++#define POWER8_PME_PM_MRK_DERAT_MISS 775 ++#define POWER8_PME_PM_MRK_DERAT_MISS_16G 776 ++#define POWER8_PME_PM_MRK_DERAT_MISS_16M 777 ++#define POWER8_PME_PM_MRK_DERAT_MISS_4K 778 ++#define POWER8_PME_PM_MRK_DERAT_MISS_64K 779 ++#define POWER8_PME_PM_MRK_DFU_FIN 780 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 781 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 782 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_DL4 783 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_DMEM 784 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2 785 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD 786 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR 787 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS 788 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 789 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 790 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF 791 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 792 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L3 793 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD 794 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR 795 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD 796 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR 797 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS 798 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 799 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF 800 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 801 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_LL4 802 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_LMEM 803 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY 804 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 805 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 806 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 807 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 808 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_RL4 809 ++#define POWER8_PME_PM_MRK_DPTEG_FROM_RMEM 810 ++#define POWER8_PME_PM_MRK_DTLB_MISS 811 ++#define POWER8_PME_PM_MRK_DTLB_MISS_16G 812 ++#define POWER8_PME_PM_MRK_DTLB_MISS_16M 813 ++#define POWER8_PME_PM_MRK_DTLB_MISS_4K 814 ++#define POWER8_PME_PM_MRK_DTLB_MISS_64K 815 ++#define POWER8_PME_PM_MRK_FAB_RSP_BKILL 816 ++#define POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC 817 ++#define POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY 818 ++#define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM 819 ++#define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 820 ++#define POWER8_PME_PM_MRK_FAB_RSP_MATCH 821 ++#define POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC 822 ++#define POWER8_PME_PM_MRK_FAB_RSP_RD_RTY 823 ++#define POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV 824 ++#define POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC 825 ++#define POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY 826 ++#define POWER8_PME_PM_MRK_FILT_MATCH 827 ++#define POWER8_PME_PM_MRK_FIN_STALL_CYC 828 ++#define POWER8_PME_PM_MRK_FXU_FIN 829 ++#define POWER8_PME_PM_MRK_GRP_CMPL 830 ++#define POWER8_PME_PM_MRK_GRP_IC_MISS 831 ++#define POWER8_PME_PM_MRK_GRP_NTC 832 ++#define POWER8_PME_PM_MRK_INST_CMPL 833 ++#define POWER8_PME_PM_MRK_INST_DECODED 834 ++#define POWER8_PME_PM_MRK_INST_DISP 835 ++#define POWER8_PME_PM_MRK_INST_FIN 836 ++#define POWER8_PME_PM_MRK_INST_FROM_L3MISS 837 ++#define POWER8_PME_PM_MRK_INST_ISSUED 838 ++#define POWER8_PME_PM_MRK_INST_TIMEO 839 ++#define POWER8_PME_PM_MRK_L1_ICACHE_MISS 840 ++#define POWER8_PME_PM_MRK_L1_RELOAD_VALID 841 ++#define POWER8_PME_PM_MRK_L2_RC_DISP 842 ++#define POWER8_PME_PM_MRK_L2_RC_DONE 843 ++#define POWER8_PME_PM_MRK_LARX_FIN 844 ++#define POWER8_PME_PM_MRK_LD_MISS_EXPOSED 845 ++#define POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC 846 ++#define POWER8_PME_PM_MRK_LD_MISS_L1 847 ++#define POWER8_PME_PM_MRK_LD_MISS_L1_CYC 848 ++#define POWER8_PME_PM_MRK_LSU_FIN 849 ++#define POWER8_PME_PM_MRK_LSU_FLUSH 850 ++#define POWER8_PME_PM_MRK_LSU_FLUSH_LRQ 851 ++#define POWER8_PME_PM_MRK_LSU_FLUSH_SRQ 852 ++#define POWER8_PME_PM_MRK_LSU_FLUSH_ULD 853 ++#define POWER8_PME_PM_MRK_LSU_FLUSH_UST 854 ++#define POWER8_PME_PM_MRK_LSU_REJECT 855 ++#define POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS 856 ++#define POWER8_PME_PM_MRK_NTF_FIN 857 ++#define POWER8_PME_PM_MRK_RUN_CYC 858 ++#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF 859 ++#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF 860 ++#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD 861 ++#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 862 ++#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 863 ++#define POWER8_PME_PM_MRK_STALL_CMPLU_CYC 864 ++#define POWER8_PME_PM_MRK_STCX_FAIL 865 ++#define POWER8_PME_PM_MRK_ST_CMPL 866 ++#define POWER8_PME_PM_MRK_ST_CMPL_INT 867 ++#define POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 868 ++#define POWER8_PME_PM_MRK_ST_FWD 869 ++#define POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 870 ++#define POWER8_PME_PM_MRK_ST_NEST 871 ++#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF 872 ++#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF 873 ++#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD 874 ++#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 875 ++#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 876 ++#define POWER8_PME_PM_MRK_VSU_FIN 877 ++#define POWER8_PME_PM_MULT_MRK 878 ++#define POWER8_PME_PM_NESTED_TEND 879 ++#define POWER8_PME_PM_NEST_REF_CLK 880 ++#define POWER8_PME_PM_NON_FAV_TBEGIN 881 ++#define POWER8_PME_PM_NON_TM_RST_SC 882 ++#define POWER8_PME_PM_NTCG_ALL_FIN 883 ++#define POWER8_PME_PM_OUTER_TBEGIN 884 ++#define POWER8_PME_PM_OUTER_TEND 885 ++#define POWER8_PME_PM_PMC1_OVERFLOW 886 ++#define POWER8_PME_PM_PMC2_OVERFLOW 887 ++#define POWER8_PME_PM_PMC2_REWIND 888 ++#define POWER8_PME_PM_PMC2_SAVED 889 ++#define POWER8_PME_PM_PMC3_OVERFLOW 890 ++#define POWER8_PME_PM_PMC4_OVERFLOW 891 ++#define POWER8_PME_PM_PMC4_REWIND 892 ++#define POWER8_PME_PM_PMC4_SAVED 893 ++#define POWER8_PME_PM_PMC5_OVERFLOW 894 ++#define POWER8_PME_PM_PMC6_OVERFLOW 895 ++#define POWER8_PME_PM_PREF_TRACKED 896 ++#define POWER8_PME_PM_PREF_TRACK_EFF 897 ++#define POWER8_PME_PM_PREF_TRACK_INEFF 898 ++#define POWER8_PME_PM_PREF_TRACK_MOD 899 ++#define POWER8_PME_PM_PREF_TRACK_MOD_L2 900 ++#define POWER8_PME_PM_PREF_TRACK_MOD_L3 901 ++#define POWER8_PME_PM_PROBE_NOP_DISP 902 ++#define POWER8_PME_PM_PTE_PREFETCH 903 ++#define POWER8_PME_PM_PUMP_CPRED 904 ++#define POWER8_PME_PM_PUMP_MPRED 905 ++#define POWER8_PME_PM_RC0_ALLOC 906 ++#define POWER8_PME_PM_RC0_BUSY 907 ++#define POWER8_PME_PM_RC_LIFETIME_EXC_1024 908 ++#define POWER8_PME_PM_RC_LIFETIME_EXC_2048 909 ++#define POWER8_PME_PM_RC_LIFETIME_EXC_256 910 ++#define POWER8_PME_PM_RC_LIFETIME_EXC_32 911 ++#define POWER8_PME_PM_RC_USAGE 912 ++#define POWER8_PME_PM_RD_CLEARING_SC 913 ++#define POWER8_PME_PM_RD_FORMING_SC 914 ++#define POWER8_PME_PM_RD_HIT_PF 915 ++#define POWER8_PME_PM_REAL_SRQ_FULL 916 ++#define POWER8_PME_PM_RUN_CYC 917 ++#define POWER8_PME_PM_RUN_CYC_SMT2_MODE 918 ++#define POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE 919 ++#define POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE 920 ++#define POWER8_PME_PM_RUN_CYC_SMT4_MODE 921 ++#define POWER8_PME_PM_RUN_CYC_SMT8_MODE 922 ++#define POWER8_PME_PM_RUN_CYC_ST_MODE 923 ++#define POWER8_PME_PM_RUN_INST_CMPL 924 ++#define POWER8_PME_PM_RUN_PURR 925 ++#define POWER8_PME_PM_RUN_SPURR 926 ++#define POWER8_PME_PM_SEC_ERAT_HIT 927 ++#define POWER8_PME_PM_SHL_CREATED 928 ++#define POWER8_PME_PM_SHL_ST_CONVERT 929 ++#define POWER8_PME_PM_SHL_ST_DISABLE 930 ++#define POWER8_PME_PM_SN0_ALLOC 931 ++#define POWER8_PME_PM_SN0_BUSY 932 ++#define POWER8_PME_PM_SNOOP_TLBIE 933 ++#define POWER8_PME_PM_SNP_TM_HIT_M 934 ++#define POWER8_PME_PM_SNP_TM_HIT_T 935 ++#define POWER8_PME_PM_SN_USAGE 936 ++#define POWER8_PME_PM_STALL_END_GCT_EMPTY 937 ++#define POWER8_PME_PM_STCX_FAIL 938 ++#define POWER8_PME_PM_STCX_LSU 939 ++#define POWER8_PME_PM_ST_CAUSED_FAIL 940 ++#define POWER8_PME_PM_ST_CMPL 941 ++#define POWER8_PME_PM_ST_FIN 942 ++#define POWER8_PME_PM_ST_FWD 943 ++#define POWER8_PME_PM_ST_MISS_L1 944 ++#define POWER8_PME_PM_SUSPENDED 945 ++#define POWER8_PME_PM_SWAP_CANCEL 946 ++#define POWER8_PME_PM_SWAP_CANCEL_GPR 947 ++#define POWER8_PME_PM_SWAP_COMPLETE 948 ++#define POWER8_PME_PM_SWAP_COMPLETE_GPR 949 ++#define POWER8_PME_PM_SYNC_MRK_BR_LINK 950 ++#define POWER8_PME_PM_SYNC_MRK_BR_MPRED 951 ++#define POWER8_PME_PM_SYNC_MRK_FX_DIVIDE 952 ++#define POWER8_PME_PM_SYNC_MRK_L2HIT 953 ++#define POWER8_PME_PM_SYNC_MRK_L2MISS 954 ++#define POWER8_PME_PM_SYNC_MRK_L3MISS 955 ++#define POWER8_PME_PM_SYNC_MRK_PROBE_NOP 956 ++#define POWER8_PME_PM_SYS_PUMP_CPRED 957 ++#define POWER8_PME_PM_SYS_PUMP_MPRED 958 ++#define POWER8_PME_PM_SYS_PUMP_MPRED_RTY 959 ++#define POWER8_PME_PM_TABLEWALK_CYC 960 ++#define POWER8_PME_PM_TABLEWALK_CYC_PREF 961 ++#define POWER8_PME_PM_TABORT_TRECLAIM 962 ++#define POWER8_PME_PM_TB_BIT_TRANS 963 ++#define POWER8_PME_PM_TEND_PEND_CYC 964 ++#define POWER8_PME_PM_THRD_ALL_RUN_CYC 965 ++#define POWER8_PME_PM_THRD_CONC_RUN_INST 966 ++#define POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC 967 ++#define POWER8_PME_PM_THRD_PRIO_0_1_CYC 968 ++#define POWER8_PME_PM_THRD_PRIO_2_3_CYC 969 ++#define POWER8_PME_PM_THRD_PRIO_4_5_CYC 970 ++#define POWER8_PME_PM_THRD_PRIO_6_7_CYC 971 ++#define POWER8_PME_PM_THRD_REBAL_CYC 972 ++#define POWER8_PME_PM_THRESH_EXC_1024 973 ++#define POWER8_PME_PM_THRESH_EXC_128 974 ++#define POWER8_PME_PM_THRESH_EXC_2048 975 ++#define POWER8_PME_PM_THRESH_EXC_256 976 ++#define POWER8_PME_PM_THRESH_EXC_32 977 ++#define POWER8_PME_PM_THRESH_EXC_4096 978 ++#define POWER8_PME_PM_THRESH_EXC_512 979 ++#define POWER8_PME_PM_THRESH_EXC_64 980 ++#define POWER8_PME_PM_THRESH_MET 981 ++#define POWER8_PME_PM_THRESH_NOT_MET 982 ++#define POWER8_PME_PM_TLBIE_FIN 983 ++#define POWER8_PME_PM_TLB_MISS 984 ++#define POWER8_PME_PM_TM_BEGIN_ALL 985 ++#define POWER8_PME_PM_TM_CAM_OVERFLOW 986 ++#define POWER8_PME_PM_TM_CAP_OVERFLOW 987 ++#define POWER8_PME_PM_TM_END_ALL 988 ++#define POWER8_PME_PM_TM_FAIL_CONF_NON_TM 989 ++#define POWER8_PME_PM_TM_FAIL_CON_TM 990 ++#define POWER8_PME_PM_TM_FAIL_DISALLOW 991 ++#define POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 992 ++#define POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT 993 ++#define POWER8_PME_PM_TM_FAIL_SELF 994 ++#define POWER8_PME_PM_TM_FAIL_TLBIE 995 ++#define POWER8_PME_PM_TM_FAIL_TX_CONFLICT 996 ++#define POWER8_PME_PM_TM_FAV_CAUSED_FAIL 997 ++#define POWER8_PME_PM_TM_LD_CAUSED_FAIL 998 ++#define POWER8_PME_PM_TM_LD_CONF 999 ++#define POWER8_PME_PM_TM_RST_SC 1000 ++#define POWER8_PME_PM_TM_SC_CO 1001 ++#define POWER8_PME_PM_TM_ST_CAUSED_FAIL 1002 ++#define POWER8_PME_PM_TM_ST_CONF 1003 ++#define POWER8_PME_PM_TM_TBEGIN 1004 ++#define POWER8_PME_PM_TM_TRANS_RUN_CYC 1005 ++#define POWER8_PME_PM_TM_TRANS_RUN_INST 1006 ++#define POWER8_PME_PM_TM_TRESUME 1007 ++#define POWER8_PME_PM_TM_TSUSPEND 1008 ++#define POWER8_PME_PM_TM_TX_PASS_RUN_CYC 1009 ++#define POWER8_PME_PM_TM_TX_PASS_RUN_INST 1010 ++#define POWER8_PME_PM_UP_PREF_L3 1011 ++#define POWER8_PME_PM_UP_PREF_POINTER 1012 ++#define POWER8_PME_PM_VSU0_16FLOP 1013 ++#define POWER8_PME_PM_VSU0_1FLOP 1014 ++#define POWER8_PME_PM_VSU0_2FLOP 1015 ++#define POWER8_PME_PM_VSU0_4FLOP 1016 ++#define POWER8_PME_PM_VSU0_8FLOP 1017 ++#define POWER8_PME_PM_VSU0_COMPLEX_ISSUED 1018 ++#define POWER8_PME_PM_VSU0_CY_ISSUED 1019 ++#define POWER8_PME_PM_VSU0_DD_ISSUED 1020 ++#define POWER8_PME_PM_VSU0_DP_2FLOP 1021 ++#define POWER8_PME_PM_VSU0_DP_FMA 1022 ++#define POWER8_PME_PM_VSU0_DP_FSQRT_FDIV 1023 ++#define POWER8_PME_PM_VSU0_DQ_ISSUED 1024 ++#define POWER8_PME_PM_VSU0_EX_ISSUED 1025 ++#define POWER8_PME_PM_VSU0_FIN 1026 ++#define POWER8_PME_PM_VSU0_FMA 1027 ++#define POWER8_PME_PM_VSU0_FPSCR 1028 ++#define POWER8_PME_PM_VSU0_FSQRT_FDIV 1029 ++#define POWER8_PME_PM_VSU0_PERMUTE_ISSUED 1030 ++#define POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED 1031 ++#define POWER8_PME_PM_VSU0_SIMPLE_ISSUED 1032 ++#define POWER8_PME_PM_VSU0_SINGLE 1033 ++#define POWER8_PME_PM_VSU0_SQ 1034 ++#define POWER8_PME_PM_VSU0_STF 1035 ++#define POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED 1036 ++#define POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED 1037 ++#define POWER8_PME_PM_VSU1_16FLOP 1038 ++#define POWER8_PME_PM_VSU1_1FLOP 1039 ++#define POWER8_PME_PM_VSU1_2FLOP 1040 ++#define POWER8_PME_PM_VSU1_4FLOP 1041 ++#define POWER8_PME_PM_VSU1_8FLOP 1042 ++#define POWER8_PME_PM_VSU1_COMPLEX_ISSUED 1043 ++#define POWER8_PME_PM_VSU1_CY_ISSUED 1044 ++#define POWER8_PME_PM_VSU1_DD_ISSUED 1045 ++#define POWER8_PME_PM_VSU1_DP_2FLOP 1046 ++#define POWER8_PME_PM_VSU1_DP_FMA 1047 ++#define POWER8_PME_PM_VSU1_DP_FSQRT_FDIV 1048 ++#define POWER8_PME_PM_VSU1_DQ_ISSUED 1049 ++#define POWER8_PME_PM_VSU1_EX_ISSUED 1050 ++#define POWER8_PME_PM_VSU1_FIN 1051 ++#define POWER8_PME_PM_VSU1_FMA 1052 ++#define POWER8_PME_PM_VSU1_FPSCR 1053 ++#define POWER8_PME_PM_VSU1_FSQRT_FDIV 1054 ++#define POWER8_PME_PM_VSU1_PERMUTE_ISSUED 1055 ++#define POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED 1056 ++#define POWER8_PME_PM_VSU1_SIMPLE_ISSUED 1057 ++#define POWER8_PME_PM_VSU1_SINGLE 1058 ++#define POWER8_PME_PM_VSU1_SQ 1059 ++#define POWER8_PME_PM_VSU1_STF 1060 ++#define POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED 1061 ++#define POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED 1062 + + static const pme_power_entry_t power8_pe[] = { ++[ POWER8_PME_PM_1LPAR_CYC ] = { ++ .pme_name = "PM_1LPAR_CYC", ++ .pme_code = 0x1f05e, ++ .pme_short_desc = "Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar", ++ .pme_long_desc = "Number of cycles in single lpar mode.", ++}, + [ POWER8_PME_PM_1PLUS_PPC_CMPL ] = { + .pme_name = "PM_1PLUS_PPC_CMPL", + .pme_code = 0x100f2, +- .pme_short_desc = "one or more ppc instructions completed", +- .pme_long_desc = "one or more ppc instructions finished", ++ .pme_short_desc = "1 or more ppc insts finished", ++ .pme_long_desc = "1 or more ppc insts finished (completed).", + }, + [ POWER8_PME_PM_1PLUS_PPC_DISP ] = { + .pme_name = "PM_1PLUS_PPC_DISP", + .pme_code = 0x400f2, + .pme_short_desc = "Cycles at least one Instr Dispatched", +- .pme_long_desc = "Cycles at least one Instr Dispatched", ++ .pme_long_desc = "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521", ++}, ++[ POWER8_PME_PM_2LPAR_CYC ] = { ++ .pme_name = "PM_2LPAR_CYC", ++ .pme_code = 0x2006e, ++ .pme_short_desc = "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to Lpar1", ++ .pme_long_desc = "Number of cycles in 2 lpar mode.", ++}, ++[ POWER8_PME_PM_4LPAR_CYC ] = { ++ .pme_name = "PM_4LPAR_CYC", ++ .pme_code = 0x4e05e, ++ .pme_short_desc = "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and threads 6-7 belong to lpar3", ++ .pme_long_desc = "Number of cycles in 4 LPAR mode.", ++}, ++[ POWER8_PME_PM_ALL_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_ALL_CHIP_PUMP_CPRED", ++ .pme_code = 0x610050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)", ++}, ++[ POWER8_PME_PM_ALL_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_ALL_GRP_PUMP_CPRED", ++ .pme_code = 0x520050, ++ .pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++}, ++[ POWER8_PME_PM_ALL_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_ALL_GRP_PUMP_MPRED", ++ .pme_code = 0x620052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_ALL_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x610052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++}, ++[ POWER8_PME_PM_ALL_PUMP_CPRED ] = { ++ .pme_name = "PM_ALL_PUMP_CPRED", ++ .pme_code = 0x610054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++}, ++[ POWER8_PME_PM_ALL_PUMP_MPRED ] = { ++ .pme_name = "PM_ALL_PUMP_MPRED", ++ .pme_code = 0x640052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++}, ++[ POWER8_PME_PM_ALL_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_ALL_SYS_PUMP_CPRED", ++ .pme_code = 0x630050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++}, ++[ POWER8_PME_PM_ALL_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_ALL_SYS_PUMP_MPRED", ++ .pme_code = 0x630052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_ALL_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x640050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", + }, + [ POWER8_PME_PM_ANY_THRD_RUN_CYC ] = { + .pme_name = "PM_ANY_THRD_RUN_CYC", + .pme_code = 0x100fa, +- .pme_short_desc = "Any thread in run_cycles (was one thread in run_cycles)", +- .pme_long_desc = "One of threads in run_cycles", +-}, +-[ POWER8_PME_PM_BR_MPRED_CMPL ] = { +- .pme_name = "PM_BR_MPRED_CMPL", +- .pme_code = 0x400f6, +- .pme_short_desc = "Number of Branch Mispredicts", +- .pme_long_desc = "Number of Branch Mispredicts", +-}, +-[ POWER8_PME_PM_BR_TAKEN_CMPL ] = { +- .pme_name = "PM_BR_TAKEN_CMPL", +- .pme_code = 0x200fa, +- .pme_short_desc = "Branch Taken", +- .pme_long_desc = "New event for Branch Taken", +-}, +-[ POWER8_PME_PM_CYC ] = { +- .pme_name = "PM_CYC", +- .pme_code = 0x100f0, +- .pme_short_desc = "Cycles", +- .pme_long_desc = "Cycles", +-}, +-[ POWER8_PME_PM_DATA_FROM_L2MISS ] = { +- .pme_name = "PM_DATA_FROM_L2MISS", +- .pme_code = 0x200fe, +- .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", +- .pme_long_desc = "Demand LD - L2 Miss (not L2 hit)", +-}, +-[ POWER8_PME_PM_DATA_FROM_L3MISS ] = { +- .pme_name = "PM_DATA_FROM_L3MISS", +- .pme_code = 0x300fe, +- .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", +- .pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", +-}, +-[ POWER8_PME_PM_DATA_FROM_MEM ] = { +- .pme_name = "PM_DATA_FROM_MEM", +- .pme_code = 0x400fe, +- .pme_short_desc = "Data cache reload from memory (including L4)", +- .pme_long_desc = "data from Memory", +-}, +-[ POWER8_PME_PM_DTLB_MISS ] = { +- .pme_name = "PM_DTLB_MISS", +- .pme_code = 0x300fc, +- .pme_short_desc = "Data PTEG Reloaded (DTLB Miss)", +- .pme_long_desc = "Data PTEG reload", +-}, +-[ POWER8_PME_PM_EXT_INT ] = { +- .pme_name = "PM_EXT_INT", +- .pme_code = 0x200f8, +- .pme_short_desc = "external interrupt", +- .pme_long_desc = "external interrupt", +-}, +-[ POWER8_PME_PM_FLOP ] = { +- .pme_name = "PM_FLOP", +- .pme_code = 0x100f4, +- .pme_short_desc = "Floating Point Operations Finished", +- .pme_long_desc = "Floating Point Operations Finished", +-}, +-[ POWER8_PME_PM_FLUSH ] = { +- .pme_name = "PM_FLUSH", +- .pme_code = 0x400f8, +- .pme_short_desc = "Flush (any type)", +- .pme_long_desc = "Flush (any type)", +-}, +-[ POWER8_PME_PM_GCT_NOSLOT_CYC ] = { +- .pme_name = "PM_GCT_NOSLOT_CYC", +- .pme_code = 0x100f8, +- .pme_short_desc = "Pipeline empty (No itags assigned , no GCT slots used)", +- .pme_long_desc = "No itags assigned", +-}, +-[ POWER8_PME_PM_IERAT_MISS ] = { +- .pme_name = "PM_IERAT_MISS", +- .pme_code = 0x100f6, +- .pme_short_desc = "IERAT Reloaded (Miss)", +- .pme_long_desc = "Cycles Instruction ERAT was reloaded", +-}, +-[ POWER8_PME_PM_INST_DISP ] = { +- .pme_name = "PM_INST_DISP", +- .pme_code = 0x200f2, +- .pme_short_desc = "Number of PPC Dispatched", +- .pme_long_desc = "Number of PPC Dispatched", +-}, +-[ POWER8_PME_PM_INST_FROM_L3MISS ] = { +- .pme_name = "PM_INST_FROM_L3MISS", +- .pme_code = 0x300fa, +- .pme_short_desc = "Inst from L3 miss", +- .pme_long_desc = "A Instruction cacheline request resolved from a location that was beyond the local L3 cache", +-}, +-[ POWER8_PME_PM_ITLB_MISS ] = { +- .pme_name = "PM_ITLB_MISS", +- .pme_code = 0x400fc, +- .pme_short_desc = "ITLB Reloaded", +- .pme_long_desc = "ITLB Reloaded (always zero on POWER6)", +-}, +-[ POWER8_PME_PM_L1_DCACHE_RELOAD_VALID ] = { +- .pme_name = "PM_L1_DCACHE_RELOAD_VALID", +- .pme_code = 0x300f6, +- .pme_short_desc = "DL1 reloaded due to Demand Load", +- .pme_long_desc = "DL1 reloaded due to Demand Load", +-}, +-[ POWER8_PME_PM_L1_ICACHE_MISS ] = { +- .pme_name = "PM_L1_ICACHE_MISS", +- .pme_code = 0x200fc, +- .pme_short_desc = "Demand iCache Miss", +- .pme_long_desc = "Demand iCache Miss", +-}, +-[ POWER8_PME_PM_LD_MISS_L1 ] = { +- .pme_name = "PM_LD_MISS_L1", +- .pme_code = 0x400f0, +- .pme_short_desc = "Load Missed L1", +- .pme_long_desc = "Load Missed L1", +-}, +-[ POWER8_PME_PM_LSU_DERAT_MISS ] = { +- .pme_name = "PM_LSU_DERAT_MISS", +- .pme_code = 0x200f6, +- .pme_short_desc = "DERAT Reloaded (Miss)", +- .pme_long_desc = "DERAT Reloaded due to a DERAT miss", +-}, +-[ POWER8_PME_PM_MRK_BR_MPRED_CMPL ] = { +- .pme_name = "PM_MRK_BR_MPRED_CMPL", +- .pme_code = 0x300e4, +- .pme_short_desc = "Marked Branch Mispredicted", +- .pme_long_desc = "Marked Branch Mispredicted", +-}, +-[ POWER8_PME_PM_MRK_BR_TAKEN_CMPL ] = { +- .pme_name = "PM_MRK_BR_TAKEN_CMPL", +- .pme_code = 0x100e2, +- .pme_short_desc = "Marked Branch Taken", +- .pme_long_desc = "Marked Branch Taken completed", +-}, +-[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS ] = { +- .pme_name = "PM_MRK_DATA_FROM_L2MISS", +- .pme_code = 0x400e8, +- .pme_short_desc = "Data cache reload L2 miss", +- .pme_long_desc = "sampled load resolved beyond L2", +-}, +-[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = { +- .pme_name = "PM_MRK_DATA_FROM_L3MISS", +- .pme_code = 0x200e4, +- .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load", +- .pme_long_desc = "sampled load resolved beyond L3", +-}, +-[ POWER8_PME_PM_MRK_DATA_FROM_MEM ] = { +- .pme_name = "PM_MRK_DATA_FROM_MEM", +- .pme_code = 0x200e0, +- .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", +- .pme_long_desc = "sampled load resolved from memory", +-}, +-[ POWER8_PME_PM_MRK_DERAT_MISS ] = { +- .pme_name = "PM_MRK_DERAT_MISS", +- .pme_code = 0x300e6, +- .pme_short_desc = "Erat Miss (TLB Access) All page sizes", +- .pme_long_desc = "Erat Miss (TLB Access) All page sizes", +-}, +-[ POWER8_PME_PM_MRK_DTLB_MISS ] = { +- .pme_name = "PM_MRK_DTLB_MISS", +- .pme_code = 0x400e4, +- .pme_short_desc = "Marked dtlb miss", +- .pme_long_desc = "sampled Instruction dtlb miss", +-}, +-[ POWER8_PME_PM_MRK_INST_CMPL ] = { +- .pme_name = "PM_MRK_INST_CMPL", +- .pme_code = 0x400e0, +- .pme_short_desc = "marked instruction completed", +- .pme_long_desc = "Marked group complete", +-}, +-[ POWER8_PME_PM_MRK_INST_DISP ] = { +- .pme_name = "PM_MRK_INST_DISP", +- .pme_code = 0x100e0, +- .pme_short_desc = "Marked Instruction dispatched", +- .pme_long_desc = "The thread has dispatched a randomly sampled marked instruction", +-}, +-[ POWER8_PME_PM_MRK_INST_FROM_L3MISS ] = { +- .pme_name = "PM_MRK_INST_FROM_L3MISS", +- .pme_code = 0x400e6, +- .pme_short_desc = "sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache", +- .pme_long_desc = "sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache", +-}, +-[ POWER8_PME_PM_MRK_L1_ICACHE_MISS ] = { +- .pme_name = "PM_MRK_L1_ICACHE_MISS", +- .pme_code = 0x100e4, +- .pme_short_desc = "Marked L1 Icache Miss", +- .pme_long_desc = "sampled Instruction suffered an icache Miss", +-}, +-[ POWER8_PME_PM_MRK_L1_RELOAD_VALID ] = { +- .pme_name = "PM_MRK_L1_RELOAD_VALID", +- .pme_code = 0x100ea, +- .pme_short_desc = "Marked demand reload", +- .pme_long_desc = "Sampled Instruction had a data reload", +-}, +-[ POWER8_PME_PM_MRK_LD_MISS_L1 ] = { +- .pme_name = "PM_MRK_LD_MISS_L1", +- .pme_code = 0x200e2, +- .pme_short_desc = "Marked DL1 Demand Miss counted at exec time", +- .pme_long_desc = "Marked DL1 Demand Miss", +-}, +-[ POWER8_PME_PM_MRK_ST_CMPL ] = { +- .pme_name = "PM_MRK_ST_CMPL", +- .pme_code = 0x300e2, +- .pme_short_desc = "Marked store completed", +- .pme_long_desc = "marked store completed and sent to nest", +-}, +-[ POWER8_PME_PM_RUN_CYC ] = { +- .pme_name = "PM_RUN_CYC", +- .pme_code = 0x600f4, +- .pme_short_desc = "Run_cycles", +- .pme_long_desc = "Run_cycles", +-}, +-[ POWER8_PME_PM_RUN_INST_CMPL ] = { +- .pme_name = "PM_RUN_INST_CMPL", +- .pme_code = 0x500fa, +- .pme_short_desc = "Run_Instructions", +- .pme_long_desc = "Run_Instructions", +-}, +-[ POWER8_PME_PM_RUN_PURR ] = { +- .pme_name = "PM_RUN_PURR", +- .pme_code = 0x400f4, +- .pme_short_desc = "Run_PURR", +- .pme_long_desc = "Run_PURR", +-}, +-[ POWER8_PME_PM_ST_FIN ] = { +- .pme_name = "PM_ST_FIN", +- .pme_code = 0x200f0, +- .pme_short_desc = "Store Instructions Finished (store sent to nest)", +- .pme_long_desc = "Store Instructions Finished", +-}, +-[ POWER8_PME_PM_ST_MISS_L1 ] = { +- .pme_name = "PM_ST_MISS_L1", +- .pme_code = 0x300f0, +- .pme_short_desc = "Store Missed L1", +- .pme_long_desc = "Store Missed L1", +-}, +-[ POWER8_PME_PM_TB_BIT_TRANS ] = { +- .pme_name = "PM_TB_BIT_TRANS", +- .pme_code = 0x300f8, +- .pme_short_desc = "timebase event", +- .pme_long_desc = "timebase event", +-}, +-[ POWER8_PME_PM_THRD_CONC_RUN_INST ] = { +- .pme_name = "PM_THRD_CONC_RUN_INST", +- .pme_code = 0x300f4, +- .pme_short_desc = "Concurrent Run Instructions", +- .pme_long_desc = "PPC Instructions Finished when both threads in run_cycles", +-}, +-[ POWER8_PME_PM_THRESH_EXC_1024 ] = { +- .pme_name = "PM_THRESH_EXC_1024", +- .pme_code = 0x300ea, +- .pme_short_desc = "Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024", +- .pme_long_desc = "Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024", +-}, +-[ POWER8_PME_PM_THRESH_EXC_128 ] = { +- .pme_name = "PM_THRESH_EXC_128", +- .pme_code = 0x400ea, +- .pme_short_desc = "Threshold counter exceeded a value of 128", +- .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128", +-}, +-[ POWER8_PME_PM_THRESH_EXC_2048 ] = { +- .pme_name = "PM_THRESH_EXC_2048", +- .pme_code = 0x400ec, +- .pme_short_desc = "Threshold counter exceeded a value of 2048", +- .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048", +-}, +-[ POWER8_PME_PM_THRESH_EXC_256 ] = { +- .pme_name = "PM_THRESH_EXC_256", +- .pme_code = 0x100e8, +- .pme_short_desc = "Threshold counter exceed a count of 256", +- .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256", +-}, +-[ POWER8_PME_PM_THRESH_EXC_32 ] = { +- .pme_name = "PM_THRESH_EXC_32", +- .pme_code = 0x200e6, +- .pme_short_desc = "Threshold counter exceeded a value of 32", +- .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32", +-}, +-[ POWER8_PME_PM_THRESH_EXC_4096 ] = { +- .pme_name = "PM_THRESH_EXC_4096", +- .pme_code = 0x100e6, +- .pme_short_desc = "Threshold counter exceed a count of 4096", +- .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096", +-}, +-[ POWER8_PME_PM_THRESH_EXC_512 ] = { +- .pme_name = "PM_THRESH_EXC_512", +- .pme_code = 0x200e8, +- .pme_short_desc = "Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512", +- .pme_long_desc = "Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512", +-}, +-[ POWER8_PME_PM_THRESH_EXC_64 ] = { +- .pme_name = "PM_THRESH_EXC_64", +- .pme_code = 0x300e8, +- .pme_short_desc = "Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64", +- .pme_long_desc = "Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64", +-}, +-[ POWER8_PME_PM_THRESH_MET ] = { +- .pme_name = "PM_THRESH_MET", +- .pme_code = 0x100ec, +- .pme_short_desc = "threshold exceeded", +- .pme_long_desc = "Threshold exceeded", ++ .pme_short_desc = "One of threads in run_cycles", ++ .pme_long_desc = "Any thread in run_cycles (was one thread in run_cycles).", ++}, ++[ POWER8_PME_PM_BACK_BR_CMPL ] = { ++ .pme_name = "PM_BACK_BR_CMPL", ++ .pme_code = 0x2505e, ++ .pme_short_desc = "Branch instruction completed with a target address less than current instruction address", ++ .pme_long_desc = "Branch instruction completed with a target address less than current instruction address.", ++}, ++[ POWER8_PME_PM_BANK_CONFLICT ] = { ++ .pme_name = "PM_BANK_CONFLICT", ++ .pme_code = 0x4082, ++ .pme_short_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.", ++ .pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.", ++}, ++[ POWER8_PME_PM_BRU_FIN ] = { ++ .pme_name = "PM_BRU_FIN", ++ .pme_code = 0x10068, ++ .pme_short_desc = "Branch Instruction Finished", ++ .pme_long_desc = "Branch Instruction Finished .", + }, + [ POWER8_PME_PM_BR_2PATH ] = { + .pme_name = "PM_BR_2PATH", +- .pme_code = 0x40036, ++ .pme_code = 0x20036, + .pme_short_desc = "two path branch", + .pme_long_desc = "two path branch.", + }, ++[ POWER8_PME_PM_BR_BC_8 ] = { ++ .pme_name = "PM_BR_BC_8", ++ .pme_code = 0x5086, ++ .pme_short_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline", ++ .pme_long_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline", ++}, ++[ POWER8_PME_PM_BR_BC_8_CONV ] = { ++ .pme_name = "PM_BR_BC_8_CONV", ++ .pme_code = 0x5084, ++ .pme_short_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.", ++ .pme_long_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.", ++}, + [ POWER8_PME_PM_BR_CMPL ] = { + .pme_name = "PM_BR_CMPL", + .pme_code = 0x40060, + .pme_short_desc = "Branch Instruction completed", + .pme_long_desc = "Branch Instruction completed.", + }, ++[ POWER8_PME_PM_BR_MPRED_CCACHE ] = { ++ .pme_name = "PM_BR_MPRED_CCACHE", ++ .pme_code = 0x40ac, ++ .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction", ++}, ++[ POWER8_PME_PM_BR_MPRED_CMPL ] = { ++ .pme_name = "PM_BR_MPRED_CMPL", ++ .pme_code = 0x400f6, ++ .pme_short_desc = "Number of Branch Mispredicts", ++ .pme_long_desc = "Number of Branch Mispredicts.", ++}, ++[ POWER8_PME_PM_BR_MPRED_CR ] = { ++ .pme_name = "PM_BR_MPRED_CR", ++ .pme_code = 0x40b8, ++ .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).", ++ .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).", ++}, ++[ POWER8_PME_PM_BR_MPRED_LSTACK ] = { ++ .pme_name = "PM_BR_MPRED_LSTACK", ++ .pme_code = 0x40ae, ++ .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction", ++}, ++[ POWER8_PME_PM_BR_MPRED_TA ] = { ++ .pme_name = "PM_BR_MPRED_TA", ++ .pme_code = 0x40ba, ++ .pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.", ++ .pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.", ++}, + [ POWER8_PME_PM_BR_MRK_2PATH ] = { + .pme_name = "PM_BR_MRK_2PATH", +- .pme_code = 0x40138, ++ .pme_code = 0x10138, + .pme_short_desc = "marked two path branch", + .pme_long_desc = "marked two path branch.", + }, ++[ POWER8_PME_PM_BR_PRED_BR0 ] = { ++ .pme_name = "PM_BR_PRED_BR0", ++ .pme_code = 0x409c, ++ .pme_short_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target", ++ .pme_long_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target", ++}, ++[ POWER8_PME_PM_BR_PRED_BR1 ] = { ++ .pme_name = "PM_BR_PRED_BR1", ++ .pme_code = 0x409e, ++ .pme_short_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.", ++ .pme_long_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.", ++}, ++[ POWER8_PME_PM_BR_PRED_BR_CMPL ] = { ++ .pme_name = "PM_BR_PRED_BR_CMPL", ++ .pme_code = 0x489c, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1).", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_BR_PRED_CCACHE_BR0 ] = { ++ .pme_name = "PM_BR_PRED_CCACHE_BR0", ++ .pme_code = 0x40a4, ++ .pme_short_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction", ++}, ++[ POWER8_PME_PM_BR_PRED_CCACHE_BR1 ] = { ++ .pme_name = "PM_BR_PRED_CCACHE_BR1", ++ .pme_code = 0x40a6, ++ .pme_short_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction", ++}, ++[ POWER8_PME_PM_BR_PRED_CCACHE_CMPL ] = { ++ .pme_name = "PM_BR_PRED_CCACHE_CMPL", ++ .pme_code = 0x48a4, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type.", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_BR_PRED_CR_BR0 ] = { ++ .pme_name = "PM_BR_PRED_CR_BR0", ++ .pme_code = 0x40b0, ++ .pme_short_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", ++ .pme_long_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra", ++}, ++[ POWER8_PME_PM_BR_PRED_CR_BR1 ] = { ++ .pme_name = "PM_BR_PRED_CR_BR1", ++ .pme_code = 0x40b2, ++ .pme_short_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches", ++ .pme_long_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra", ++}, ++[ POWER8_PME_PM_BR_PRED_CR_CMPL ] = { ++ .pme_name = "PM_BR_PRED_CR_CMPL", ++ .pme_code = 0x48b0, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'.", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_BR_PRED_LSTACK_BR0 ] = { ++ .pme_name = "PM_BR_PRED_LSTACK_BR0", ++ .pme_code = 0x40a8, ++ .pme_short_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction", ++}, ++[ POWER8_PME_PM_BR_PRED_LSTACK_BR1 ] = { ++ .pme_name = "PM_BR_PRED_LSTACK_BR1", ++ .pme_code = 0x40aa, ++ .pme_short_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction", ++ .pme_long_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction", ++}, ++[ POWER8_PME_PM_BR_PRED_LSTACK_CMPL ] = { ++ .pme_name = "PM_BR_PRED_LSTACK_CMPL", ++ .pme_code = 0x48a8, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type).", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_BR_PRED_TA_BR0 ] = { ++ .pme_name = "PM_BR_PRED_TA_BR0", ++ .pme_code = 0x40b4, ++ .pme_short_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.", ++ .pme_long_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.", ++}, ++[ POWER8_PME_PM_BR_PRED_TA_BR1 ] = { ++ .pme_name = "PM_BR_PRED_TA_BR1", ++ .pme_code = 0x40b6, ++ .pme_short_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.", ++ .pme_long_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.", ++}, ++[ POWER8_PME_PM_BR_PRED_TA_CMPL ] = { ++ .pme_name = "PM_BR_PRED_TA_CMPL", ++ .pme_code = 0x48b4, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'.", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_BR_TAKEN_CMPL ] = { ++ .pme_name = "PM_BR_TAKEN_CMPL", ++ .pme_code = 0x200fa, ++ .pme_short_desc = "New event for Branch Taken", ++ .pme_long_desc = "Branch Taken.", ++}, ++[ POWER8_PME_PM_BR_UNCOND_BR0 ] = { ++ .pme_name = "PM_BR_UNCOND_BR0", ++ .pme_code = 0x40a0, ++ .pme_short_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", ++ .pme_long_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", ++}, ++[ POWER8_PME_PM_BR_UNCOND_BR1 ] = { ++ .pme_name = "PM_BR_UNCOND_BR1", ++ .pme_code = 0x40a2, ++ .pme_short_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", ++ .pme_long_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve.", ++}, ++[ POWER8_PME_PM_BR_UNCOND_CMPL ] = { ++ .pme_name = "PM_BR_UNCOND_CMPL", ++ .pme_code = 0x48a0, ++ .pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed.", ++ .pme_long_desc = "IFU", ++}, ++[ POWER8_PME_PM_CASTOUT_ISSUED ] = { ++ .pme_name = "PM_CASTOUT_ISSUED", ++ .pme_code = 0x3094, ++ .pme_short_desc = "Castouts issued", ++ .pme_long_desc = "Castouts issued", ++}, ++[ POWER8_PME_PM_CASTOUT_ISSUED_GPR ] = { ++ .pme_name = "PM_CASTOUT_ISSUED_GPR", ++ .pme_code = 0x3096, ++ .pme_short_desc = "Castouts issued GPR", ++ .pme_long_desc = "Castouts issued GPR", ++}, ++[ POWER8_PME_PM_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_CHIP_PUMP_CPRED", ++ .pme_code = 0x10050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d).", ++}, ++[ POWER8_PME_PM_CLB_HELD ] = { ++ .pme_name = "PM_CLB_HELD", ++ .pme_code = 0x2090, ++ .pme_short_desc = "CLB Hold: Any Reason", ++ .pme_long_desc = "CLB Hold: Any Reason", ++}, + [ POWER8_PME_PM_CMPLU_STALL ] = { + .pme_name = "PM_CMPLU_STALL", +- .pme_code = 0x1e054, ++ .pme_code = 0x4000a, + .pme_short_desc = "Completion stall", + .pme_long_desc = "Completion stall.", + }, +@@ -540,7 +1439,7 @@ static const pme_power_entry_t power8_pe[] = { + [ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = { + .pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", + .pme_code = 0x4c016, +- .pme_short_desc = "Completion stall due to cache miss due to L2 l3 conflict", ++ .pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", + .pme_long_desc = "Completion stall due to cache miss resolving in core's L2/L3 with a conflict.", + }, + [ POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = { +@@ -552,7 +1451,7 @@ static const pme_power_entry_t power8_pe[] = { + [ POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM ] = { + .pme_name = "PM_CMPLU_STALL_DMISS_LMEM", + .pme_code = 0x4c018, +- .pme_short_desc = "GCT empty by branch mispredict + IC miss", ++ .pme_short_desc = "Completion stall due to cache miss that resolves in local memory", + .pme_long_desc = "Completion stall due to cache miss resolving in core's Local Memory.", + }, + [ POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = { +@@ -615,6 +1514,12 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Completion stall due to mem ECC delay", + .pme_long_desc = "Completion stall due to mem ECC delay.", + }, ++[ POWER8_PME_PM_CMPLU_STALL_NO_NTF ] = { ++ .pme_name = "PM_CMPLU_STALL_NO_NTF", ++ .pme_code = 0x2e01c, ++ .pme_short_desc = "Completion stall due to nop", ++ .pme_long_desc = "Completion stall due to nop.", ++}, + [ POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH ] = { + .pme_name = "PM_CMPLU_STALL_NTCG_FLUSH", + .pme_code = 0x2e01e, +@@ -624,7 +1529,7 @@ static const pme_power_entry_t power8_pe[] = { + [ POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL ] = { + .pme_name = "PM_CMPLU_STALL_OTHER_CMPL", + .pme_code = 0x30006, +- .pme_short_desc = "Instructions core completed while this thread was stalled.", ++ .pme_short_desc = "Instructions core completed while this tread was stalled", + .pme_long_desc = "Instructions core completed while this thread was stalled.", + }, + [ POWER8_PME_PM_CMPLU_STALL_REJECT ] = { +@@ -660,7 +1565,7 @@ static const pme_power_entry_t power8_pe[] = { + [ POWER8_PME_PM_CMPLU_STALL_STORE ] = { + .pme_name = "PM_CMPLU_STALL_STORE", + .pme_code = 0x2c014, +- .pme_short_desc = "Completion stall by stores this includes store agent finishes in pipe LS0/LS1 and store data finishes in LS2/LS3", ++ .pme_short_desc = "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3", + .pme_long_desc = "Completion stall by stores.", + }, + [ POWER8_PME_PM_CMPLU_STALL_ST_FWD ] = { +@@ -693,47 +1598,563 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Completion stall due to VSU instruction", + .pme_long_desc = "Completion stall due to VSU instruction.", + }, ++[ POWER8_PME_PM_CO0_ALLOC ] = { ++ .pme_name = "PM_CO0_ALLOC", ++ .pme_code = 0x16083, ++ .pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_CO0_BUSY ] = { ++ .pme_name = "PM_CO0_BUSY", ++ .pme_code = 0x16082, ++ .pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++}, ++[ POWER8_PME_PM_CO_DISP_FAIL ] = { ++ .pme_name = "PM_CO_DISP_FAIL", ++ .pme_code = 0x517082, ++ .pme_short_desc = "CO dispatch failed due to all CO machines being busy", ++ .pme_long_desc = "CO dispatch failed due to all CO machines being busy", ++}, ++[ POWER8_PME_PM_CO_TM_SC_FOOTPRINT ] = { ++ .pme_name = "PM_CO_TM_SC_FOOTPRINT", ++ .pme_code = 0x527084, ++ .pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)", ++ .pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)", ++}, ++[ POWER8_PME_PM_CO_USAGE ] = { ++ .pme_name = "PM_CO_USAGE", ++ .pme_code = 0x3608a, ++ .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++ .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++}, ++[ POWER8_PME_PM_CRU_FIN ] = { ++ .pme_name = "PM_CRU_FIN", ++ .pme_code = 0x40066, ++ .pme_short_desc = "IFU Finished a (non-branch) instruction", ++ .pme_long_desc = "IFU Finished a (non-branch) instruction.", ++}, ++[ POWER8_PME_PM_CYC ] = { ++ .pme_name = "PM_CYC", ++ .pme_code = 0x1e, ++ .pme_short_desc = "Cycles", ++ .pme_long_desc = "Cycles .", ++}, ++[ POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_ALL_CHIP_PUMP_CPRED", ++ .pme_code = 0x61c050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_DL2L3_MOD", ++ .pme_code = 0x64c048, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_DATA_ALL_FROM_DL2L3_SHR", ++ .pme_code = 0x63c048, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_DL4 ] = { ++ .pme_name = "PM_DATA_ALL_FROM_DL4", ++ .pme_code = 0x63c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_DMEM ] = { ++ .pme_name = "PM_DATA_ALL_FROM_DMEM", ++ .pme_code = 0x64c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2 ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2", ++ .pme_code = 0x61c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L21_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L21_MOD", ++ .pme_code = 0x64c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L21_SHR ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L21_SHR", ++ .pme_code = 0x63c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2MISS_MOD", ++ .pme_code = 0x61c04e, ++ .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x63c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x64c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2_MEPF", ++ .pme_code = 0x62c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x61c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L3 ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L3", ++ .pme_code = 0x64c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L31_ECO_MOD", ++ .pme_code = 0x64c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L31_ECO_SHR", ++ .pme_code = 0x63c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L31_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L31_MOD", ++ .pme_code = 0x62c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L31_SHR ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L31_SHR", ++ .pme_code = 0x61c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L3MISS_MOD", ++ .pme_code = 0x64c04e, ++ .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x63c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L3_MEPF", ++ .pme_code = 0x62c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_DATA_ALL_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x61c044, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_LL4 ] = { ++ .pme_name = "PM_DATA_ALL_FROM_LL4", ++ .pme_code = 0x61c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_LMEM ] = { ++ .pme_name = "PM_DATA_ALL_FROM_LMEM", ++ .pme_code = 0x62c048, ++ .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_MEMORY ] = { ++ .pme_name = "PM_DATA_ALL_FROM_MEMORY", ++ .pme_code = 0x62c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_DATA_ALL_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x64c04a, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_DATA_ALL_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x61c048, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_DATA_ALL_FROM_RL2L3_MOD", ++ .pme_code = 0x62c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_DATA_ALL_FROM_RL2L3_SHR", ++ .pme_code = 0x61c04a, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_RL4 ] = { ++ .pme_name = "PM_DATA_ALL_FROM_RL4", ++ .pme_code = 0x62c04a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_FROM_RMEM ] = { ++ .pme_name = "PM_DATA_ALL_FROM_RMEM", ++ .pme_code = 0x63c04a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either demand loads or data prefetch", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1", ++}, ++[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_ALL_GRP_PUMP_CPRED", ++ .pme_code = 0x62c050, ++ .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED", ++ .pme_code = 0x62c052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x61c052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_ALL_PUMP_CPRED", ++ .pme_code = 0x61c054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for either demand loads or data prefetch", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_ALL_PUMP_MPRED", ++ .pme_code = 0x64c052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_ALL_SYS_PUMP_CPRED", ++ .pme_code = 0x63c050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load", ++}, ++[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED", ++ .pme_code = 0x63c052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for either demand loads or data prefetch", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x64c050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load", ++}, ++[ POWER8_PME_PM_DATA_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_CHIP_PUMP_CPRED", ++ .pme_code = 0x1c050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load.", ++}, ++[ POWER8_PME_PM_DATA_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_DATA_FROM_DL2L3_MOD", ++ .pme_code = 0x4c048, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_DATA_FROM_DL2L3_SHR", ++ .pme_code = 0x3c048, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_DL4 ] = { ++ .pme_name = "PM_DATA_FROM_DL4", ++ .pme_code = 0x3c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_DMEM ] = { ++ .pme_name = "PM_DATA_FROM_DMEM", ++ .pme_code = 0x4c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, + [ POWER8_PME_PM_DATA_FROM_L2 ] = { + .pme_name = "PM_DATA_FROM_L2", + .pme_code = 0x1c042, +- .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[16]", +- .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[20].", ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L21_MOD ] = { ++ .pme_name = "PM_DATA_FROM_L21_MOD", ++ .pme_code = 0x4c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L21_SHR ] = { ++ .pme_name = "PM_DATA_FROM_L21_SHR", ++ .pme_code = 0x3c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L2MISS ] = { ++ .pme_name = "PM_DATA_FROM_L2MISS", ++ .pme_code = 0x200fe, ++ .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", ++ .pme_long_desc = "Demand LD - L2 Miss (not L2 hit).", ++}, ++[ POWER8_PME_PM_DATA_FROM_L2MISS_MOD ] = { ++ .pme_name = "PM_DATA_FROM_L2MISS_MOD", ++ .pme_code = 0x1c04e, ++ .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x3c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x4c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L2_MEPF ] = { ++ .pme_name = "PM_DATA_FROM_L2_MEPF", ++ .pme_code = 0x2c040, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", + }, + [ POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = { + .pme_name = "PM_DATA_FROM_L2_NO_CONFLICT", + .pme_code = 0x1c040, +- .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16]", +- .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20] .", ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 .", + }, + [ POWER8_PME_PM_DATA_FROM_L3 ] = { + .pme_name = "PM_DATA_FROM_L3", + .pme_code = 0x4c042, + .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load", +- .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load.", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_DATA_FROM_L31_ECO_MOD", ++ .pme_code = 0x4c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_DATA_FROM_L31_ECO_SHR", ++ .pme_code = 0x3c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L31_MOD ] = { ++ .pme_name = "PM_DATA_FROM_L31_MOD", ++ .pme_code = 0x2c044, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L31_SHR ] = { ++ .pme_name = "PM_DATA_FROM_L31_SHR", ++ .pme_code = 0x1c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L3MISS ] = { ++ .pme_name = "PM_DATA_FROM_L3MISS", ++ .pme_code = 0x300fe, ++ .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", ++ .pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit).", + }, + [ POWER8_PME_PM_DATA_FROM_L3MISS_MOD ] = { + .pme_name = "PM_DATA_FROM_L3MISS_MOD", + .pme_code = 0x4c04e, +- .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load", +- .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load.", ++ .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x3c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_L3_MEPF ] = { ++ .pme_name = "PM_DATA_FROM_L3_MEPF", ++ .pme_code = 0x2c042, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", + }, + [ POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = { + .pme_name = "PM_DATA_FROM_L3_NO_CONFLICT", + .pme_code = 0x1c044, +- .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16]", +- .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20].", ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_LL4 ] = { ++ .pme_name = "PM_DATA_FROM_LL4", ++ .pme_code = 0x1c04c, ++ .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", + }, + [ POWER8_PME_PM_DATA_FROM_LMEM ] = { + .pme_name = "PM_DATA_FROM_LMEM", + .pme_code = 0x2c048, + .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load", +- .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load.", ++ .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_MEM ] = { ++ .pme_name = "PM_DATA_FROM_MEM", ++ .pme_code = 0x400fe, ++ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", ++ .pme_long_desc = "Data cache reload from memory (including L4).", + }, + [ POWER8_PME_PM_DATA_FROM_MEMORY ] = { + .pme_name = "PM_DATA_FROM_MEMORY", + .pme_code = 0x2c04c, + .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load", +- .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load.", ++ .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4c04a, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_DATA_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x1c048, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_DATA_FROM_RL2L3_MOD", ++ .pme_code = 0x2c046, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_DATA_FROM_RL2L3_SHR", ++ .pme_code = 0x1c04a, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_RL4 ] = { ++ .pme_name = "PM_DATA_FROM_RL4", ++ .pme_code = 0x2c04a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_FROM_RMEM ] = { ++ .pme_name = "PM_DATA_FROM_RMEM", ++ .pme_code = 0x3c04a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.", ++}, ++[ POWER8_PME_PM_DATA_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_GRP_PUMP_CPRED", ++ .pme_code = 0x2c050, ++ .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load.", ++}, ++[ POWER8_PME_PM_DATA_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_GRP_PUMP_MPRED", ++ .pme_code = 0x2c052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x1c052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load.", ++}, ++[ POWER8_PME_PM_DATA_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_PUMP_CPRED", ++ .pme_code = 0x1c054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for a demand load", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load.", ++}, ++[ POWER8_PME_PM_DATA_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_PUMP_MPRED", ++ .pme_code = 0x4c052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for a demand load", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load.", ++}, ++[ POWER8_PME_PM_DATA_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_DATA_SYS_PUMP_CPRED", ++ .pme_code = 0x3c050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load.", ++}, ++[ POWER8_PME_PM_DATA_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_DATA_SYS_PUMP_MPRED", ++ .pme_code = 0x3c052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x4c050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load.", ++}, ++[ POWER8_PME_PM_DATA_TABLEWALK_CYC ] = { ++ .pme_name = "PM_DATA_TABLEWALK_CYC", ++ .pme_code = 0x3001a, ++ .pme_short_desc = "Tablwalk Cycles (could be 1 or 2 active)", ++ .pme_long_desc = "Data Tablewalk Active.", ++}, ++[ POWER8_PME_PM_DC_COLLISIONS ] = { ++ .pme_name = "PM_DC_COLLISIONS", ++ .pme_code = 0xe0bc, ++ .pme_short_desc = "DATA Cache collisions", ++ .pme_long_desc = "DATA Cache collisions42", ++}, ++[ POWER8_PME_PM_DC_PREF_STREAM_ALLOC ] = { ++ .pme_name = "PM_DC_PREF_STREAM_ALLOC", ++ .pme_code = 0x1e050, ++ .pme_short_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1", ++ .pme_long_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1.", ++}, ++[ POWER8_PME_PM_DC_PREF_STREAM_CONF ] = { ++ .pme_name = "PM_DC_PREF_STREAM_CONF", ++ .pme_code = 0x2e050, ++ .pme_short_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down", ++ .pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down.", ++}, ++[ POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF ] = { ++ .pme_name = "PM_DC_PREF_STREAM_FUZZY_CONF", ++ .pme_code = 0x4e050, ++ .pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)", ++ .pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up).", + }, + [ POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF ] = { + .pme_name = "PM_DC_PREF_STREAM_STRIDED_CONF", +@@ -741,11 +2162,593 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.", + .pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software..", + }, ++[ POWER8_PME_PM_DERAT_MISS_16G ] = { ++ .pme_name = "PM_DERAT_MISS_16G", ++ .pme_code = 0x4c054, ++ .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G", ++ .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G.", ++}, ++[ POWER8_PME_PM_DERAT_MISS_16M ] = { ++ .pme_name = "PM_DERAT_MISS_16M", ++ .pme_code = 0x3c054, ++ .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M", ++ .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M.", ++}, ++[ POWER8_PME_PM_DERAT_MISS_4K ] = { ++ .pme_name = "PM_DERAT_MISS_4K", ++ .pme_code = 0x1c056, ++ .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K", ++ .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K.", ++}, ++[ POWER8_PME_PM_DERAT_MISS_64K ] = { ++ .pme_name = "PM_DERAT_MISS_64K", ++ .pme_code = 0x2c054, ++ .pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K", ++ .pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K.", ++}, ++[ POWER8_PME_PM_DFU ] = { ++ .pme_name = "PM_DFU", ++ .pme_code = 0xb0ba, ++ .pme_short_desc = "Finish DFU (all finish)", ++ .pme_long_desc = "Finish DFU (all finish)", ++}, ++[ POWER8_PME_PM_DFU_DCFFIX ] = { ++ .pme_name = "PM_DFU_DCFFIX", ++ .pme_code = 0xb0be, ++ .pme_short_desc = "Convert from fixed opcode finish (dcffix,dcffixq)", ++ .pme_long_desc = "Convert from fixed opcode finish (dcffix,dcffixq)", ++}, ++[ POWER8_PME_PM_DFU_DENBCD ] = { ++ .pme_name = "PM_DFU_DENBCD", ++ .pme_code = 0xb0bc, ++ .pme_short_desc = "BCD->DPD opcode finish (denbcd, denbcdq)", ++ .pme_long_desc = "BCD->DPD opcode finish (denbcd, denbcdq)", ++}, ++[ POWER8_PME_PM_DFU_MC ] = { ++ .pme_name = "PM_DFU_MC", ++ .pme_code = 0xb0b8, ++ .pme_short_desc = "Finish DFU multicycle", ++ .pme_long_desc = "Finish DFU multicycle", ++}, ++[ POWER8_PME_PM_DISP_CLB_HELD_BAL ] = { ++ .pme_name = "PM_DISP_CLB_HELD_BAL", ++ .pme_code = 0x2092, ++ .pme_short_desc = "Dispatch/CLB Hold: Balance", ++ .pme_long_desc = "Dispatch/CLB Hold: Balance", ++}, ++[ POWER8_PME_PM_DISP_CLB_HELD_RES ] = { ++ .pme_name = "PM_DISP_CLB_HELD_RES", ++ .pme_code = 0x2094, ++ .pme_short_desc = "Dispatch/CLB Hold: Resource", ++ .pme_long_desc = "Dispatch/CLB Hold: Resource", ++}, ++[ POWER8_PME_PM_DISP_CLB_HELD_SB ] = { ++ .pme_name = "PM_DISP_CLB_HELD_SB", ++ .pme_code = 0x20a8, ++ .pme_short_desc = "Dispatch/CLB Hold: Scoreboard", ++ .pme_long_desc = "Dispatch/CLB Hold: Scoreboard", ++}, ++[ POWER8_PME_PM_DISP_CLB_HELD_SYNC ] = { ++ .pme_name = "PM_DISP_CLB_HELD_SYNC", ++ .pme_code = 0x2098, ++ .pme_short_desc = "Dispatch/CLB Hold: Sync type instruction", ++ .pme_long_desc = "Dispatch/CLB Hold: Sync type instruction", ++}, ++[ POWER8_PME_PM_DISP_CLB_HELD_TLBIE ] = { ++ .pme_name = "PM_DISP_CLB_HELD_TLBIE", ++ .pme_code = 0x2096, ++ .pme_short_desc = "Dispatch Hold: Due to TLBIE", ++ .pme_long_desc = "Dispatch Hold: Due to TLBIE", ++}, ++[ POWER8_PME_PM_DISP_HELD ] = { ++ .pme_name = "PM_DISP_HELD", ++ .pme_code = 0x10006, ++ .pme_short_desc = "Dispatch Held", ++ .pme_long_desc = "Dispatch Held.", ++}, ++[ POWER8_PME_PM_DISP_HELD_IQ_FULL ] = { ++ .pme_name = "PM_DISP_HELD_IQ_FULL", ++ .pme_code = 0x20006, ++ .pme_short_desc = "Dispatch held due to Issue q full", ++ .pme_long_desc = "Dispatch held due to Issue q full.", ++}, ++[ POWER8_PME_PM_DISP_HELD_MAP_FULL ] = { ++ .pme_name = "PM_DISP_HELD_MAP_FULL", ++ .pme_code = 0x1002a, ++ .pme_short_desc = "Dispatch for this thread was held because the Mappers were full", ++ .pme_long_desc = "Dispatch held due to Mapper full.", ++}, ++[ POWER8_PME_PM_DISP_HELD_SRQ_FULL ] = { ++ .pme_name = "PM_DISP_HELD_SRQ_FULL", ++ .pme_code = 0x30018, ++ .pme_short_desc = "Dispatch held due SRQ no room", ++ .pme_long_desc = "Dispatch held due SRQ no room.", ++}, ++[ POWER8_PME_PM_DISP_HELD_SYNC_HOLD ] = { ++ .pme_name = "PM_DISP_HELD_SYNC_HOLD", ++ .pme_code = 0x4003c, ++ .pme_short_desc = "Dispatch held due to SYNC hold", ++ .pme_long_desc = "Dispatch held due to SYNC hold.", ++}, ++[ POWER8_PME_PM_DISP_HOLD_GCT_FULL ] = { ++ .pme_name = "PM_DISP_HOLD_GCT_FULL", ++ .pme_code = 0x30a6, ++ .pme_short_desc = "Dispatch Hold Due to no space in the GCT", ++ .pme_long_desc = "Dispatch Hold Due to no space in the GCT", ++}, ++[ POWER8_PME_PM_DISP_WT ] = { ++ .pme_name = "PM_DISP_WT", ++ .pme_code = 0x30008, ++ .pme_short_desc = "Dispatched Starved", ++ .pme_long_desc = "Dispatched Starved (not held, nothing to dispatch).", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_DPTEG_FROM_DL2L3_MOD", ++ .pme_code = 0x4e048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_DPTEG_FROM_DL2L3_SHR", ++ .pme_code = 0x3e048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_DL4 ] = { ++ .pme_name = "PM_DPTEG_FROM_DL4", ++ .pme_code = 0x3e04c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_DMEM ] = { ++ .pme_name = "PM_DPTEG_FROM_DMEM", ++ .pme_code = 0x4e04c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2 ] = { ++ .pme_name = "PM_DPTEG_FROM_L2", ++ .pme_code = 0x1e042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L21_MOD ] = { ++ .pme_name = "PM_DPTEG_FROM_L21_MOD", ++ .pme_code = 0x4e046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L21_SHR ] = { ++ .pme_name = "PM_DPTEG_FROM_L21_SHR", ++ .pme_code = 0x3e046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2MISS ] = { ++ .pme_name = "PM_DPTEG_FROM_L2MISS", ++ .pme_code = 0x1e04e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x3e040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x4e040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2_MEPF ] = { ++ .pme_name = "PM_DPTEG_FROM_L2_MEPF", ++ .pme_code = 0x2e040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x1e040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L3 ] = { ++ .pme_name = "PM_DPTEG_FROM_L3", ++ .pme_code = 0x4e042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_DPTEG_FROM_L31_ECO_MOD", ++ .pme_code = 0x4e044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_DPTEG_FROM_L31_ECO_SHR", ++ .pme_code = 0x3e044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L31_MOD ] = { ++ .pme_name = "PM_DPTEG_FROM_L31_MOD", ++ .pme_code = 0x2e044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L31_SHR ] = { ++ .pme_name = "PM_DPTEG_FROM_L31_SHR", ++ .pme_code = 0x1e046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L3MISS ] = { ++ .pme_name = "PM_DPTEG_FROM_L3MISS", ++ .pme_code = 0x4e04e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x3e042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L3_MEPF ] = { ++ .pme_name = "PM_DPTEG_FROM_L3_MEPF", ++ .pme_code = 0x2e042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x1e044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_LL4 ] = { ++ .pme_name = "PM_DPTEG_FROM_LL4", ++ .pme_code = 0x1e04c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_LMEM ] = { ++ .pme_name = "PM_DPTEG_FROM_LMEM", ++ .pme_code = 0x2e048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_MEMORY ] = { ++ .pme_name = "PM_DPTEG_FROM_MEMORY", ++ .pme_code = 0x2e04c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4e04a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x1e048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_DPTEG_FROM_RL2L3_MOD", ++ .pme_code = 0x2e046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_DPTEG_FROM_RL2L3_SHR", ++ .pme_code = 0x1e04a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_RL4 ] = { ++ .pme_name = "PM_DPTEG_FROM_RL4", ++ .pme_code = 0x2e04a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request.", ++}, ++[ POWER8_PME_PM_DPTEG_FROM_RMEM ] = { ++ .pme_name = "PM_DPTEG_FROM_RMEM", ++ .pme_code = 0x3e04a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request.", ++}, ++[ POWER8_PME_PM_DSLB_MISS ] = { ++ .pme_name = "PM_DSLB_MISS", ++ .pme_code = 0xd094, ++ .pme_short_desc = "Data SLB Miss - Total of all segment sizes", ++ .pme_long_desc = "Data SLB Miss - Total of all segment sizesData SLB misses", ++}, ++[ POWER8_PME_PM_DTLB_MISS ] = { ++ .pme_name = "PM_DTLB_MISS", ++ .pme_code = 0x300fc, ++ .pme_short_desc = "Data PTEG reload", ++ .pme_long_desc = "Data PTEG Reloaded (DTLB Miss).", ++}, ++[ POWER8_PME_PM_DTLB_MISS_16G ] = { ++ .pme_name = "PM_DTLB_MISS_16G", ++ .pme_code = 0x1c058, ++ .pme_short_desc = "Data TLB Miss page size 16G", ++ .pme_long_desc = "Data TLB Miss page size 16G.", ++}, ++[ POWER8_PME_PM_DTLB_MISS_16M ] = { ++ .pme_name = "PM_DTLB_MISS_16M", ++ .pme_code = 0x4c056, ++ .pme_short_desc = "Data TLB Miss page size 16M", ++ .pme_long_desc = "Data TLB Miss page size 16M.", ++}, ++[ POWER8_PME_PM_DTLB_MISS_4K ] = { ++ .pme_name = "PM_DTLB_MISS_4K", ++ .pme_code = 0x2c056, ++ .pme_short_desc = "Data TLB Miss page size 4k", ++ .pme_long_desc = "Data TLB Miss page size 4k.", ++}, ++[ POWER8_PME_PM_DTLB_MISS_64K ] = { ++ .pme_name = "PM_DTLB_MISS_64K", ++ .pme_code = 0x3c056, ++ .pme_short_desc = "Data TLB Miss page size 64K", ++ .pme_long_desc = "Data TLB Miss page size 64K.", ++}, ++[ POWER8_PME_PM_EAT_FORCE_MISPRED ] = { ++ .pme_name = "PM_EAT_FORCE_MISPRED", ++ .pme_code = 0x50a8, ++ .pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue", ++ .pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is", ++}, ++[ POWER8_PME_PM_EAT_FULL_CYC ] = { ++ .pme_name = "PM_EAT_FULL_CYC", ++ .pme_code = 0x4084, ++ .pme_short_desc = "Cycles No room in EAT", ++ .pme_long_desc = "Cycles No room in EATSet on bank conflict and case where no ibuffers available.", ++}, ++[ POWER8_PME_PM_EE_OFF_EXT_INT ] = { ++ .pme_name = "PM_EE_OFF_EXT_INT", ++ .pme_code = 0x2080, ++ .pme_short_desc = "Ee off and external interrupt", ++ .pme_long_desc = "Ee off and external interrupt", ++}, ++[ POWER8_PME_PM_EXT_INT ] = { ++ .pme_name = "PM_EXT_INT", ++ .pme_code = 0x200f8, ++ .pme_short_desc = "external interrupt", ++ .pme_long_desc = "external interrupt.", ++}, ++[ POWER8_PME_PM_FAV_TBEGIN ] = { ++ .pme_name = "PM_FAV_TBEGIN", ++ .pme_code = 0x20b4, ++ .pme_short_desc = "Dispatch time Favored tbegin", ++ .pme_long_desc = "Dispatch time Favored tbegin", ++}, ++[ POWER8_PME_PM_FLOP ] = { ++ .pme_name = "PM_FLOP", ++ .pme_code = 0x100f4, ++ .pme_short_desc = "Floating Point Operation Finished", ++ .pme_long_desc = "Floating Point Operations Finished.", ++}, ++[ POWER8_PME_PM_FLOP_SUM_SCALAR ] = { ++ .pme_name = "PM_FLOP_SUM_SCALAR", ++ .pme_code = 0xa0ae, ++ .pme_short_desc = "flops summary scalar instructions", ++ .pme_long_desc = "flops summary scalar instructions", ++}, ++[ POWER8_PME_PM_FLOP_SUM_VEC ] = { ++ .pme_name = "PM_FLOP_SUM_VEC", ++ .pme_code = 0xa0ac, ++ .pme_short_desc = "flops summary vector instructions", ++ .pme_long_desc = "flops summary vector instructions", ++}, ++[ POWER8_PME_PM_FLUSH ] = { ++ .pme_name = "PM_FLUSH", ++ .pme_code = 0x400f8, ++ .pme_short_desc = "Flush (any type)", ++ .pme_long_desc = "Flush (any type).", ++}, ++[ POWER8_PME_PM_FLUSH_BR_MPRED ] = { ++ .pme_name = "PM_FLUSH_BR_MPRED", ++ .pme_code = 0x2084, ++ .pme_short_desc = "Flush caused by branch mispredict", ++ .pme_long_desc = "Flush caused by branch mispredict", ++}, ++[ POWER8_PME_PM_FLUSH_COMPLETION ] = { ++ .pme_name = "PM_FLUSH_COMPLETION", ++ .pme_code = 0x30012, ++ .pme_short_desc = "Completion Flush", ++ .pme_long_desc = "Completion Flush.", ++}, ++[ POWER8_PME_PM_FLUSH_DISP ] = { ++ .pme_name = "PM_FLUSH_DISP", ++ .pme_code = 0x2082, ++ .pme_short_desc = "Dispatch flush", ++ .pme_long_desc = "Dispatch flush", ++}, ++[ POWER8_PME_PM_FLUSH_DISP_SB ] = { ++ .pme_name = "PM_FLUSH_DISP_SB", ++ .pme_code = 0x208c, ++ .pme_short_desc = "Dispatch Flush: Scoreboard", ++ .pme_long_desc = "Dispatch Flush: Scoreboard", ++}, ++[ POWER8_PME_PM_FLUSH_DISP_SYNC ] = { ++ .pme_name = "PM_FLUSH_DISP_SYNC", ++ .pme_code = 0x2088, ++ .pme_short_desc = "Dispatch Flush: Sync", ++ .pme_long_desc = "Dispatch Flush: Sync", ++}, ++[ POWER8_PME_PM_FLUSH_DISP_TLBIE ] = { ++ .pme_name = "PM_FLUSH_DISP_TLBIE", ++ .pme_code = 0x208a, ++ .pme_short_desc = "Dispatch Flush: TLBIE", ++ .pme_long_desc = "Dispatch Flush: TLBIE", ++}, ++[ POWER8_PME_PM_FLUSH_LSU ] = { ++ .pme_name = "PM_FLUSH_LSU", ++ .pme_code = 0x208e, ++ .pme_short_desc = "Flush initiated by LSU", ++ .pme_long_desc = "Flush initiated by LSU", ++}, ++[ POWER8_PME_PM_FLUSH_PARTIAL ] = { ++ .pme_name = "PM_FLUSH_PARTIAL", ++ .pme_code = 0x2086, ++ .pme_short_desc = "Partial flush", ++ .pme_long_desc = "Partial flush", ++}, ++[ POWER8_PME_PM_FPU0_FCONV ] = { ++ .pme_name = "PM_FPU0_FCONV", ++ .pme_code = 0xa0b0, ++ .pme_short_desc = "Convert instruction executed", ++ .pme_long_desc = "Convert instruction executed", ++}, ++[ POWER8_PME_PM_FPU0_FEST ] = { ++ .pme_name = "PM_FPU0_FEST", ++ .pme_code = 0xa0b8, ++ .pme_short_desc = "Estimate instruction executed", ++ .pme_long_desc = "Estimate instruction executed", ++}, ++[ POWER8_PME_PM_FPU0_FRSP ] = { ++ .pme_name = "PM_FPU0_FRSP", ++ .pme_code = 0xa0b4, ++ .pme_short_desc = "Round to single precision instruction executed", ++ .pme_long_desc = "Round to single precision instruction executed", ++}, ++[ POWER8_PME_PM_FPU1_FCONV ] = { ++ .pme_name = "PM_FPU1_FCONV", ++ .pme_code = 0xa0b2, ++ .pme_short_desc = "Convert instruction executed", ++ .pme_long_desc = "Convert instruction executed", ++}, ++[ POWER8_PME_PM_FPU1_FEST ] = { ++ .pme_name = "PM_FPU1_FEST", ++ .pme_code = 0xa0ba, ++ .pme_short_desc = "Estimate instruction executed", ++ .pme_long_desc = "Estimate instruction executed", ++}, ++[ POWER8_PME_PM_FPU1_FRSP ] = { ++ .pme_name = "PM_FPU1_FRSP", ++ .pme_code = 0xa0b6, ++ .pme_short_desc = "Round to single precision instruction executed", ++ .pme_long_desc = "Round to single precision instruction executed", ++}, ++[ POWER8_PME_PM_FREQ_DOWN ] = { ++ .pme_name = "PM_FREQ_DOWN", ++ .pme_code = 0x3000c, ++ .pme_short_desc = "Power Management: Below Threshold B", ++ .pme_long_desc = "Frequency is being slewed down due to Power Management.", ++}, ++[ POWER8_PME_PM_FREQ_UP ] = { ++ .pme_name = "PM_FREQ_UP", ++ .pme_code = 0x4000c, ++ .pme_short_desc = "Power Management: Above Threshold A", ++ .pme_long_desc = "Frequency is being slewed up due to Power Management.", ++}, ++[ POWER8_PME_PM_FUSION_TOC_GRP0_1 ] = { ++ .pme_name = "PM_FUSION_TOC_GRP0_1", ++ .pme_code = 0x50b0, ++ .pme_short_desc = "One pair of instructions fused with TOC in Group0", ++ .pme_long_desc = "One pair of instructions fused with TOC in Group0", ++}, ++[ POWER8_PME_PM_FUSION_TOC_GRP0_2 ] = { ++ .pme_name = "PM_FUSION_TOC_GRP0_2", ++ .pme_code = 0x50ae, ++ .pme_short_desc = "Two pairs of instructions fused with TOCin Group0", ++ .pme_long_desc = "Two pairs of instructions fused with TOCin Group0", ++}, ++[ POWER8_PME_PM_FUSION_TOC_GRP0_3 ] = { ++ .pme_name = "PM_FUSION_TOC_GRP0_3", ++ .pme_code = 0x50ac, ++ .pme_short_desc = "Three pairs of instructions fused with TOC in Group0", ++ .pme_long_desc = "Three pairs of instructions fused with TOC in Group0", ++}, ++[ POWER8_PME_PM_FUSION_TOC_GRP1_1 ] = { ++ .pme_name = "PM_FUSION_TOC_GRP1_1", ++ .pme_code = 0x50b2, ++ .pme_short_desc = "One pair of instructions fused with TOX in Group1", ++ .pme_long_desc = "One pair of instructions fused with TOX in Group1", ++}, ++[ POWER8_PME_PM_FUSION_VSX_GRP0_1 ] = { ++ .pme_name = "PM_FUSION_VSX_GRP0_1", ++ .pme_code = 0x50b8, ++ .pme_short_desc = "One pair of instructions fused with VSX in Group0", ++ .pme_long_desc = "One pair of instructions fused with VSX in Group0", ++}, ++[ POWER8_PME_PM_FUSION_VSX_GRP0_2 ] = { ++ .pme_name = "PM_FUSION_VSX_GRP0_2", ++ .pme_code = 0x50b6, ++ .pme_short_desc = "Two pairs of instructions fused with VSX in Group0", ++ .pme_long_desc = "Two pairs of instructions fused with VSX in Group0", ++}, ++[ POWER8_PME_PM_FUSION_VSX_GRP0_3 ] = { ++ .pme_name = "PM_FUSION_VSX_GRP0_3", ++ .pme_code = 0x50b4, ++ .pme_short_desc = "Three pairs of instructions fused with VSX in Group0", ++ .pme_long_desc = "Three pairs of instructions fused with VSX in Group0", ++}, ++[ POWER8_PME_PM_FUSION_VSX_GRP1_1 ] = { ++ .pme_name = "PM_FUSION_VSX_GRP1_1", ++ .pme_code = 0x50ba, ++ .pme_short_desc = "One pair of instructions fused with VSX in Group1", ++ .pme_long_desc = "One pair of instructions fused with VSX in Group1", ++}, ++[ POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { ++ .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", ++ .pme_code = 0x3000e, ++ .pme_short_desc = "fxu0 busy and fxu1 idle", ++ .pme_long_desc = "fxu0 busy and fxu1 idle.", ++}, ++[ POWER8_PME_PM_FXU0_FIN ] = { ++ .pme_name = "PM_FXU0_FIN", ++ .pme_code = 0x10004, ++ .pme_short_desc = "The fixed point unit Unit 0 finished an instruction. Instructions that finish may not necessary complete.", ++ .pme_long_desc = "FXU0 Finished.", ++}, ++[ POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { ++ .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", ++ .pme_code = 0x4000e, ++ .pme_short_desc = "fxu0 idle and fxu1 busy.", ++ .pme_long_desc = "fxu0 idle and fxu1 busy. .", ++}, ++[ POWER8_PME_PM_FXU1_FIN ] = { ++ .pme_name = "PM_FXU1_FIN", ++ .pme_code = 0x40004, ++ .pme_short_desc = "FXU1 Finished", ++ .pme_long_desc = "FXU1 Finished.", ++}, ++[ POWER8_PME_PM_FXU_BUSY ] = { ++ .pme_name = "PM_FXU_BUSY", ++ .pme_code = 0x2000e, ++ .pme_short_desc = "fxu0 busy and fxu1 busy.", ++ .pme_long_desc = "fxu0 busy and fxu1 busy..", ++}, ++[ POWER8_PME_PM_FXU_IDLE ] = { ++ .pme_name = "PM_FXU_IDLE", ++ .pme_code = 0x1000e, ++ .pme_short_desc = "fxu0 idle and fxu1 idle", ++ .pme_long_desc = "fxu0 idle and fxu1 idle.", ++}, ++[ POWER8_PME_PM_GCT_EMPTY_CYC ] = { ++ .pme_name = "PM_GCT_EMPTY_CYC", ++ .pme_code = 0x20008, ++ .pme_short_desc = "No itags assigned either thread (GCT Empty)", ++ .pme_long_desc = "No itags assigned either thread (GCT Empty).", ++}, ++[ POWER8_PME_PM_GCT_MERGE ] = { ++ .pme_name = "PM_GCT_MERGE", ++ .pme_code = 0x30a4, ++ .pme_short_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread", ++ .pme_long_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread", ++}, + [ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED ] = { + .pme_name = "PM_GCT_NOSLOT_BR_MPRED", + .pme_code = 0x4d01e, +- .pme_short_desc = "Gct empty fo this thread due to branch misprediction", +- .pme_long_desc = "Gct empty for this thread due to branch misprediction.", ++ .pme_short_desc = "Gct empty for this thread due to branch mispred", ++ .pme_long_desc = "Gct empty for this thread due to branch mispred.", + }, + [ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS ] = { + .pme_name = "PM_GCT_NOSLOT_BR_MPRED_ICMISS", +@@ -753,12 +2756,24 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Gct empty for this thread due to Icache Miss and branch mispred", + .pme_long_desc = "Gct empty for this thread due to Icache Miss and branch mispred.", + }, ++[ POWER8_PME_PM_GCT_NOSLOT_CYC ] = { ++ .pme_name = "PM_GCT_NOSLOT_CYC", ++ .pme_code = 0x100f8, ++ .pme_short_desc = "No itags assigned", ++ .pme_long_desc = "Pipeline empty (No itags assigned , no GCT slots used).", ++}, + [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ ] = { + .pme_name = "PM_GCT_NOSLOT_DISP_HELD_ISSQ", + .pme_code = 0x2d01e, + .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full", + .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full.", + }, ++[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP ] = { ++ .pme_name = "PM_GCT_NOSLOT_DISP_HELD_MAP", ++ .pme_code = 0x4d01c, ++ .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full", ++ .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full.", ++}, + [ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER ] = { + .pme_name = "PM_GCT_NOSLOT_DISP_HELD_OTHER", + .pme_code = 0x2e010, +@@ -783,36 +2798,1818 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Gct empty for this thread due to Icache Miss", + .pme_long_desc = "Gct empty for this thread due to Icache Miss.", + }, ++[ POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_11_14_ENTRIES", ++ .pme_code = 0x20a2, ++ .pme_short_desc = "GCT Utilization 11-14 entries", ++ .pme_long_desc = "GCT Utilization 11-14 entries", ++}, ++[ POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_15_17_ENTRIES", ++ .pme_code = 0x20a4, ++ .pme_short_desc = "GCT Utilization 15-17 entries", ++ .pme_long_desc = "GCT Utilization 15-17 entries", ++}, ++[ POWER8_PME_PM_GCT_UTIL_18_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_18_ENTRIES", ++ .pme_code = 0x20a6, ++ .pme_short_desc = "GCT Utilization 18+ entries", ++ .pme_long_desc = "GCT Utilization 18+ entries", ++}, ++[ POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_1_2_ENTRIES", ++ .pme_code = 0x209c, ++ .pme_short_desc = "GCT Utilization 1-2 entries", ++ .pme_long_desc = "GCT Utilization 1-2 entries", ++}, ++[ POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_3_6_ENTRIES", ++ .pme_code = 0x209e, ++ .pme_short_desc = "GCT Utilization 3-6 entries", ++ .pme_long_desc = "GCT Utilization 3-6 entries", ++}, ++[ POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES ] = { ++ .pme_name = "PM_GCT_UTIL_7_10_ENTRIES", ++ .pme_code = 0x20a0, ++ .pme_short_desc = "GCT Utilization 7-10 entries", ++ .pme_long_desc = "GCT Utilization 7-10 entries", ++}, ++[ POWER8_PME_PM_GRP_BR_MPRED_NONSPEC ] = { ++ .pme_name = "PM_GRP_BR_MPRED_NONSPEC", ++ .pme_code = 0x1000a, ++ .pme_short_desc = "Group experienced non-speculative branch redirect", ++ .pme_long_desc = "Group experienced Non-speculative br mispredicct.", ++}, ++[ POWER8_PME_PM_GRP_CMPL ] = { ++ .pme_name = "PM_GRP_CMPL", ++ .pme_code = 0x30004, ++ .pme_short_desc = "group completed", ++ .pme_long_desc = "group completed.", ++}, + [ POWER8_PME_PM_GRP_DISP ] = { + .pme_name = "PM_GRP_DISP", + .pme_code = 0x3000a, + .pme_short_desc = "group dispatch", + .pme_long_desc = "dispatch_success (Group Dispatched).", + }, ++[ POWER8_PME_PM_GRP_IC_MISS_NONSPEC ] = { ++ .pme_name = "PM_GRP_IC_MISS_NONSPEC", ++ .pme_code = 0x1000c, ++ .pme_short_desc = "Group experienced non-speculative I cache miss", ++ .pme_long_desc = "Group experi enced Non-specu lative I cache miss.", ++}, + [ POWER8_PME_PM_GRP_MRK ] = { + .pme_name = "PM_GRP_MRK", + .pme_code = 0x10130, + .pme_short_desc = "Instruction Marked", + .pme_long_desc = "Instruction marked in idu.", + }, ++[ POWER8_PME_PM_GRP_NON_FULL_GROUP ] = { ++ .pme_name = "PM_GRP_NON_FULL_GROUP", ++ .pme_code = 0x509c, ++ .pme_short_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches", ++ .pme_long_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches", ++}, ++[ POWER8_PME_PM_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_GRP_PUMP_CPRED", ++ .pme_code = 0x20050, ++ .pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_GRP_PUMP_MPRED", ++ .pme_code = 0x20052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x10052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_GRP_TERM_2ND_BRANCH ] = { ++ .pme_name = "PM_GRP_TERM_2ND_BRANCH", ++ .pme_code = 0x50a4, ++ .pme_short_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group", ++ .pme_long_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group", ++}, ++[ POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR ] = { ++ .pme_name = "PM_GRP_TERM_FPU_AFTER_BR", ++ .pme_code = 0x50a6, ++ .pme_short_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes", ++ .pme_long_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes", ++}, ++[ POWER8_PME_PM_GRP_TERM_NOINST ] = { ++ .pme_name = "PM_GRP_TERM_NOINST", ++ .pme_code = 0x509e, ++ .pme_short_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).", ++ .pme_long_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).", ++}, ++[ POWER8_PME_PM_GRP_TERM_OTHER ] = { ++ .pme_name = "PM_GRP_TERM_OTHER", ++ .pme_code = 0x50a0, ++ .pme_short_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.", ++ .pme_long_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.", ++}, ++[ POWER8_PME_PM_GRP_TERM_SLOT_LIMIT ] = { ++ .pme_name = "PM_GRP_TERM_SLOT_LIMIT", ++ .pme_code = 0x50a2, ++ .pme_short_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination", ++ .pme_long_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination", ++}, + [ POWER8_PME_PM_HV_CYC ] = { + .pme_name = "PM_HV_CYC", + .pme_code = 0x2000a, +- .pme_short_desc = "cycles in hypervisor mode", ++ .pme_short_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration", + .pme_long_desc = "cycles in hypervisor mode .", + }, ++[ POWER8_PME_PM_IBUF_FULL_CYC ] = { ++ .pme_name = "PM_IBUF_FULL_CYC", ++ .pme_code = 0x4086, ++ .pme_short_desc = "Cycles No room in ibuff", ++ .pme_long_desc = "Cycles No room in ibufffully qualified tranfer (if5 valid).", ++}, ++[ POWER8_PME_PM_IC_DEMAND_CYC ] = { ++ .pme_name = "PM_IC_DEMAND_CYC", ++ .pme_code = 0x10018, ++ .pme_short_desc = "Cycles when a demand ifetch was pending", ++ .pme_long_desc = "Demand ifetch pending.", ++}, ++[ POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { ++ .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", ++ .pme_code = 0x4098, ++ .pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", ++ .pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)", ++}, ++[ POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { ++ .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", ++ .pme_code = 0x409a, ++ .pme_short_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", ++ .pme_long_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)", ++}, ++[ POWER8_PME_PM_IC_DEMAND_REQ ] = { ++ .pme_name = "PM_IC_DEMAND_REQ", ++ .pme_code = 0x4088, ++ .pme_short_desc = "Demand Instruction fetch request", ++ .pme_long_desc = "Demand Instruction fetch request", ++}, ++[ POWER8_PME_PM_IC_INVALIDATE ] = { ++ .pme_name = "PM_IC_INVALIDATE", ++ .pme_code = 0x508a, ++ .pme_short_desc = "Ic line invalidated", ++ .pme_long_desc = "Ic line invalidated", ++}, ++[ POWER8_PME_PM_IC_PREF_CANCEL_HIT ] = { ++ .pme_name = "PM_IC_PREF_CANCEL_HIT", ++ .pme_code = 0x4092, ++ .pme_short_desc = "Prefetch Canceled due to icache hit", ++ .pme_long_desc = "Prefetch Canceled due to icache hit", ++}, ++[ POWER8_PME_PM_IC_PREF_CANCEL_L2 ] = { ++ .pme_name = "PM_IC_PREF_CANCEL_L2", ++ .pme_code = 0x4094, ++ .pme_short_desc = "L2 Squashed request", ++ .pme_long_desc = "L2 Squashed request", ++}, ++[ POWER8_PME_PM_IC_PREF_CANCEL_PAGE ] = { ++ .pme_name = "PM_IC_PREF_CANCEL_PAGE", ++ .pme_code = 0x4090, ++ .pme_short_desc = "Prefetch Canceled due to page boundary", ++ .pme_long_desc = "Prefetch Canceled due to page boundary", ++}, ++[ POWER8_PME_PM_IC_PREF_REQ ] = { ++ .pme_name = "PM_IC_PREF_REQ", ++ .pme_code = 0x408a, ++ .pme_short_desc = "Instruction prefetch requests", ++ .pme_long_desc = "Instruction prefetch requests", ++}, ++[ POWER8_PME_PM_IC_PREF_WRITE ] = { ++ .pme_name = "PM_IC_PREF_WRITE", ++ .pme_code = 0x408e, ++ .pme_short_desc = "Instruction prefetch written into IL1", ++ .pme_long_desc = "Instruction prefetch written into IL1", ++}, ++[ POWER8_PME_PM_IC_RELOAD_PRIVATE ] = { ++ .pme_name = "PM_IC_RELOAD_PRIVATE", ++ .pme_code = 0x4096, ++ .pme_short_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat", ++ .pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv", ++}, ++[ POWER8_PME_PM_IERAT_RELOAD ] = { ++ .pme_name = "PM_IERAT_RELOAD", ++ .pme_code = 0x100f6, ++ .pme_short_desc = "Number of I-ERAT reloads", ++ .pme_long_desc = "IERAT Reloaded (Miss).", ++}, ++[ POWER8_PME_PM_IERAT_RELOAD_16M ] = { ++ .pme_name = "PM_IERAT_RELOAD_16M", ++ .pme_code = 0x4006a, ++ .pme_short_desc = "IERAT Reloaded (Miss) for a 16M page", ++ .pme_long_desc = "IERAT Reloaded (Miss) for a 16M page.", ++}, ++[ POWER8_PME_PM_IERAT_RELOAD_4K ] = { ++ .pme_name = "PM_IERAT_RELOAD_4K", ++ .pme_code = 0x20064, ++ .pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)", ++ .pme_long_desc = "IERAT Reloaded (Miss) for a 4k page.", ++}, ++[ POWER8_PME_PM_IERAT_RELOAD_64K ] = { ++ .pme_name = "PM_IERAT_RELOAD_64K", ++ .pme_code = 0x3006a, ++ .pme_short_desc = "IERAT Reloaded (Miss) for a 64k page", ++ .pme_long_desc = "IERAT Reloaded (Miss) for a 64k page.", ++}, ++[ POWER8_PME_PM_IFETCH_THROTTLE ] = { ++ .pme_name = "PM_IFETCH_THROTTLE", ++ .pme_code = 0x3405e, ++ .pme_short_desc = "Cycles in which Instruction fetch throttle was active", ++ .pme_long_desc = "Cycles instruction fecth was throttled in IFU.", ++}, ++[ POWER8_PME_PM_IFU_L2_TOUCH ] = { ++ .pme_name = "PM_IFU_L2_TOUCH", ++ .pme_code = 0x5088, ++ .pme_short_desc = "L2 touch to update MRU on a line", ++ .pme_long_desc = "L2 touch to update MRU on a line", ++}, ++[ POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_ALL_CHIP_PUMP_CPRED", ++ .pme_code = 0x514050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_DL2L3_MOD", ++ .pme_code = 0x544048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_INST_ALL_FROM_DL2L3_SHR", ++ .pme_code = 0x534048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_DL4 ] = { ++ .pme_name = "PM_INST_ALL_FROM_DL4", ++ .pme_code = 0x53404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_DMEM ] = { ++ .pme_name = "PM_INST_ALL_FROM_DMEM", ++ .pme_code = 0x54404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2 ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2", ++ .pme_code = 0x514042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L21_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_L21_MOD", ++ .pme_code = 0x544046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L21_SHR ] = { ++ .pme_name = "PM_INST_ALL_FROM_L21_SHR", ++ .pme_code = 0x534046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2MISS ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2MISS", ++ .pme_code = 0x51404e, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x534040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x544040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2_MEPF ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2_MEPF", ++ .pme_code = 0x524040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_INST_ALL_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x514040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L3 ] = { ++ .pme_name = "PM_INST_ALL_FROM_L3", ++ .pme_code = 0x544042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_L31_ECO_MOD", ++ .pme_code = 0x544044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_INST_ALL_FROM_L31_ECO_SHR", ++ .pme_code = 0x534044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L31_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_L31_MOD", ++ .pme_code = 0x524044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L31_SHR ] = { ++ .pme_name = "PM_INST_ALL_FROM_L31_SHR", ++ .pme_code = 0x514046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_L3MISS_MOD", ++ .pme_code = 0x54404e, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_INST_ALL_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x534042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L3_MEPF ] = { ++ .pme_name = "PM_INST_ALL_FROM_L3_MEPF", ++ .pme_code = 0x524042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_INST_ALL_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x514044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_LL4 ] = { ++ .pme_name = "PM_INST_ALL_FROM_LL4", ++ .pme_code = 0x51404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_LMEM ] = { ++ .pme_name = "PM_INST_ALL_FROM_LMEM", ++ .pme_code = 0x524048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_MEMORY ] = { ++ .pme_name = "PM_INST_ALL_FROM_MEMORY", ++ .pme_code = 0x52404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_INST_ALL_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x54404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_INST_ALL_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x514048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_INST_ALL_FROM_RL2L3_MOD", ++ .pme_code = 0x524046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_INST_ALL_FROM_RL2L3_SHR", ++ .pme_code = 0x51404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_RL4 ] = { ++ .pme_name = "PM_INST_ALL_FROM_RL4", ++ .pme_code = 0x52404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_FROM_RMEM ] = { ++ .pme_name = "PM_INST_ALL_FROM_RMEM", ++ .pme_code = 0x53404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to instruction fetches and prefetches", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1", ++}, ++[ POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_ALL_GRP_PUMP_CPRED", ++ .pme_code = 0x524050, ++ .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_ALL_GRP_PUMP_MPRED", ++ .pme_code = 0x524052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_INST_ALL_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x514052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_ALL_PUMP_CPRED", ++ .pme_code = 0x514054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_ALL_PUMP_MPRED", ++ .pme_code = 0x544052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_ALL_SYS_PUMP_CPRED", ++ .pme_code = 0x534050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_ALL_SYS_PUMP_MPRED", ++ .pme_code = 0x534052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for instruction fetches and prefetches", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_INST_ALL_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x544050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch", ++}, ++[ POWER8_PME_PM_INST_CHIP_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_CHIP_PUMP_CPRED", ++ .pme_code = 0x14050, ++ .pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch.", ++}, + [ POWER8_PME_PM_INST_CMPL ] = { + .pme_name = "PM_INST_CMPL", +- .pme_code = 0x10002, ++ .pme_code = 0x2, + .pme_short_desc = "Number of PowerPC Instructions that completed.", + .pme_long_desc = "PPC Instructions Finished (completed).", + }, ++[ POWER8_PME_PM_INST_DISP ] = { ++ .pme_name = "PM_INST_DISP", ++ .pme_code = 0x200f2, ++ .pme_short_desc = "PPC Dispatched", ++ .pme_long_desc = "PPC Dispatched.", ++}, ++[ POWER8_PME_PM_INST_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_INST_FROM_DL2L3_MOD", ++ .pme_code = 0x44048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_INST_FROM_DL2L3_SHR", ++ .pme_code = 0x34048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_DL4 ] = { ++ .pme_name = "PM_INST_FROM_DL4", ++ .pme_code = 0x3404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_DMEM ] = { ++ .pme_name = "PM_INST_FROM_DMEM", ++ .pme_code = 0x4404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L1 ] = { ++ .pme_name = "PM_INST_FROM_L1", ++ .pme_code = 0x4080, ++ .pme_short_desc = "Instruction fetches from L1", ++ .pme_long_desc = "Instruction fetches from L1", ++}, ++[ POWER8_PME_PM_INST_FROM_L2 ] = { ++ .pme_name = "PM_INST_FROM_L2", ++ .pme_code = 0x14042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L21_MOD ] = { ++ .pme_name = "PM_INST_FROM_L21_MOD", ++ .pme_code = 0x44046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L21_SHR ] = { ++ .pme_name = "PM_INST_FROM_L21_SHR", ++ .pme_code = 0x34046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L2MISS ] = { ++ .pme_name = "PM_INST_FROM_L2MISS", ++ .pme_code = 0x1404e, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x34040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x44040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L2_MEPF ] = { ++ .pme_name = "PM_INST_FROM_L2_MEPF", ++ .pme_code = 0x24040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_INST_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x14040, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L3 ] = { ++ .pme_name = "PM_INST_FROM_L3", ++ .pme_code = 0x44042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_INST_FROM_L31_ECO_MOD", ++ .pme_code = 0x44044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_INST_FROM_L31_ECO_SHR", ++ .pme_code = 0x34044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L31_MOD ] = { ++ .pme_name = "PM_INST_FROM_L31_MOD", ++ .pme_code = 0x24044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L31_SHR ] = { ++ .pme_name = "PM_INST_FROM_L31_SHR", ++ .pme_code = 0x14046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L3MISS ] = { ++ .pme_name = "PM_INST_FROM_L3MISS", ++ .pme_code = 0x300fa, ++ .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", ++ .pme_long_desc = "Inst from L3 miss.", ++}, ++[ POWER8_PME_PM_INST_FROM_L3MISS_MOD ] = { ++ .pme_name = "PM_INST_FROM_L3MISS_MOD", ++ .pme_code = 0x4404e, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_INST_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x34042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L3_MEPF ] = { ++ .pme_name = "PM_INST_FROM_L3_MEPF", ++ .pme_code = 0x24042, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_INST_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x14044, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_LL4 ] = { ++ .pme_name = "PM_INST_FROM_LL4", ++ .pme_code = 0x1404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_LMEM ] = { ++ .pme_name = "PM_INST_FROM_LMEM", ++ .pme_code = 0x24048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_MEMORY ] = { ++ .pme_name = "PM_INST_FROM_MEMORY", ++ .pme_code = 0x2404c, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_INST_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_INST_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x14048, ++ .pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_INST_FROM_RL2L3_MOD", ++ .pme_code = 0x24046, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_INST_FROM_RL2L3_SHR", ++ .pme_code = 0x1404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_RL4 ] = { ++ .pme_name = "PM_INST_FROM_RL4", ++ .pme_code = 0x2404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_FROM_RMEM ] = { ++ .pme_name = "PM_INST_FROM_RMEM", ++ .pme_code = 0x3404a, ++ .pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", ++ .pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .", ++}, ++[ POWER8_PME_PM_INST_GRP_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_GRP_PUMP_CPRED", ++ .pme_code = 0x24050, ++ .pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch.", ++}, ++[ POWER8_PME_PM_INST_GRP_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_GRP_PUMP_MPRED", ++ .pme_code = 0x24052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro", ++}, ++[ POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_INST_GRP_PUMP_MPRED_RTY", ++ .pme_code = 0x14052, ++ .pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch", ++ .pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch.", ++}, ++[ POWER8_PME_PM_INST_IMC_MATCH_CMPL ] = { ++ .pme_name = "PM_INST_IMC_MATCH_CMPL", ++ .pme_code = 0x1003a, ++ .pme_short_desc = "IMC Match Count ( Not architected in P8)", ++ .pme_long_desc = "IMC Match Count.", ++}, ++[ POWER8_PME_PM_INST_IMC_MATCH_DISP ] = { ++ .pme_name = "PM_INST_IMC_MATCH_DISP", ++ .pme_code = 0x30016, ++ .pme_short_desc = "Matched Instructions Dispatched", ++ .pme_long_desc = "IMC Matches dispatched.", ++}, ++[ POWER8_PME_PM_INST_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_PUMP_CPRED", ++ .pme_code = 0x14054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch.", ++}, ++[ POWER8_PME_PM_INST_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_PUMP_MPRED", ++ .pme_code = 0x44052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch.", ++}, ++[ POWER8_PME_PM_INST_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_INST_SYS_PUMP_CPRED", ++ .pme_code = 0x34050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch.", ++}, ++[ POWER8_PME_PM_INST_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_INST_SYS_PUMP_MPRED", ++ .pme_code = 0x34052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_INST_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x44050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch.", ++}, + [ POWER8_PME_PM_IOPS_CMPL ] = { + .pme_name = "PM_IOPS_CMPL", + .pme_code = 0x10014, + .pme_short_desc = "Internal Operations completed", + .pme_long_desc = "IOPS Completed.", + }, ++[ POWER8_PME_PM_IOPS_DISP ] = { ++ .pme_name = "PM_IOPS_DISP", ++ .pme_code = 0x30014, ++ .pme_short_desc = "Internal Operations dispatched", ++ .pme_long_desc = "IOPS dispatched.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_IPTEG_FROM_DL2L3_MOD", ++ .pme_code = 0x45048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_IPTEG_FROM_DL2L3_SHR", ++ .pme_code = 0x35048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_DL4 ] = { ++ .pme_name = "PM_IPTEG_FROM_DL4", ++ .pme_code = 0x3504c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_DMEM ] = { ++ .pme_name = "PM_IPTEG_FROM_DMEM", ++ .pme_code = 0x4504c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2 ] = { ++ .pme_name = "PM_IPTEG_FROM_L2", ++ .pme_code = 0x15042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L21_MOD ] = { ++ .pme_name = "PM_IPTEG_FROM_L21_MOD", ++ .pme_code = 0x45046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L21_SHR ] = { ++ .pme_name = "PM_IPTEG_FROM_L21_SHR", ++ .pme_code = 0x35046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2MISS ] = { ++ .pme_name = "PM_IPTEG_FROM_L2MISS", ++ .pme_code = 0x1504e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x35040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x45040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2_MEPF ] = { ++ .pme_name = "PM_IPTEG_FROM_L2_MEPF", ++ .pme_code = 0x25040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x15040, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L3 ] = { ++ .pme_name = "PM_IPTEG_FROM_L3", ++ .pme_code = 0x45042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_IPTEG_FROM_L31_ECO_MOD", ++ .pme_code = 0x45044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_IPTEG_FROM_L31_ECO_SHR", ++ .pme_code = 0x35044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L31_MOD ] = { ++ .pme_name = "PM_IPTEG_FROM_L31_MOD", ++ .pme_code = 0x25044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L31_SHR ] = { ++ .pme_name = "PM_IPTEG_FROM_L31_SHR", ++ .pme_code = 0x15046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L3MISS ] = { ++ .pme_name = "PM_IPTEG_FROM_L3MISS", ++ .pme_code = 0x4504e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x35042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L3_MEPF ] = { ++ .pme_name = "PM_IPTEG_FROM_L3_MEPF", ++ .pme_code = 0x25042, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x15044, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_LL4 ] = { ++ .pme_name = "PM_IPTEG_FROM_LL4", ++ .pme_code = 0x1504c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_LMEM ] = { ++ .pme_name = "PM_IPTEG_FROM_LMEM", ++ .pme_code = 0x25048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_MEMORY ] = { ++ .pme_name = "PM_IPTEG_FROM_MEMORY", ++ .pme_code = 0x2504c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4504a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x15048, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_IPTEG_FROM_RL2L3_MOD", ++ .pme_code = 0x25046, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_IPTEG_FROM_RL2L3_SHR", ++ .pme_code = 0x1504a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_RL4 ] = { ++ .pme_name = "PM_IPTEG_FROM_RL4", ++ .pme_code = 0x2504a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request.", ++}, ++[ POWER8_PME_PM_IPTEG_FROM_RMEM ] = { ++ .pme_name = "PM_IPTEG_FROM_RMEM", ++ .pme_code = 0x3504a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request.", ++}, ++[ POWER8_PME_PM_ISIDE_DISP ] = { ++ .pme_name = "PM_ISIDE_DISP", ++ .pme_code = 0x617082, ++ .pme_short_desc = "All i-side dispatch attempts", ++ .pme_long_desc = "All i-side dispatch attempts", ++}, ++[ POWER8_PME_PM_ISIDE_DISP_FAIL ] = { ++ .pme_name = "PM_ISIDE_DISP_FAIL", ++ .pme_code = 0x627084, ++ .pme_short_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine", ++ .pme_long_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine", ++}, ++[ POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER ] = { ++ .pme_name = "PM_ISIDE_DISP_FAIL_OTHER", ++ .pme_code = 0x627086, ++ .pme_short_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision", ++ .pme_long_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision", ++}, ++[ POWER8_PME_PM_ISIDE_L2MEMACC ] = { ++ .pme_name = "PM_ISIDE_L2MEMACC", ++ .pme_code = 0x4608e, ++ .pme_short_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)", ++ .pme_long_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)", ++}, ++[ POWER8_PME_PM_ISIDE_MRU_TOUCH ] = { ++ .pme_name = "PM_ISIDE_MRU_TOUCH", ++ .pme_code = 0x44608e, ++ .pme_short_desc = "Iside L2 MRU touch", ++ .pme_long_desc = "Iside L2 MRU touch", ++}, ++[ POWER8_PME_PM_ISLB_MISS ] = { ++ .pme_name = "PM_ISLB_MISS", ++ .pme_code = 0xd096, ++ .pme_short_desc = "I SLB Miss.", ++ .pme_long_desc = "I SLB Miss.", ++}, ++[ POWER8_PME_PM_ISU_REF_FX0 ] = { ++ .pme_name = "PM_ISU_REF_FX0", ++ .pme_code = 0x30ac, ++ .pme_short_desc = "FX0 ISU reject", ++ .pme_long_desc = "FX0 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REF_FX1 ] = { ++ .pme_name = "PM_ISU_REF_FX1", ++ .pme_code = 0x30ae, ++ .pme_short_desc = "FX1 ISU reject", ++ .pme_long_desc = "FX1 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REF_FXU ] = { ++ .pme_name = "PM_ISU_REF_FXU", ++ .pme_code = 0x38ac, ++ .pme_short_desc = "FXU ISU reject from either pipe", ++ .pme_long_desc = "ISU", ++}, ++[ POWER8_PME_PM_ISU_REF_LS0 ] = { ++ .pme_name = "PM_ISU_REF_LS0", ++ .pme_code = 0x30b0, ++ .pme_short_desc = "LS0 ISU reject", ++ .pme_long_desc = "LS0 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REF_LS1 ] = { ++ .pme_name = "PM_ISU_REF_LS1", ++ .pme_code = 0x30b2, ++ .pme_short_desc = "LS1 ISU reject", ++ .pme_long_desc = "LS1 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REF_LS2 ] = { ++ .pme_name = "PM_ISU_REF_LS2", ++ .pme_code = 0x30b4, ++ .pme_short_desc = "LS2 ISU reject", ++ .pme_long_desc = "LS2 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REF_LS3 ] = { ++ .pme_name = "PM_ISU_REF_LS3", ++ .pme_code = 0x30b6, ++ .pme_short_desc = "LS3 ISU reject", ++ .pme_long_desc = "LS3 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REJECTS_ALL ] = { ++ .pme_name = "PM_ISU_REJECTS_ALL", ++ .pme_code = 0x309c, ++ .pme_short_desc = "All isu rejects could be more than 1 per cycle", ++ .pme_long_desc = "All isu rejects could be more than 1 per cycle", ++}, ++[ POWER8_PME_PM_ISU_REJECT_RES_NA ] = { ++ .pme_name = "PM_ISU_REJECT_RES_NA", ++ .pme_code = 0x30a2, ++ .pme_short_desc = "ISU reject due to resource not available", ++ .pme_long_desc = "ISU reject due to resource not available", ++}, ++[ POWER8_PME_PM_ISU_REJECT_SAR_BYPASS ] = { ++ .pme_name = "PM_ISU_REJECT_SAR_BYPASS", ++ .pme_code = 0x309e, ++ .pme_short_desc = "Reject because of SAR bypass", ++ .pme_long_desc = "Reject because of SAR bypass", ++}, ++[ POWER8_PME_PM_ISU_REJECT_SRC_NA ] = { ++ .pme_name = "PM_ISU_REJECT_SRC_NA", ++ .pme_code = 0x30a0, ++ .pme_short_desc = "ISU reject due to source not available", ++ .pme_long_desc = "ISU reject due to source not available", ++}, ++[ POWER8_PME_PM_ISU_REJ_VS0 ] = { ++ .pme_name = "PM_ISU_REJ_VS0", ++ .pme_code = 0x30a8, ++ .pme_short_desc = "VS0 ISU reject", ++ .pme_long_desc = "VS0 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REJ_VS1 ] = { ++ .pme_name = "PM_ISU_REJ_VS1", ++ .pme_code = 0x30aa, ++ .pme_short_desc = "VS1 ISU reject", ++ .pme_long_desc = "VS1 ISU reject", ++}, ++[ POWER8_PME_PM_ISU_REJ_VSU ] = { ++ .pme_name = "PM_ISU_REJ_VSU", ++ .pme_code = 0x38a8, ++ .pme_short_desc = "VSU ISU reject from either pipe", ++ .pme_long_desc = "ISU", ++}, ++[ POWER8_PME_PM_ISYNC ] = { ++ .pme_name = "PM_ISYNC", ++ .pme_code = 0x30b8, ++ .pme_short_desc = "Isync count per thread", ++ .pme_long_desc = "Isync count per thread", ++}, ++[ POWER8_PME_PM_ITLB_MISS ] = { ++ .pme_name = "PM_ITLB_MISS", ++ .pme_code = 0x400fc, ++ .pme_short_desc = "ITLB Reloaded (always zero on POWER6)", ++ .pme_long_desc = "ITLB Reloaded.", ++}, ++[ POWER8_PME_PM_L1MISS_LAT_EXC_1024 ] = { ++ .pme_name = "PM_L1MISS_LAT_EXC_1024", ++ .pme_code = 0x200301ea, ++ .pme_short_desc = "L1 misses that took longer than 1024 cyles to resolve (miss to reload)", ++ .pme_long_desc = "Reload latency exceeded 1024 cyc", ++}, ++[ POWER8_PME_PM_L1MISS_LAT_EXC_2048 ] = { ++ .pme_name = "PM_L1MISS_LAT_EXC_2048", ++ .pme_code = 0x200401ec, ++ .pme_short_desc = "L1 misses that took longer than 2048 cyles to resolve (miss to reload)", ++ .pme_long_desc = "Reload latency exceeded 2048 cyc", ++}, ++[ POWER8_PME_PM_L1MISS_LAT_EXC_256 ] = { ++ .pme_name = "PM_L1MISS_LAT_EXC_256", ++ .pme_code = 0x200101e8, ++ .pme_short_desc = "L1 misses that took longer than 256 cyles to resolve (miss to reload)", ++ .pme_long_desc = "Reload latency exceeded 256 cyc", ++}, ++[ POWER8_PME_PM_L1MISS_LAT_EXC_32 ] = { ++ .pme_name = "PM_L1MISS_LAT_EXC_32", ++ .pme_code = 0x200201e6, ++ .pme_short_desc = "L1 misses that took longer than 32 cyles to resolve (miss to reload)", ++ .pme_long_desc = "Reload latency exceeded 32 cyc", ++}, ++[ POWER8_PME_PM_L1PF_L2MEMACC ] = { ++ .pme_name = "PM_L1PF_L2MEMACC", ++ .pme_code = 0x26086, ++ .pme_short_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)", ++ .pme_long_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)", ++}, ++[ POWER8_PME_PM_L1_DCACHE_RELOADED_ALL ] = { ++ .pme_name = "PM_L1_DCACHE_RELOADED_ALL", ++ .pme_code = 0x1002c, ++ .pme_short_desc = "L1 data cache reloaded for demand or prefetch", ++ .pme_long_desc = "L1 data cache reloaded for demand or prefetch .", ++}, ++[ POWER8_PME_PM_L1_DCACHE_RELOAD_VALID ] = { ++ .pme_name = "PM_L1_DCACHE_RELOAD_VALID", ++ .pme_code = 0x300f6, ++ .pme_short_desc = "DL1 reloaded due to Demand Load", ++ .pme_long_desc = "DL1 reloaded due to Demand Load .", ++}, ++[ POWER8_PME_PM_L1_DEMAND_WRITE ] = { ++ .pme_name = "PM_L1_DEMAND_WRITE", ++ .pme_code = 0x408c, ++ .pme_short_desc = "Instruction Demand sectors wriittent into IL1", ++ .pme_long_desc = "Instruction Demand sectors wriittent into IL1", ++}, ++[ POWER8_PME_PM_L1_ICACHE_MISS ] = { ++ .pme_name = "PM_L1_ICACHE_MISS", ++ .pme_code = 0x200fd, ++ .pme_short_desc = "Demand iCache Miss", ++ .pme_long_desc = "Demand iCache Miss.", ++}, ++[ POWER8_PME_PM_L1_ICACHE_RELOADED_ALL ] = { ++ .pme_name = "PM_L1_ICACHE_RELOADED_ALL", ++ .pme_code = 0x40012, ++ .pme_short_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch", ++ .pme_long_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch.", ++}, ++[ POWER8_PME_PM_L1_ICACHE_RELOADED_PREF ] = { ++ .pme_name = "PM_L1_ICACHE_RELOADED_PREF", ++ .pme_code = 0x30068, ++ .pme_short_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)", ++ .pme_long_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch).", ++}, ++[ POWER8_PME_PM_L2_CASTOUT_MOD ] = { ++ .pme_name = "PM_L2_CASTOUT_MOD", ++ .pme_code = 0x417080, ++ .pme_short_desc = "L2 Castouts - Modified (M, Mu, Me)", ++ .pme_long_desc = "L2 Castouts - Modified (M, Mu, Me)", ++}, ++[ POWER8_PME_PM_L2_CASTOUT_SHR ] = { ++ .pme_name = "PM_L2_CASTOUT_SHR", ++ .pme_code = 0x417082, ++ .pme_short_desc = "L2 Castouts - Shared (T, Te, Si, S)", ++ .pme_long_desc = "L2 Castouts - Shared (T, Te, Si, S)", ++}, ++[ POWER8_PME_PM_L2_CHIP_PUMP ] = { ++ .pme_name = "PM_L2_CHIP_PUMP", ++ .pme_code = 0x27084, ++ .pme_short_desc = "RC requests that were local on chip pump attempts", ++ .pme_long_desc = "RC requests that were local on chip pump attempts", ++}, ++[ POWER8_PME_PM_L2_DC_INV ] = { ++ .pme_name = "PM_L2_DC_INV", ++ .pme_code = 0x427086, ++ .pme_short_desc = "Dcache invalidates from L2", ++ .pme_long_desc = "Dcache invalidates from L2", ++}, ++[ POWER8_PME_PM_L2_DISP_ALL_L2MISS ] = { ++ .pme_name = "PM_L2_DISP_ALL_L2MISS", ++ .pme_code = 0x44608c, ++ .pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2miss.", ++ .pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2miss.", ++}, ++[ POWER8_PME_PM_L2_GROUP_PUMP ] = { ++ .pme_name = "PM_L2_GROUP_PUMP", ++ .pme_code = 0x27086, ++ .pme_short_desc = "RC requests that were on Node Pump attempts", ++ .pme_long_desc = "RC requests that were on Node Pump attempts", ++}, ++[ POWER8_PME_PM_L2_GRP_GUESS_CORRECT ] = { ++ .pme_name = "PM_L2_GRP_GUESS_CORRECT", ++ .pme_code = 0x626084, ++ .pme_short_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)", ++ .pme_long_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)", ++}, ++[ POWER8_PME_PM_L2_GRP_GUESS_WRONG ] = { ++ .pme_name = "PM_L2_GRP_GUESS_WRONG", ++ .pme_code = 0x626086, ++ .pme_short_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)", ++ .pme_long_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)", ++}, ++[ POWER8_PME_PM_L2_IC_INV ] = { ++ .pme_name = "PM_L2_IC_INV", ++ .pme_code = 0x427084, ++ .pme_short_desc = "Icache Invalidates from L2", ++ .pme_long_desc = "Icache Invalidates from L2", ++}, ++[ POWER8_PME_PM_L2_INST ] = { ++ .pme_name = "PM_L2_INST", ++ .pme_code = 0x436088, ++ .pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", ++ .pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)", ++}, ++[ POWER8_PME_PM_L2_INST_MISS ] = { ++ .pme_name = "PM_L2_INST_MISS", ++ .pme_code = 0x43608a, ++ .pme_short_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)", ++ .pme_long_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)", ++}, ++[ POWER8_PME_PM_L2_LD ] = { ++ .pme_name = "PM_L2_LD", ++ .pme_code = 0x416080, ++ .pme_short_desc = "All successful D-side Load dispatches for this thread", ++ .pme_long_desc = "All successful D-side Load dispatches for this thread", ++}, ++[ POWER8_PME_PM_L2_LD_DISP ] = { ++ .pme_name = "PM_L2_LD_DISP", ++ .pme_code = 0x437088, ++ .pme_short_desc = "All successful load dispatches", ++ .pme_long_desc = "All successful load dispatches", ++}, ++[ POWER8_PME_PM_L2_LD_HIT ] = { ++ .pme_name = "PM_L2_LD_HIT", ++ .pme_code = 0x43708a, ++ .pme_short_desc = "All successful load dispatches that were L2 hits", ++ .pme_long_desc = "All successful load dispatches that were L2 hits", ++}, ++[ POWER8_PME_PM_L2_LD_MISS ] = { ++ .pme_name = "PM_L2_LD_MISS", ++ .pme_code = 0x426084, ++ .pme_short_desc = "All successful D-Side Load dispatches that were an L2miss for this thread", ++ .pme_long_desc = "All successful D-Side Load dispatches that were an L2miss for this thread", ++}, ++[ POWER8_PME_PM_L2_LOC_GUESS_CORRECT ] = { ++ .pme_name = "PM_L2_LOC_GUESS_CORRECT", ++ .pme_code = 0x616080, ++ .pme_short_desc = "L2 guess loc and guess was correct (ie data local)", ++ .pme_long_desc = "L2 guess loc and guess was correct (ie data local)", ++}, ++[ POWER8_PME_PM_L2_LOC_GUESS_WRONG ] = { ++ .pme_name = "PM_L2_LOC_GUESS_WRONG", ++ .pme_code = 0x616082, ++ .pme_short_desc = "L2 guess loc and guess was not correct (ie data not on chip)", ++ .pme_long_desc = "L2 guess loc and guess was not correct (ie data not on chip)", ++}, ++[ POWER8_PME_PM_L2_RCLD_DISP ] = { ++ .pme_name = "PM_L2_RCLD_DISP", ++ .pme_code = 0x516080, ++ .pme_short_desc = "L2 RC load dispatch attempt", ++ .pme_long_desc = "L2 RC load dispatch attempt", ++}, ++[ POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { ++ .pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR", ++ .pme_code = 0x516082, ++ .pme_short_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", ++ .pme_long_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", ++}, ++[ POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { ++ .pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER", ++ .pme_code = 0x526084, ++ .pme_short_desc = "L2 RC load dispatch attempt failed due to other reasons", ++ .pme_long_desc = "L2 RC load dispatch attempt failed due to other reasons", ++}, ++[ POWER8_PME_PM_L2_RCST_DISP ] = { ++ .pme_name = "PM_L2_RCST_DISP", ++ .pme_code = 0x536088, ++ .pme_short_desc = "L2 RC store dispatch attempt", ++ .pme_long_desc = "L2 RC store dispatch attempt", ++}, ++[ POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { ++ .pme_name = "PM_L2_RCST_DISP_FAIL_ADDR", ++ .pme_code = 0x53608a, ++ .pme_short_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", ++ .pme_long_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", ++}, ++[ POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { ++ .pme_name = "PM_L2_RCST_DISP_FAIL_OTHER", ++ .pme_code = 0x54608c, ++ .pme_short_desc = "L2 RC store dispatch attempt failed due to other reasons", ++ .pme_long_desc = "L2 RC store dispatch attempt failed due to other reasons", ++}, ++[ POWER8_PME_PM_L2_RC_ST_DONE ] = { ++ .pme_name = "PM_L2_RC_ST_DONE", ++ .pme_code = 0x537088, ++ .pme_short_desc = "RC did st to line that was Tx or Sx", ++ .pme_long_desc = "RC did st to line that was Tx or Sx", ++}, ++[ POWER8_PME_PM_L2_RTY_LD ] = { ++ .pme_name = "PM_L2_RTY_LD", ++ .pme_code = 0x63708a, ++ .pme_short_desc = "RC retries on PB for any load from core", ++ .pme_long_desc = "RC retries on PB for any load from core", ++}, ++[ POWER8_PME_PM_L2_RTY_ST ] = { ++ .pme_name = "PM_L2_RTY_ST", ++ .pme_code = 0x3708a, ++ .pme_short_desc = "RC retries on PB for any store from core", ++ .pme_long_desc = "RC retries on PB for any store from core", ++}, ++[ POWER8_PME_PM_L2_SN_M_RD_DONE ] = { ++ .pme_name = "PM_L2_SN_M_RD_DONE", ++ .pme_code = 0x54708c, ++ .pme_short_desc = "SNP dispatched for a read and was M", ++ .pme_long_desc = "SNP dispatched for a read and was M", ++}, ++[ POWER8_PME_PM_L2_SN_M_WR_DONE ] = { ++ .pme_name = "PM_L2_SN_M_WR_DONE", ++ .pme_code = 0x54708e, ++ .pme_short_desc = "SNP dispatched for a write and was M", ++ .pme_long_desc = "SNP dispatched for a write and was M", ++}, ++[ POWER8_PME_PM_L2_SN_SX_I_DONE ] = { ++ .pme_name = "PM_L2_SN_SX_I_DONE", ++ .pme_code = 0x53708a, ++ .pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix", ++ .pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix", ++}, ++[ POWER8_PME_PM_L2_ST ] = { ++ .pme_name = "PM_L2_ST", ++ .pme_code = 0x17080, ++ .pme_short_desc = "All successful D-side store dispatches for this thread", ++ .pme_long_desc = "All successful D-side store dispatches for this thread", ++}, ++[ POWER8_PME_PM_L2_ST_DISP ] = { ++ .pme_name = "PM_L2_ST_DISP", ++ .pme_code = 0x44708c, ++ .pme_short_desc = "All successful store dispatches", ++ .pme_long_desc = "All successful store dispatches", ++}, ++[ POWER8_PME_PM_L2_ST_HIT ] = { ++ .pme_name = "PM_L2_ST_HIT", ++ .pme_code = 0x44708e, ++ .pme_short_desc = "All successful store dispatches that were L2Hits", ++ .pme_long_desc = "All successful store dispatches that were L2Hits", ++}, ++[ POWER8_PME_PM_L2_ST_MISS ] = { ++ .pme_name = "PM_L2_ST_MISS", ++ .pme_code = 0x17082, ++ .pme_short_desc = "All successful D-side store dispatches for this thread that were L2 Miss", ++ .pme_long_desc = "All successful D-side store dispatches for this thread that were L2 Miss", ++}, ++[ POWER8_PME_PM_L2_SYS_GUESS_CORRECT ] = { ++ .pme_name = "PM_L2_SYS_GUESS_CORRECT", ++ .pme_code = 0x636088, ++ .pme_short_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)", ++ .pme_long_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)", ++}, ++[ POWER8_PME_PM_L2_SYS_GUESS_WRONG ] = { ++ .pme_name = "PM_L2_SYS_GUESS_WRONG", ++ .pme_code = 0x63608a, ++ .pme_short_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)", ++ .pme_long_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)", ++}, ++[ POWER8_PME_PM_L2_SYS_PUMP ] = { ++ .pme_name = "PM_L2_SYS_PUMP", ++ .pme_code = 0x617080, ++ .pme_short_desc = "RC requests that were system pump attempts", ++ .pme_long_desc = "RC requests that were system pump attempts", ++}, ++[ POWER8_PME_PM_L2_TM_REQ_ABORT ] = { ++ .pme_name = "PM_L2_TM_REQ_ABORT", ++ .pme_code = 0x1e05e, ++ .pme_short_desc = "TM abort", ++ .pme_long_desc = "TM abort.", ++}, ++[ POWER8_PME_PM_L2_TM_ST_ABORT_SISTER ] = { ++ .pme_name = "PM_L2_TM_ST_ABORT_SISTER", ++ .pme_code = 0x3e05c, ++ .pme_short_desc = "TM marked store abort", ++ .pme_long_desc = "TM marked store abort.", ++}, ++[ POWER8_PME_PM_L3_CINJ ] = { ++ .pme_name = "PM_L3_CINJ", ++ .pme_code = 0x23808a, ++ .pme_short_desc = "l3 ci of cache inject", ++ .pme_long_desc = "l3 ci of cache inject", ++}, ++[ POWER8_PME_PM_L3_CI_HIT ] = { ++ .pme_name = "PM_L3_CI_HIT", ++ .pme_code = 0x128084, ++ .pme_short_desc = "L3 Castins Hit (total count", ++ .pme_long_desc = "L3 Castins Hit (total count", ++}, ++[ POWER8_PME_PM_L3_CI_MISS ] = { ++ .pme_name = "PM_L3_CI_MISS", ++ .pme_code = 0x128086, ++ .pme_short_desc = "L3 castins miss (total count", ++ .pme_long_desc = "L3 castins miss (total count", ++}, ++[ POWER8_PME_PM_L3_CI_USAGE ] = { ++ .pme_name = "PM_L3_CI_USAGE", ++ .pme_code = 0x819082, ++ .pme_short_desc = "rotating sample of 16 CI or CO actives", ++ .pme_long_desc = "rotating sample of 16 CI or CO actives", ++}, ++[ POWER8_PME_PM_L3_CO ] = { ++ .pme_name = "PM_L3_CO", ++ .pme_code = 0x438088, ++ .pme_short_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)", ++ .pme_long_desc = "l3 castout occuring ( does not include casthrough or log writes (cinj/dmaw)", ++}, ++[ POWER8_PME_PM_L3_CO0_ALLOC ] = { ++ .pme_name = "PM_L3_CO0_ALLOC", ++ .pme_code = 0x83908b, ++ .pme_short_desc = "lifetime, sample of CO machine 0 valid", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_L3_CO0_BUSY ] = { ++ .pme_name = "PM_L3_CO0_BUSY", ++ .pme_code = 0x83908a, ++ .pme_short_desc = "lifetime, sample of CO machine 0 valid", ++ .pme_long_desc = "lifetime, sample of CO machine 0 valid", ++}, ++[ POWER8_PME_PM_L3_CO_L31 ] = { ++ .pme_name = "PM_L3_CO_L31", ++ .pme_code = 0x28086, ++ .pme_short_desc = "L3 CO to L3.1 OR of port 0 and 1 ( lossy)", ++ .pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 ( lossy)", ++}, ++[ POWER8_PME_PM_L3_CO_LCO ] = { ++ .pme_name = "PM_L3_CO_LCO", ++ .pme_code = 0x238088, ++ .pme_short_desc = "Total L3 castouts occurred on LCO", ++ .pme_long_desc = "Total L3 castouts occurred on LCO", ++}, ++[ POWER8_PME_PM_L3_CO_MEM ] = { ++ .pme_name = "PM_L3_CO_MEM", ++ .pme_code = 0x28084, ++ .pme_short_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)", ++ .pme_long_desc = "L3 CO to memory OR of port 0 and 1 ( lossy)", ++}, ++[ POWER8_PME_PM_L3_CO_MEPF ] = { ++ .pme_name = "PM_L3_CO_MEPF", ++ .pme_code = 0x18082, ++ .pme_short_desc = "L3 CO of line in Mep state ( includes casthrough", ++ .pme_long_desc = "L3 CO of line in Mep state ( includes casthrough", ++}, ++[ POWER8_PME_PM_L3_GRP_GUESS_CORRECT ] = { ++ .pme_name = "PM_L3_GRP_GUESS_CORRECT", ++ .pme_code = 0xb19082, ++ .pme_short_desc = "Initial scope=group and data from same group (near) (pred successful)", ++ .pme_long_desc = "Initial scope=group and data from same group (near) (pred successful)", ++}, ++[ POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = { ++ .pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH", ++ .pme_code = 0xb3908a, ++ .pme_short_desc = "Initial scope=group but data from local node. Predition too high", ++ .pme_long_desc = "Initial scope=group but data from local node. Predition too high", ++}, ++[ POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = { ++ .pme_name = "PM_L3_GRP_GUESS_WRONG_LOW", ++ .pme_code = 0xb39088, ++ .pme_short_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low", ++ .pme_long_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low", ++}, ++[ POWER8_PME_PM_L3_HIT ] = { ++ .pme_name = "PM_L3_HIT", ++ .pme_code = 0x218080, ++ .pme_short_desc = "L3 Hits", ++ .pme_long_desc = "L3 Hits", ++}, ++[ POWER8_PME_PM_L3_L2_CO_HIT ] = { ++ .pme_name = "PM_L3_L2_CO_HIT", ++ .pme_code = 0x138088, ++ .pme_short_desc = "L2 castout hits", ++ .pme_long_desc = "L2 castout hits", ++}, ++[ POWER8_PME_PM_L3_L2_CO_MISS ] = { ++ .pme_name = "PM_L3_L2_CO_MISS", ++ .pme_code = 0x13808a, ++ .pme_short_desc = "L2 castout miss", ++ .pme_long_desc = "L2 castout miss", ++}, ++[ POWER8_PME_PM_L3_LAT_CI_HIT ] = { ++ .pme_name = "PM_L3_LAT_CI_HIT", ++ .pme_code = 0x14808c, ++ .pme_short_desc = "L3 Lateral Castins Hit", ++ .pme_long_desc = "L3 Lateral Castins Hit", ++}, ++[ POWER8_PME_PM_L3_LAT_CI_MISS ] = { ++ .pme_name = "PM_L3_LAT_CI_MISS", ++ .pme_code = 0x14808e, ++ .pme_short_desc = "L3 Lateral Castins Miss", ++ .pme_long_desc = "L3 Lateral Castins Miss", ++}, ++[ POWER8_PME_PM_L3_LD_HIT ] = { ++ .pme_name = "PM_L3_LD_HIT", ++ .pme_code = 0x228084, ++ .pme_short_desc = "L3 demand LD Hits", ++ .pme_long_desc = "L3 demand LD Hits", ++}, ++[ POWER8_PME_PM_L3_LD_MISS ] = { ++ .pme_name = "PM_L3_LD_MISS", ++ .pme_code = 0x228086, ++ .pme_short_desc = "L3 demand LD Miss", ++ .pme_long_desc = "L3 demand LD Miss", ++}, ++[ POWER8_PME_PM_L3_LD_PREF ] = { ++ .pme_name = "PM_L3_LD_PREF", ++ .pme_code = 0x1e052, ++ .pme_short_desc = "L3 Load Prefetches", ++ .pme_long_desc = "L3 Load Prefetches.", ++}, ++[ POWER8_PME_PM_L3_LOC_GUESS_CORRECT ] = { ++ .pme_name = "PM_L3_LOC_GUESS_CORRECT", ++ .pme_code = 0xb19080, ++ .pme_short_desc = "initial scope=node/chip and data from local node (local) (pred successful)", ++ .pme_long_desc = "initial scope=node/chip and data from local node (local) (pred successful)", ++}, ++[ POWER8_PME_PM_L3_LOC_GUESS_WRONG ] = { ++ .pme_name = "PM_L3_LOC_GUESS_WRONG", ++ .pme_code = 0xb29086, ++ .pme_short_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low", ++ .pme_long_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low", ++}, ++[ POWER8_PME_PM_L3_MISS ] = { ++ .pme_name = "PM_L3_MISS", ++ .pme_code = 0x218082, ++ .pme_short_desc = "L3 Misses", ++ .pme_long_desc = "L3 Misses", ++}, ++[ POWER8_PME_PM_L3_P0_CO_L31 ] = { ++ .pme_name = "PM_L3_P0_CO_L31", ++ .pme_code = 0x54808c, ++ .pme_short_desc = "l3 CO to L3.1 (lco) port 0", ++ .pme_long_desc = "l3 CO to L3.1 (lco) port 0", ++}, ++[ POWER8_PME_PM_L3_P0_CO_MEM ] = { ++ .pme_name = "PM_L3_P0_CO_MEM", ++ .pme_code = 0x538088, ++ .pme_short_desc = "l3 CO to memory port 0", ++ .pme_long_desc = "l3 CO to memory port 0", ++}, ++[ POWER8_PME_PM_L3_P0_CO_RTY ] = { ++ .pme_name = "PM_L3_P0_CO_RTY", ++ .pme_code = 0x929084, ++ .pme_short_desc = "L3 CO received retry port 0", ++ .pme_long_desc = "L3 CO received retry port 0", ++}, ++[ POWER8_PME_PM_L3_P0_GRP_PUMP ] = { ++ .pme_name = "PM_L3_P0_GRP_PUMP", ++ .pme_code = 0xa29084, ++ .pme_short_desc = "L3 pf sent with grp scope port 0", ++ .pme_long_desc = "L3 pf sent with grp scope port 0", ++}, ++[ POWER8_PME_PM_L3_P0_LCO_DATA ] = { ++ .pme_name = "PM_L3_P0_LCO_DATA", ++ .pme_code = 0x528084, ++ .pme_short_desc = "lco sent with data port 0", ++ .pme_long_desc = "lco sent with data port 0", ++}, ++[ POWER8_PME_PM_L3_P0_LCO_NO_DATA ] = { ++ .pme_name = "PM_L3_P0_LCO_NO_DATA", ++ .pme_code = 0x518080, ++ .pme_short_desc = "dataless l3 lco sent port 0", ++ .pme_long_desc = "dataless l3 lco sent port 0", ++}, ++[ POWER8_PME_PM_L3_P0_LCO_RTY ] = { ++ .pme_name = "PM_L3_P0_LCO_RTY", ++ .pme_code = 0xa4908c, ++ .pme_short_desc = "L3 LCO received retry port 0", ++ .pme_long_desc = "L3 LCO received retry port 0", ++}, ++[ POWER8_PME_PM_L3_P0_NODE_PUMP ] = { ++ .pme_name = "PM_L3_P0_NODE_PUMP", ++ .pme_code = 0xa19080, ++ .pme_short_desc = "L3 pf sent with nodal scope port 0", ++ .pme_long_desc = "L3 pf sent with nodal scope port 0", ++}, ++[ POWER8_PME_PM_L3_P0_PF_RTY ] = { ++ .pme_name = "PM_L3_P0_PF_RTY", ++ .pme_code = 0x919080, ++ .pme_short_desc = "L3 PF received retry port 0", ++ .pme_long_desc = "L3 PF received retry port 0", ++}, ++[ POWER8_PME_PM_L3_P0_SN_HIT ] = { ++ .pme_name = "PM_L3_P0_SN_HIT", ++ .pme_code = 0x939088, ++ .pme_short_desc = "L3 snoop hit port 0", ++ .pme_long_desc = "L3 snoop hit port 0", ++}, ++[ POWER8_PME_PM_L3_P0_SN_INV ] = { ++ .pme_name = "PM_L3_P0_SN_INV", ++ .pme_code = 0x118080, ++ .pme_short_desc = "Port0 snooper detects someone doing a store to a line thats Sx", ++ .pme_long_desc = "Port0 snooper detects someone doing a store to a line thats Sx", ++}, ++[ POWER8_PME_PM_L3_P0_SN_MISS ] = { ++ .pme_name = "PM_L3_P0_SN_MISS", ++ .pme_code = 0x94908c, ++ .pme_short_desc = "L3 snoop miss port 0", ++ .pme_long_desc = "L3 snoop miss port 0", ++}, ++[ POWER8_PME_PM_L3_P0_SYS_PUMP ] = { ++ .pme_name = "PM_L3_P0_SYS_PUMP", ++ .pme_code = 0xa39088, ++ .pme_short_desc = "L3 pf sent with sys scope port 0", ++ .pme_long_desc = "L3 pf sent with sys scope port 0", ++}, ++[ POWER8_PME_PM_L3_P1_CO_L31 ] = { ++ .pme_name = "PM_L3_P1_CO_L31", ++ .pme_code = 0x54808e, ++ .pme_short_desc = "l3 CO to L3.1 (lco) port 1", ++ .pme_long_desc = "l3 CO to L3.1 (lco) port 1", ++}, ++[ POWER8_PME_PM_L3_P1_CO_MEM ] = { ++ .pme_name = "PM_L3_P1_CO_MEM", ++ .pme_code = 0x53808a, ++ .pme_short_desc = "l3 CO to memory port 1", ++ .pme_long_desc = "l3 CO to memory port 1", ++}, ++[ POWER8_PME_PM_L3_P1_CO_RTY ] = { ++ .pme_name = "PM_L3_P1_CO_RTY", ++ .pme_code = 0x929086, ++ .pme_short_desc = "L3 CO received retry port 1", ++ .pme_long_desc = "L3 CO received retry port 1", ++}, ++[ POWER8_PME_PM_L3_P1_GRP_PUMP ] = { ++ .pme_name = "PM_L3_P1_GRP_PUMP", ++ .pme_code = 0xa29086, ++ .pme_short_desc = "L3 pf sent with grp scope port 1", ++ .pme_long_desc = "L3 pf sent with grp scope port 1", ++}, ++[ POWER8_PME_PM_L3_P1_LCO_DATA ] = { ++ .pme_name = "PM_L3_P1_LCO_DATA", ++ .pme_code = 0x528086, ++ .pme_short_desc = "lco sent with data port 1", ++ .pme_long_desc = "lco sent with data port 1", ++}, ++[ POWER8_PME_PM_L3_P1_LCO_NO_DATA ] = { ++ .pme_name = "PM_L3_P1_LCO_NO_DATA", ++ .pme_code = 0x518082, ++ .pme_short_desc = "dataless l3 lco sent port 1", ++ .pme_long_desc = "dataless l3 lco sent port 1", ++}, ++[ POWER8_PME_PM_L3_P1_LCO_RTY ] = { ++ .pme_name = "PM_L3_P1_LCO_RTY", ++ .pme_code = 0xa4908e, ++ .pme_short_desc = "L3 LCO received retry port 1", ++ .pme_long_desc = "L3 LCO received retry port 1", ++}, ++[ POWER8_PME_PM_L3_P1_NODE_PUMP ] = { ++ .pme_name = "PM_L3_P1_NODE_PUMP", ++ .pme_code = 0xa19082, ++ .pme_short_desc = "L3 pf sent with nodal scope port 1", ++ .pme_long_desc = "L3 pf sent with nodal scope port 1", ++}, ++[ POWER8_PME_PM_L3_P1_PF_RTY ] = { ++ .pme_name = "PM_L3_P1_PF_RTY", ++ .pme_code = 0x919082, ++ .pme_short_desc = "L3 PF received retry port 1", ++ .pme_long_desc = "L3 PF received retry port 1", ++}, ++[ POWER8_PME_PM_L3_P1_SN_HIT ] = { ++ .pme_name = "PM_L3_P1_SN_HIT", ++ .pme_code = 0x93908a, ++ .pme_short_desc = "L3 snoop hit port 1", ++ .pme_long_desc = "L3 snoop hit port 1", ++}, ++[ POWER8_PME_PM_L3_P1_SN_INV ] = { ++ .pme_name = "PM_L3_P1_SN_INV", ++ .pme_code = 0x118082, ++ .pme_short_desc = "Port1 snooper detects someone doing a store to a line thats Sx", ++ .pme_long_desc = "Port1 snooper detects someone doing a store to a line thats Sx", ++}, ++[ POWER8_PME_PM_L3_P1_SN_MISS ] = { ++ .pme_name = "PM_L3_P1_SN_MISS", ++ .pme_code = 0x94908e, ++ .pme_short_desc = "L3 snoop miss port 1", ++ .pme_long_desc = "L3 snoop miss port 1", ++}, ++[ POWER8_PME_PM_L3_P1_SYS_PUMP ] = { ++ .pme_name = "PM_L3_P1_SYS_PUMP", ++ .pme_code = 0xa3908a, ++ .pme_short_desc = "L3 pf sent with sys scope port 1", ++ .pme_long_desc = "L3 pf sent with sys scope port 1", ++}, ++[ POWER8_PME_PM_L3_PF0_ALLOC ] = { ++ .pme_name = "PM_L3_PF0_ALLOC", ++ .pme_code = 0x84908d, ++ .pme_short_desc = "lifetime, sample of PF machine 0 valid", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_L3_PF0_BUSY ] = { ++ .pme_name = "PM_L3_PF0_BUSY", ++ .pme_code = 0x84908c, ++ .pme_short_desc = "lifetime, sample of PF machine 0 valid", ++ .pme_long_desc = "lifetime, sample of PF machine 0 valid", ++}, ++[ POWER8_PME_PM_L3_PF_HIT_L3 ] = { ++ .pme_name = "PM_L3_PF_HIT_L3", ++ .pme_code = 0x428084, ++ .pme_short_desc = "l3 pf hit in l3", ++ .pme_long_desc = "l3 pf hit in l3", ++}, ++[ POWER8_PME_PM_L3_PF_MISS_L3 ] = { ++ .pme_name = "PM_L3_PF_MISS_L3", ++ .pme_code = 0x18080, ++ .pme_short_desc = "L3 Prefetch missed in L3", ++ .pme_long_desc = "L3 Prefetch missed in L3", ++}, ++[ POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_L3_PF_OFF_CHIP_CACHE", ++ .pme_code = 0x3808a, ++ .pme_short_desc = "L3 Prefetch from Off chip cache", ++ .pme_long_desc = "L3 Prefetch from Off chip cache", ++}, ++[ POWER8_PME_PM_L3_PF_OFF_CHIP_MEM ] = { ++ .pme_name = "PM_L3_PF_OFF_CHIP_MEM", ++ .pme_code = 0x4808e, ++ .pme_short_desc = "L3 Prefetch from Off chip memory", ++ .pme_long_desc = "L3 Prefetch from Off chip memory", ++}, ++[ POWER8_PME_PM_L3_PF_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_L3_PF_ON_CHIP_CACHE", ++ .pme_code = 0x38088, ++ .pme_short_desc = "L3 Prefetch from On chip cache", ++ .pme_long_desc = "L3 Prefetch from On chip cache", ++}, ++[ POWER8_PME_PM_L3_PF_ON_CHIP_MEM ] = { ++ .pme_name = "PM_L3_PF_ON_CHIP_MEM", ++ .pme_code = 0x4808c, ++ .pme_short_desc = "L3 Prefetch from On chip memory", ++ .pme_long_desc = "L3 Prefetch from On chip memory", ++}, ++[ POWER8_PME_PM_L3_PF_USAGE ] = { ++ .pme_name = "PM_L3_PF_USAGE", ++ .pme_code = 0x829084, ++ .pme_short_desc = "rotating sample of 32 PF actives", ++ .pme_long_desc = "rotating sample of 32 PF actives", ++}, ++[ POWER8_PME_PM_L3_PREF_ALL ] = { ++ .pme_name = "PM_L3_PREF_ALL", ++ .pme_code = 0x4e052, ++ .pme_short_desc = "Total HW L3 prefetches(Load+store)", ++ .pme_long_desc = "Total HW L3 prefetches(Load+store).", ++}, ++[ POWER8_PME_PM_L3_RD0_ALLOC ] = { ++ .pme_name = "PM_L3_RD0_ALLOC", ++ .pme_code = 0x84908f, ++ .pme_short_desc = "lifetime, sample of RD machine 0 valid", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_L3_RD0_BUSY ] = { ++ .pme_name = "PM_L3_RD0_BUSY", ++ .pme_code = 0x84908e, ++ .pme_short_desc = "lifetime, sample of RD machine 0 valid", ++ .pme_long_desc = "lifetime, sample of RD machine 0 valid", ++}, ++[ POWER8_PME_PM_L3_RD_USAGE ] = { ++ .pme_name = "PM_L3_RD_USAGE", ++ .pme_code = 0x829086, ++ .pme_short_desc = "rotating sample of 16 RD actives", ++ .pme_long_desc = "rotating sample of 16 RD actives", ++}, ++[ POWER8_PME_PM_L3_SN0_ALLOC ] = { ++ .pme_name = "PM_L3_SN0_ALLOC", ++ .pme_code = 0x839089, ++ .pme_short_desc = "lifetime, sample of snooper machine 0 valid", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_L3_SN0_BUSY ] = { ++ .pme_name = "PM_L3_SN0_BUSY", ++ .pme_code = 0x839088, ++ .pme_short_desc = "lifetime, sample of snooper machine 0 valid", ++ .pme_long_desc = "lifetime, sample of snooper machine 0 valid", ++}, ++[ POWER8_PME_PM_L3_SN_USAGE ] = { ++ .pme_name = "PM_L3_SN_USAGE", ++ .pme_code = 0x819080, ++ .pme_short_desc = "rotating sample of 8 snoop valids", ++ .pme_long_desc = "rotating sample of 8 snoop valids", ++}, ++[ POWER8_PME_PM_L3_ST_PREF ] = { ++ .pme_name = "PM_L3_ST_PREF", ++ .pme_code = 0x2e052, ++ .pme_short_desc = "L3 store Prefetches", ++ .pme_long_desc = "L3 store Prefetches.", ++}, ++[ POWER8_PME_PM_L3_SW_PREF ] = { ++ .pme_name = "PM_L3_SW_PREF", ++ .pme_code = 0x3e052, ++ .pme_short_desc = "Data stream touchto L3", ++ .pme_long_desc = "Data stream touchto L3.", ++}, ++[ POWER8_PME_PM_L3_SYS_GUESS_CORRECT ] = { ++ .pme_name = "PM_L3_SYS_GUESS_CORRECT", ++ .pme_code = 0xb29084, ++ .pme_short_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)", ++ .pme_long_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)", ++}, ++[ POWER8_PME_PM_L3_SYS_GUESS_WRONG ] = { ++ .pme_name = "PM_L3_SYS_GUESS_WRONG", ++ .pme_code = 0xb4908c, ++ .pme_short_desc = "Initial scope=system but data from local or near. Predction too high", ++ .pme_long_desc = "Initial scope=system but data from local or near. Predction too high", ++}, ++[ POWER8_PME_PM_L3_TRANS_PF ] = { ++ .pme_name = "PM_L3_TRANS_PF", ++ .pme_code = 0x24808e, ++ .pme_short_desc = "L3 Transient prefetch", ++ .pme_long_desc = "L3 Transient prefetch", ++}, ++[ POWER8_PME_PM_L3_WI0_ALLOC ] = { ++ .pme_name = "PM_L3_WI0_ALLOC", ++ .pme_code = 0x18081, ++ .pme_short_desc = "lifetime, sample of Write Inject machine 0 valid", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_L3_WI0_BUSY ] = { ++ .pme_name = "PM_L3_WI0_BUSY", ++ .pme_code = 0x418080, ++ .pme_short_desc = "lifetime, sample of Write Inject machine 0 valid", ++ .pme_long_desc = "lifetime, sample of Write Inject machine 0 valid", ++}, ++[ POWER8_PME_PM_L3_WI_USAGE ] = { ++ .pme_name = "PM_L3_WI_USAGE", ++ .pme_code = 0x418082, ++ .pme_short_desc = "rotating sample of 8 WI actives", ++ .pme_long_desc = "rotating sample of 8 WI actives", ++}, ++[ POWER8_PME_PM_LARX_FIN ] = { ++ .pme_name = "PM_LARX_FIN", ++ .pme_code = 0x3c058, ++ .pme_short_desc = "Larx finished", ++ .pme_long_desc = "Larx finished .", ++}, + [ POWER8_PME_PM_LD_CMPL ] = { + .pme_name = "PM_LD_CMPL", + .pme_code = 0x1002e, +@@ -825,17 +4622,839 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Cycles L3 miss was pending for this thread", + .pme_long_desc = "Cycles L3 miss was pending for this thread.", + }, ++[ POWER8_PME_PM_LD_MISS_L1 ] = { ++ .pme_name = "PM_LD_MISS_L1", ++ .pme_code = 0x3e054, ++ .pme_short_desc = "Load Missed L1", ++ .pme_long_desc = "Load Missed L1.", ++}, ++[ POWER8_PME_PM_LD_REF_L1 ] = { ++ .pme_name = "PM_LD_REF_L1", ++ .pme_code = 0x100ee, ++ .pme_short_desc = "All L1 D cache load references counted at finish, gated by reject", ++ .pme_long_desc = "Load Ref count combined for all units.", ++}, ++[ POWER8_PME_PM_LD_REF_L1_LSU0 ] = { ++ .pme_name = "PM_LD_REF_L1_LSU0", ++ .pme_code = 0xc080, ++ .pme_short_desc = "LS0 L1 D cache load references counted at finish, gated by reject", ++ .pme_long_desc = "LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references", ++}, ++[ POWER8_PME_PM_LD_REF_L1_LSU1 ] = { ++ .pme_name = "PM_LD_REF_L1_LSU1", ++ .pme_code = 0xc082, ++ .pme_short_desc = "LS1 L1 D cache load references counted at finish, gated by reject", ++ .pme_long_desc = "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references", ++}, ++[ POWER8_PME_PM_LD_REF_L1_LSU2 ] = { ++ .pme_name = "PM_LD_REF_L1_LSU2", ++ .pme_code = 0xc094, ++ .pme_short_desc = "LS2 L1 D cache load references counted at finish, gated by reject", ++ .pme_long_desc = "LS2 L1 D cache load references counted at finish, gated by reject42", ++}, ++[ POWER8_PME_PM_LD_REF_L1_LSU3 ] = { ++ .pme_name = "PM_LD_REF_L1_LSU3", ++ .pme_code = 0xc096, ++ .pme_short_desc = "LS3 L1 D cache load references counted at finish, gated by reject", ++ .pme_long_desc = "LS3 L1 D cache load references counted at finish, gated by reject42", ++}, ++[ POWER8_PME_PM_LINK_STACK_INVALID_PTR ] = { ++ .pme_name = "PM_LINK_STACK_INVALID_PTR", ++ .pme_code = 0x509a, ++ .pme_short_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops", ++ .pme_long_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops", ++}, ++[ POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = { ++ .pme_name = "PM_LINK_STACK_WRONG_ADD_PRED", ++ .pme_code = 0x5098, ++ .pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation.", ++ .pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation.", ++}, ++[ POWER8_PME_PM_LS0_ERAT_MISS_PREF ] = { ++ .pme_name = "PM_LS0_ERAT_MISS_PREF", ++ .pme_code = 0xe080, ++ .pme_short_desc = "LS0 Erat miss due to prefetch", ++ .pme_long_desc = "LS0 Erat miss due to prefetch42", ++}, ++[ POWER8_PME_PM_LS0_L1_PREF ] = { ++ .pme_name = "PM_LS0_L1_PREF", ++ .pme_code = 0xd0b8, ++ .pme_short_desc = "LS0 L1 cache data prefetches", ++ .pme_long_desc = "LS0 L1 cache data prefetches42", ++}, ++[ POWER8_PME_PM_LS0_L1_SW_PREF ] = { ++ .pme_name = "PM_LS0_L1_SW_PREF", ++ .pme_code = 0xc098, ++ .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches", ++ .pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42", ++}, ++[ POWER8_PME_PM_LS1_ERAT_MISS_PREF ] = { ++ .pme_name = "PM_LS1_ERAT_MISS_PREF", ++ .pme_code = 0xe082, ++ .pme_short_desc = "LS1 Erat miss due to prefetch", ++ .pme_long_desc = "LS1 Erat miss due to prefetch42", ++}, ++[ POWER8_PME_PM_LS1_L1_PREF ] = { ++ .pme_name = "PM_LS1_L1_PREF", ++ .pme_code = 0xd0ba, ++ .pme_short_desc = "LS1 L1 cache data prefetches", ++ .pme_long_desc = "LS1 L1 cache data prefetches42", ++}, ++[ POWER8_PME_PM_LS1_L1_SW_PREF ] = { ++ .pme_name = "PM_LS1_L1_SW_PREF", ++ .pme_code = 0xc09a, ++ .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches", ++ .pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42", ++}, ++[ POWER8_PME_PM_LSU0_FLUSH_LRQ ] = { ++ .pme_name = "PM_LSU0_FLUSH_LRQ", ++ .pme_code = 0xc0b0, ++ .pme_short_desc = "LS0 Flush: LRQ", ++ .pme_long_desc = "LS0 Flush: LRQLSU0 LRQ flushes", ++}, ++[ POWER8_PME_PM_LSU0_FLUSH_SRQ ] = { ++ .pme_name = "PM_LSU0_FLUSH_SRQ", ++ .pme_code = 0xc0b8, ++ .pme_short_desc = "LS0 Flush: SRQ", ++ .pme_long_desc = "LS0 Flush: SRQLSU0 SRQ lhs flushes", ++}, ++[ POWER8_PME_PM_LSU0_FLUSH_ULD ] = { ++ .pme_name = "PM_LSU0_FLUSH_ULD", ++ .pme_code = 0xc0a4, ++ .pme_short_desc = "LS0 Flush: Unaligned Load", ++ .pme_long_desc = "LS0 Flush: Unaligned LoadLSU0 unaligned load flushes", ++}, ++[ POWER8_PME_PM_LSU0_FLUSH_UST ] = { ++ .pme_name = "PM_LSU0_FLUSH_UST", ++ .pme_code = 0xc0ac, ++ .pme_short_desc = "LS0 Flush: Unaligned Store", ++ .pme_long_desc = "LS0 Flush: Unaligned StoreLSU0 unaligned store flushes", ++}, ++[ POWER8_PME_PM_LSU0_L1_CAM_CANCEL ] = { ++ .pme_name = "PM_LSU0_L1_CAM_CANCEL", ++ .pme_code = 0xf088, ++ .pme_short_desc = "ls0 l1 tm cam cancel", ++ .pme_long_desc = "ls0 l1 tm cam cancel42", ++}, ++[ POWER8_PME_PM_LSU0_LARX_FIN ] = { ++ .pme_name = "PM_LSU0_LARX_FIN", ++ .pme_code = 0x1e056, ++ .pme_short_desc = "Larx finished in LSU pipe0", ++ .pme_long_desc = ".", ++}, ++[ POWER8_PME_PM_LSU0_LMQ_LHR_MERGE ] = { ++ .pme_name = "PM_LSU0_LMQ_LHR_MERGE", ++ .pme_code = 0xd08c, ++ .pme_short_desc = "LS0 Load Merged with another cacheline request", ++ .pme_long_desc = "LS0 Load Merged with another cacheline request42", ++}, ++[ POWER8_PME_PM_LSU0_NCLD ] = { ++ .pme_name = "PM_LSU0_NCLD", ++ .pme_code = 0xc08c, ++ .pme_short_desc = "LS0 Non-cachable Loads counted at finish", ++ .pme_long_desc = "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads", ++}, ++[ POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT ] = { ++ .pme_name = "PM_LSU0_PRIMARY_ERAT_HIT", ++ .pme_code = 0xe090, ++ .pme_short_desc = "Primary ERAT hit", ++ .pme_long_desc = "Primary ERAT hit42", ++}, ++[ POWER8_PME_PM_LSU0_REJECT ] = { ++ .pme_name = "PM_LSU0_REJECT", ++ .pme_code = 0x1e05a, ++ .pme_short_desc = "LSU0 reject", ++ .pme_long_desc = "LSU0 reject .", ++}, ++[ POWER8_PME_PM_LSU0_SRQ_STFWD ] = { ++ .pme_name = "PM_LSU0_SRQ_STFWD", ++ .pme_code = 0xc09c, ++ .pme_short_desc = "LS0 SRQ forwarded data to a load", ++ .pme_long_desc = "LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded", ++}, ++[ POWER8_PME_PM_LSU0_STORE_REJECT ] = { ++ .pme_name = "PM_LSU0_STORE_REJECT", ++ .pme_code = 0xf084, ++ .pme_short_desc = "ls0 store reject", ++ .pme_long_desc = "ls0 store reject42", ++}, ++[ POWER8_PME_PM_LSU0_TMA_REQ_L2 ] = { ++ .pme_name = "PM_LSU0_TMA_REQ_L2", ++ .pme_code = 0xe0a8, ++ .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", ++ .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", ++}, ++[ POWER8_PME_PM_LSU0_TM_L1_HIT ] = { ++ .pme_name = "PM_LSU0_TM_L1_HIT", ++ .pme_code = 0xe098, ++ .pme_short_desc = "Load tm hit in L1", ++ .pme_long_desc = "Load tm hit in L142", ++}, ++[ POWER8_PME_PM_LSU0_TM_L1_MISS ] = { ++ .pme_name = "PM_LSU0_TM_L1_MISS", ++ .pme_code = 0xe0a0, ++ .pme_short_desc = "Load tm L1 miss", ++ .pme_long_desc = "Load tm L1 miss42", ++}, ++[ POWER8_PME_PM_LSU1_FLUSH_LRQ ] = { ++ .pme_name = "PM_LSU1_FLUSH_LRQ", ++ .pme_code = 0xc0b2, ++ .pme_short_desc = "LS1 Flush: LRQ", ++ .pme_long_desc = "LS1 Flush: LRQLSU1 LRQ flushes", ++}, ++[ POWER8_PME_PM_LSU1_FLUSH_SRQ ] = { ++ .pme_name = "PM_LSU1_FLUSH_SRQ", ++ .pme_code = 0xc0ba, ++ .pme_short_desc = "LS1 Flush: SRQ", ++ .pme_long_desc = "LS1 Flush: SRQLSU1 SRQ lhs flushes", ++}, ++[ POWER8_PME_PM_LSU1_FLUSH_ULD ] = { ++ .pme_name = "PM_LSU1_FLUSH_ULD", ++ .pme_code = 0xc0a6, ++ .pme_short_desc = "LS 1 Flush: Unaligned Load", ++ .pme_long_desc = "LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes", ++}, ++[ POWER8_PME_PM_LSU1_FLUSH_UST ] = { ++ .pme_name = "PM_LSU1_FLUSH_UST", ++ .pme_code = 0xc0ae, ++ .pme_short_desc = "LS1 Flush: Unaligned Store", ++ .pme_long_desc = "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes", ++}, ++[ POWER8_PME_PM_LSU1_L1_CAM_CANCEL ] = { ++ .pme_name = "PM_LSU1_L1_CAM_CANCEL", ++ .pme_code = 0xf08a, ++ .pme_short_desc = "ls1 l1 tm cam cancel", ++ .pme_long_desc = "ls1 l1 tm cam cancel42", ++}, ++[ POWER8_PME_PM_LSU1_LARX_FIN ] = { ++ .pme_name = "PM_LSU1_LARX_FIN", ++ .pme_code = 0x2e056, ++ .pme_short_desc = "Larx finished in LSU pipe1", ++ .pme_long_desc = "Larx finished in LSU pipe1.", ++}, ++[ POWER8_PME_PM_LSU1_LMQ_LHR_MERGE ] = { ++ .pme_name = "PM_LSU1_LMQ_LHR_MERGE", ++ .pme_code = 0xd08e, ++ .pme_short_desc = "LS1 Load Merge with another cacheline request", ++ .pme_long_desc = "LS1 Load Merge with another cacheline request42", ++}, ++[ POWER8_PME_PM_LSU1_NCLD ] = { ++ .pme_name = "PM_LSU1_NCLD", ++ .pme_code = 0xc08e, ++ .pme_short_desc = "LS1 Non-cachable Loads counted at finish", ++ .pme_long_desc = "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads", ++}, ++[ POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT ] = { ++ .pme_name = "PM_LSU1_PRIMARY_ERAT_HIT", ++ .pme_code = 0xe092, ++ .pme_short_desc = "Primary ERAT hit", ++ .pme_long_desc = "Primary ERAT hit42", ++}, ++[ POWER8_PME_PM_LSU1_REJECT ] = { ++ .pme_name = "PM_LSU1_REJECT", ++ .pme_code = 0x2e05a, ++ .pme_short_desc = "LSU1 reject", ++ .pme_long_desc = "LSU1 reject .", ++}, ++[ POWER8_PME_PM_LSU1_SRQ_STFWD ] = { ++ .pme_name = "PM_LSU1_SRQ_STFWD", ++ .pme_code = 0xc09e, ++ .pme_short_desc = "LS1 SRQ forwarded data to a load", ++ .pme_long_desc = "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded", ++}, ++[ POWER8_PME_PM_LSU1_STORE_REJECT ] = { ++ .pme_name = "PM_LSU1_STORE_REJECT", ++ .pme_code = 0xf086, ++ .pme_short_desc = "ls1 store reject", ++ .pme_long_desc = "ls1 store reject42", ++}, ++[ POWER8_PME_PM_LSU1_TMA_REQ_L2 ] = { ++ .pme_name = "PM_LSU1_TMA_REQ_L2", ++ .pme_code = 0xe0aa, ++ .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", ++ .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", ++}, ++[ POWER8_PME_PM_LSU1_TM_L1_HIT ] = { ++ .pme_name = "PM_LSU1_TM_L1_HIT", ++ .pme_code = 0xe09a, ++ .pme_short_desc = "Load tm hit in L1", ++ .pme_long_desc = "Load tm hit in L142", ++}, ++[ POWER8_PME_PM_LSU1_TM_L1_MISS ] = { ++ .pme_name = "PM_LSU1_TM_L1_MISS", ++ .pme_code = 0xe0a2, ++ .pme_short_desc = "Load tm L1 miss", ++ .pme_long_desc = "Load tm L1 miss42", ++}, ++[ POWER8_PME_PM_LSU2_FLUSH_LRQ ] = { ++ .pme_name = "PM_LSU2_FLUSH_LRQ", ++ .pme_code = 0xc0b4, ++ .pme_short_desc = "LS02Flush: LRQ", ++ .pme_long_desc = "LS02Flush: LRQ42", ++}, ++[ POWER8_PME_PM_LSU2_FLUSH_SRQ ] = { ++ .pme_name = "PM_LSU2_FLUSH_SRQ", ++ .pme_code = 0xc0bc, ++ .pme_short_desc = "LS2 Flush: SRQ", ++ .pme_long_desc = "LS2 Flush: SRQ42", ++}, ++[ POWER8_PME_PM_LSU2_FLUSH_ULD ] = { ++ .pme_name = "PM_LSU2_FLUSH_ULD", ++ .pme_code = 0xc0a8, ++ .pme_short_desc = "LS3 Flush: Unaligned Load", ++ .pme_long_desc = "LS3 Flush: Unaligned Load42", ++}, ++[ POWER8_PME_PM_LSU2_L1_CAM_CANCEL ] = { ++ .pme_name = "PM_LSU2_L1_CAM_CANCEL", ++ .pme_code = 0xf08c, ++ .pme_short_desc = "ls2 l1 tm cam cancel", ++ .pme_long_desc = "ls2 l1 tm cam cancel42", ++}, ++[ POWER8_PME_PM_LSU2_LARX_FIN ] = { ++ .pme_name = "PM_LSU2_LARX_FIN", ++ .pme_code = 0x3e056, ++ .pme_short_desc = "Larx finished in LSU pipe2", ++ .pme_long_desc = "Larx finished in LSU pipe2.", ++}, ++[ POWER8_PME_PM_LSU2_LDF ] = { ++ .pme_name = "PM_LSU2_LDF", ++ .pme_code = 0xc084, ++ .pme_short_desc = "LS2 Scalar Loads", ++ .pme_long_desc = "LS2 Scalar Loads42", ++}, ++[ POWER8_PME_PM_LSU2_LDX ] = { ++ .pme_name = "PM_LSU2_LDX", ++ .pme_code = 0xc088, ++ .pme_short_desc = "LS0 Vector Loads", ++ .pme_long_desc = "LS0 Vector Loads42", ++}, ++[ POWER8_PME_PM_LSU2_LMQ_LHR_MERGE ] = { ++ .pme_name = "PM_LSU2_LMQ_LHR_MERGE", ++ .pme_code = 0xd090, ++ .pme_short_desc = "LS0 Load Merged with another cacheline request", ++ .pme_long_desc = "LS0 Load Merged with another cacheline request42", ++}, ++[ POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT ] = { ++ .pme_name = "PM_LSU2_PRIMARY_ERAT_HIT", ++ .pme_code = 0xe094, ++ .pme_short_desc = "Primary ERAT hit", ++ .pme_long_desc = "Primary ERAT hit42", ++}, ++[ POWER8_PME_PM_LSU2_REJECT ] = { ++ .pme_name = "PM_LSU2_REJECT", ++ .pme_code = 0x3e05a, ++ .pme_short_desc = "LSU2 reject", ++ .pme_long_desc = "LSU2 reject .", ++}, ++[ POWER8_PME_PM_LSU2_SRQ_STFWD ] = { ++ .pme_name = "PM_LSU2_SRQ_STFWD", ++ .pme_code = 0xc0a0, ++ .pme_short_desc = "LS2 SRQ forwarded data to a load", ++ .pme_long_desc = "LS2 SRQ forwarded data to a load42", ++}, ++[ POWER8_PME_PM_LSU2_TMA_REQ_L2 ] = { ++ .pme_name = "PM_LSU2_TMA_REQ_L2", ++ .pme_code = 0xe0ac, ++ .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", ++ .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", ++}, ++[ POWER8_PME_PM_LSU2_TM_L1_HIT ] = { ++ .pme_name = "PM_LSU2_TM_L1_HIT", ++ .pme_code = 0xe09c, ++ .pme_short_desc = "Load tm hit in L1", ++ .pme_long_desc = "Load tm hit in L142", ++}, ++[ POWER8_PME_PM_LSU2_TM_L1_MISS ] = { ++ .pme_name = "PM_LSU2_TM_L1_MISS", ++ .pme_code = 0xe0a4, ++ .pme_short_desc = "Load tm L1 miss", ++ .pme_long_desc = "Load tm L1 miss42", ++}, ++[ POWER8_PME_PM_LSU3_FLUSH_LRQ ] = { ++ .pme_name = "PM_LSU3_FLUSH_LRQ", ++ .pme_code = 0xc0b6, ++ .pme_short_desc = "LS3 Flush: LRQ", ++ .pme_long_desc = "LS3 Flush: LRQ42", ++}, ++[ POWER8_PME_PM_LSU3_FLUSH_SRQ ] = { ++ .pme_name = "PM_LSU3_FLUSH_SRQ", ++ .pme_code = 0xc0be, ++ .pme_short_desc = "LS13 Flush: SRQ", ++ .pme_long_desc = "LS13 Flush: SRQ42", ++}, ++[ POWER8_PME_PM_LSU3_FLUSH_ULD ] = { ++ .pme_name = "PM_LSU3_FLUSH_ULD", ++ .pme_code = 0xc0aa, ++ .pme_short_desc = "LS 14Flush: Unaligned Load", ++ .pme_long_desc = "LS 14Flush: Unaligned Load42", ++}, ++[ POWER8_PME_PM_LSU3_L1_CAM_CANCEL ] = { ++ .pme_name = "PM_LSU3_L1_CAM_CANCEL", ++ .pme_code = 0xf08e, ++ .pme_short_desc = "ls3 l1 tm cam cancel", ++ .pme_long_desc = "ls3 l1 tm cam cancel42", ++}, ++[ POWER8_PME_PM_LSU3_LARX_FIN ] = { ++ .pme_name = "PM_LSU3_LARX_FIN", ++ .pme_code = 0x4e056, ++ .pme_short_desc = "Larx finished in LSU pipe3", ++ .pme_long_desc = "Larx finished in LSU pipe3.", ++}, ++[ POWER8_PME_PM_LSU3_LDF ] = { ++ .pme_name = "PM_LSU3_LDF", ++ .pme_code = 0xc086, ++ .pme_short_desc = "LS3 Scalar Loads", ++ .pme_long_desc = "LS3 Scalar Loads 42", ++}, ++[ POWER8_PME_PM_LSU3_LDX ] = { ++ .pme_name = "PM_LSU3_LDX", ++ .pme_code = 0xc08a, ++ .pme_short_desc = "LS1 Vector Loads", ++ .pme_long_desc = "LS1 Vector Loads42", ++}, ++[ POWER8_PME_PM_LSU3_LMQ_LHR_MERGE ] = { ++ .pme_name = "PM_LSU3_LMQ_LHR_MERGE", ++ .pme_code = 0xd092, ++ .pme_short_desc = "LS1 Load Merge with another cacheline request", ++ .pme_long_desc = "LS1 Load Merge with another cacheline request42", ++}, ++[ POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT ] = { ++ .pme_name = "PM_LSU3_PRIMARY_ERAT_HIT", ++ .pme_code = 0xe096, ++ .pme_short_desc = "Primary ERAT hit", ++ .pme_long_desc = "Primary ERAT hit42", ++}, ++[ POWER8_PME_PM_LSU3_REJECT ] = { ++ .pme_name = "PM_LSU3_REJECT", ++ .pme_code = 0x4e05a, ++ .pme_short_desc = "LSU3 reject", ++ .pme_long_desc = "LSU3 reject .", ++}, ++[ POWER8_PME_PM_LSU3_SRQ_STFWD ] = { ++ .pme_name = "PM_LSU3_SRQ_STFWD", ++ .pme_code = 0xc0a2, ++ .pme_short_desc = "LS3 SRQ forwarded data to a load", ++ .pme_long_desc = "LS3 SRQ forwarded data to a load42", ++}, ++[ POWER8_PME_PM_LSU3_TMA_REQ_L2 ] = { ++ .pme_name = "PM_LSU3_TMA_REQ_L2", ++ .pme_code = 0xe0ae, ++ .pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding", ++ .pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42", ++}, ++[ POWER8_PME_PM_LSU3_TM_L1_HIT ] = { ++ .pme_name = "PM_LSU3_TM_L1_HIT", ++ .pme_code = 0xe09e, ++ .pme_short_desc = "Load tm hit in L1", ++ .pme_long_desc = "Load tm hit in L142", ++}, ++[ POWER8_PME_PM_LSU3_TM_L1_MISS ] = { ++ .pme_name = "PM_LSU3_TM_L1_MISS", ++ .pme_code = 0xe0a6, ++ .pme_short_desc = "Load tm L1 miss", ++ .pme_long_desc = "Load tm L1 miss42", ++}, ++[ POWER8_PME_PM_LSU_DERAT_MISS ] = { ++ .pme_name = "PM_LSU_DERAT_MISS", ++ .pme_code = 0x200f6, ++ .pme_short_desc = "DERAT Reloaded due to a DERAT miss", ++ .pme_long_desc = "DERAT Reloaded (Miss).", ++}, ++[ POWER8_PME_PM_LSU_ERAT_MISS_PREF ] = { ++ .pme_name = "PM_LSU_ERAT_MISS_PREF", ++ .pme_code = 0xe880, ++ .pme_short_desc = "Erat miss due to prefetch, on either pipe", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_FIN ] = { ++ .pme_name = "PM_LSU_FIN", ++ .pme_code = 0x30066, ++ .pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)", ++ .pme_long_desc = "LSU Finished an instruction (up to 2 per cycle).", ++}, ++[ POWER8_PME_PM_LSU_FLUSH_UST ] = { ++ .pme_name = "PM_LSU_FLUSH_UST", ++ .pme_code = 0xc8ac, ++ .pme_short_desc = "Unaligned Store Flush on either pipe", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC ] = { ++ .pme_name = "PM_LSU_FOUR_TABLEWALK_CYC", ++ .pme_code = 0xd0a4, ++ .pme_short_desc = "Cycles when four tablewalks pending on this thread", ++ .pme_long_desc = "Cycles when four tablewalks pending on this thread42", ++}, ++[ POWER8_PME_PM_LSU_FX_FIN ] = { ++ .pme_name = "PM_LSU_FX_FIN", ++ .pme_code = 0x10066, ++ .pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle", ++ .pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle.", ++}, ++[ POWER8_PME_PM_LSU_L1_PREF ] = { ++ .pme_name = "PM_LSU_L1_PREF", ++ .pme_code = 0xd8b8, ++ .pme_short_desc = "hw initiated , include sw streaming forms as well , include sw streams as a separate event", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_L1_SW_PREF ] = { ++ .pme_name = "PM_LSU_L1_SW_PREF", ++ .pme_code = 0xc898, ++ .pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches, on both pipes", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_LDF ] = { ++ .pme_name = "PM_LSU_LDF", ++ .pme_code = 0xc884, ++ .pme_short_desc = "FPU loads only on LS2/LS3 ie LU0/LU1", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_LDX ] = { ++ .pme_name = "PM_LSU_LDX", ++ .pme_code = 0xc888, ++ .pme_short_desc = "Vector loads can issue only on LS2/LS3", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_LMQ_FULL_CYC ] = { ++ .pme_name = "PM_LSU_LMQ_FULL_CYC", ++ .pme_code = 0xd0a2, ++ .pme_short_desc = "LMQ full", ++ .pme_long_desc = "LMQ fullCycles LMQ full,", ++}, ++[ POWER8_PME_PM_LSU_LMQ_S0_ALLOC ] = { ++ .pme_name = "PM_LSU_LMQ_S0_ALLOC", ++ .pme_code = 0xd0a1, ++ .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_LMQ_S0_VALID ] = { ++ .pme_name = "PM_LSU_LMQ_S0_VALID", ++ .pme_code = 0xd0a0, ++ .pme_short_desc = "Slot 0 of LMQ valid", ++ .pme_long_desc = "Slot 0 of LMQ validLMQ slot 0 valid", ++}, ++[ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { ++ .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC", ++ .pme_code = 0x3001c, ++ .pme_short_desc = "ALL threads lsu empty (lmq and srq empty)", ++ .pme_long_desc = "ALL threads lsu empty (lmq and srq empty). Issue HW016541", ++}, ++[ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { ++ .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", ++ .pme_code = 0x2003e, ++ .pme_short_desc = "LSU empty (lmq and srq empty)", ++ .pme_long_desc = "LSU empty (lmq and srq empty).", ++}, ++[ POWER8_PME_PM_LSU_LRQ_S0_ALLOC ] = { ++ .pme_name = "PM_LSU_LRQ_S0_ALLOC", ++ .pme_code = 0xd09f, ++ .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_LRQ_S0_VALID ] = { ++ .pme_name = "PM_LSU_LRQ_S0_VALID", ++ .pme_code = 0xd09e, ++ .pme_short_desc = "Slot 0 of LRQ valid", ++ .pme_long_desc = "Slot 0 of LRQ validLRQ slot 0 valid", ++}, ++[ POWER8_PME_PM_LSU_LRQ_S43_ALLOC ] = { ++ .pme_name = "PM_LSU_LRQ_S43_ALLOC", ++ .pme_code = 0xf091, ++ .pme_short_desc = "LRQ slot 43 was released", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_LRQ_S43_VALID ] = { ++ .pme_name = "PM_LSU_LRQ_S43_VALID", ++ .pme_code = 0xf090, ++ .pme_short_desc = "LRQ slot 43 was busy", ++ .pme_long_desc = "LRQ slot 43 was busy42", ++}, ++[ POWER8_PME_PM_LSU_MRK_DERAT_MISS ] = { ++ .pme_name = "PM_LSU_MRK_DERAT_MISS", ++ .pme_code = 0x30162, ++ .pme_short_desc = "DERAT Reloaded (Miss)", ++ .pme_long_desc = "DERAT Reloaded (Miss).", ++}, ++[ POWER8_PME_PM_LSU_NCLD ] = { ++ .pme_name = "PM_LSU_NCLD", ++ .pme_code = 0xc88c, ++ .pme_short_desc = "count at finish so can return only on ls0 or ls1", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_NCST ] = { ++ .pme_name = "PM_LSU_NCST", ++ .pme_code = 0xc092, ++ .pme_short_desc = "Non-cachable Stores sent to nest", ++ .pme_long_desc = "Non-cachable Stores sent to nest42", ++}, ++[ POWER8_PME_PM_LSU_REJECT ] = { ++ .pme_name = "PM_LSU_REJECT", ++ .pme_code = 0x10064, ++ .pme_short_desc = "LSU Reject (up to 4 per cycle)", ++ .pme_long_desc = "LSU Reject (up to 4 per cycle).", ++}, ++[ POWER8_PME_PM_LSU_REJECT_ERAT_MISS ] = { ++ .pme_name = "PM_LSU_REJECT_ERAT_MISS", ++ .pme_code = 0x2e05c, ++ .pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)", ++ .pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles).", ++}, ++[ POWER8_PME_PM_LSU_REJECT_LHS ] = { ++ .pme_name = "PM_LSU_REJECT_LHS", ++ .pme_code = 0x4e05c, ++ .pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)", ++ .pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle).", ++}, ++[ POWER8_PME_PM_LSU_REJECT_LMQ_FULL ] = { ++ .pme_name = "PM_LSU_REJECT_LMQ_FULL", ++ .pme_code = 0x1e05c, ++ .pme_short_desc = "LSU reject due to LMQ full ( 4 per cycle)", ++ .pme_long_desc = "LSU reject due to LMQ full ( 4 per cycle).", ++}, ++[ POWER8_PME_PM_LSU_SET_MPRED ] = { ++ .pme_name = "PM_LSU_SET_MPRED", ++ .pme_code = 0xd082, ++ .pme_short_desc = "Line already in cache at reload time", ++ .pme_long_desc = "Line already in cache at reload time42", ++}, ++[ POWER8_PME_PM_LSU_SRQ_EMPTY_CYC ] = { ++ .pme_name = "PM_LSU_SRQ_EMPTY_CYC", ++ .pme_code = 0x40008, ++ .pme_short_desc = "ALL threads srq empty", ++ .pme_long_desc = "All threads srq empty.", ++}, ++[ POWER8_PME_PM_LSU_SRQ_FULL_CYC ] = { ++ .pme_name = "PM_LSU_SRQ_FULL_CYC", ++ .pme_code = 0x1001a, ++ .pme_short_desc = "Storage Queue is full and is blocking dispatch", ++ .pme_long_desc = "SRQ is Full.", ++}, ++[ POWER8_PME_PM_LSU_SRQ_S0_ALLOC ] = { ++ .pme_name = "PM_LSU_SRQ_S0_ALLOC", ++ .pme_code = 0xd09d, ++ .pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_SRQ_S0_VALID ] = { ++ .pme_name = "PM_LSU_SRQ_S0_VALID", ++ .pme_code = 0xd09c, ++ .pme_short_desc = "Slot 0 of SRQ valid", ++ .pme_long_desc = "Slot 0 of SRQ validSRQ slot 0 valid", ++}, ++[ POWER8_PME_PM_LSU_SRQ_S39_ALLOC ] = { ++ .pme_name = "PM_LSU_SRQ_S39_ALLOC", ++ .pme_code = 0xf093, ++ .pme_short_desc = "SRQ slot 39 was released", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_SRQ_S39_VALID ] = { ++ .pme_name = "PM_LSU_SRQ_S39_VALID", ++ .pme_code = 0xf092, ++ .pme_short_desc = "SRQ slot 39 was busy", ++ .pme_long_desc = "SRQ slot 39 was busy42", ++}, ++[ POWER8_PME_PM_LSU_SRQ_SYNC ] = { ++ .pme_name = "PM_LSU_SRQ_SYNC", ++ .pme_code = 0xd09b, ++ .pme_short_desc = "A sync in the SRQ ended", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_LSU_SRQ_SYNC_CYC ] = { ++ .pme_name = "PM_LSU_SRQ_SYNC_CYC", ++ .pme_code = 0xd09a, ++ .pme_short_desc = "A sync is in the SRQ (edge detect to count)", ++ .pme_long_desc = "A sync is in the SRQ (edge detect to count)SRQ sync duration", ++}, ++[ POWER8_PME_PM_LSU_STORE_REJECT ] = { ++ .pme_name = "PM_LSU_STORE_REJECT", ++ .pme_code = 0xf084, ++ .pme_short_desc = "Store reject on either pipe", ++ .pme_long_desc = "LSU", ++}, ++[ POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { ++ .pme_name = "PM_LSU_TWO_TABLEWALK_CYC", ++ .pme_code = 0xd0a6, ++ .pme_short_desc = "Cycles when two tablewalks pending on this thread", ++ .pme_long_desc = "Cycles when two tablewalks pending on this thread42", ++}, ++[ POWER8_PME_PM_LWSYNC ] = { ++ .pme_name = "PM_LWSYNC", ++ .pme_code = 0x5094, ++ .pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", ++ .pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out", ++}, ++[ POWER8_PME_PM_LWSYNC_HELD ] = { ++ .pme_name = "PM_LWSYNC_HELD", ++ .pme_code = 0x209a, ++ .pme_short_desc = "LWSYNC held at dispatch", ++ .pme_long_desc = "LWSYNC held at dispatch", ++}, ++[ POWER8_PME_PM_MEM_CO ] = { ++ .pme_name = "PM_MEM_CO", ++ .pme_code = 0x4c058, ++ .pme_short_desc = "Memory castouts from this lpar", ++ .pme_long_desc = "Memory castouts from this lpar.", ++}, ++[ POWER8_PME_PM_MEM_LOC_THRESH_IFU ] = { ++ .pme_name = "PM_MEM_LOC_THRESH_IFU", ++ .pme_code = 0x10058, ++ .pme_short_desc = "Local Memory above threshold for IFU speculation control", ++ .pme_long_desc = "Local Memory above threshold for IFU speculation control.", ++}, ++[ POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = { ++ .pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH", ++ .pme_code = 0x40056, ++ .pme_short_desc = "Local memory above threshold for LSU medium", ++ .pme_long_desc = "Local memory above threshold for LSU medium.", ++}, ++[ POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED ] = { ++ .pme_name = "PM_MEM_LOC_THRESH_LSU_MED", ++ .pme_code = 0x1c05e, ++ .pme_short_desc = "Local memory above theshold for data prefetch", ++ .pme_long_desc = "Local memory above theshold for data prefetch.", ++}, ++[ POWER8_PME_PM_MEM_PREF ] = { ++ .pme_name = "PM_MEM_PREF", ++ .pme_code = 0x2c058, ++ .pme_short_desc = "Memory prefetch for this lpar. Includes L4", ++ .pme_long_desc = "Memory prefetch for this lpar.", ++}, ++[ POWER8_PME_PM_MEM_READ ] = { ++ .pme_name = "PM_MEM_READ", ++ .pme_code = 0x10056, ++ .pme_short_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4", ++ .pme_long_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch).", ++}, ++[ POWER8_PME_PM_MEM_RWITM ] = { ++ .pme_name = "PM_MEM_RWITM", ++ .pme_code = 0x3c05e, ++ .pme_short_desc = "Memory rwitm for this lpar", ++ .pme_long_desc = "Memory rwitm for this lpar.", ++}, ++[ POWER8_PME_PM_MRK_BACK_BR_CMPL ] = { ++ .pme_name = "PM_MRK_BACK_BR_CMPL", ++ .pme_code = 0x3515e, ++ .pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address", ++ .pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address.", ++}, ++[ POWER8_PME_PM_MRK_BRU_FIN ] = { ++ .pme_name = "PM_MRK_BRU_FIN", ++ .pme_code = 0x2013a, ++ .pme_short_desc = "bru marked instr finish", ++ .pme_long_desc = "bru marked instr finish.", ++}, ++[ POWER8_PME_PM_MRK_BR_CMPL ] = { ++ .pme_name = "PM_MRK_BR_CMPL", ++ .pme_code = 0x1016e, ++ .pme_short_desc = "Branch Instruction completed", ++ .pme_long_desc = "Branch Instruction completed.", ++}, ++[ POWER8_PME_PM_MRK_BR_MPRED_CMPL ] = { ++ .pme_name = "PM_MRK_BR_MPRED_CMPL", ++ .pme_code = 0x301e4, ++ .pme_short_desc = "Marked Branch Mispredicted", ++ .pme_long_desc = "Marked Branch Mispredicted.", ++}, ++[ POWER8_PME_PM_MRK_BR_TAKEN_CMPL ] = { ++ .pme_name = "PM_MRK_BR_TAKEN_CMPL", ++ .pme_code = 0x101e2, ++ .pme_short_desc = "Marked Branch Taken completed", ++ .pme_long_desc = "Marked Branch Taken.", ++}, ++[ POWER8_PME_PM_MRK_CRU_FIN ] = { ++ .pme_name = "PM_MRK_CRU_FIN", ++ .pme_code = 0x3013a, ++ .pme_short_desc = "IFU non-branch finished", ++ .pme_long_desc = "IFU non-branch marked instruction finished.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", ++ .pme_code = 0x4d148, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", ++ .pme_code = 0x2d128, ++ .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", ++ .pme_code = 0x3d148, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", ++ .pme_code = 0x2c128, ++ .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL4 ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL4", ++ .pme_code = 0x3d14c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DL4_CYC", ++ .pme_code = 0x2c12c, ++ .pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DMEM ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DMEM", ++ .pme_code = 0x4d14c, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_DMEM_CYC", ++ .pme_code = 0x2d12c, ++ .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_L2 ] = { + .pme_name = "PM_MRK_DATA_FROM_L2", + .pme_code = 0x1d142, + .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load", + .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L21_MOD", ++ .pme_code = 0x4d146, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC", ++ .pme_code = 0x2d126, ++ .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L21_SHR", ++ .pme_code = 0x3d146, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC", ++ .pme_code = 0x2c126, ++ .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2MISS", ++ .pme_code = 0x1d14e, ++ .pme_short_desc = "Data cache reload L2 miss", ++ .pme_long_desc = "Data cache reload L2 miss.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = { + .pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC", + .pme_code = 0x4c12e, +- .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load", +- .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load.", ++ .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load.", + }, + [ POWER8_PME_PM_MRK_DATA_FROM_L2_CYC ] = { + .pme_name = "PM_MRK_DATA_FROM_L2_CYC", +@@ -843,6 +5462,42 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load", + .pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x3d140, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", ++ .pme_code = 0x2c120, ++ .pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x4d140, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", ++ .pme_code = 0x2d120, ++ .pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_MEPF", ++ .pme_code = 0x2d140, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC", ++ .pme_code = 0x4d120, ++ .pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = { + .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT", + .pme_code = 0x1d140, +@@ -861,11 +5516,65 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load", + .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD", ++ .pme_code = 0x4d144, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC", ++ .pme_code = 0x2d124, ++ .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR", ++ .pme_code = 0x3d144, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC", ++ .pme_code = 0x2c124, ++ .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_MOD", ++ .pme_code = 0x2d144, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC", ++ .pme_code = 0x4d124, ++ .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_SHR", ++ .pme_code = 0x1d146, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC", ++ .pme_code = 0x4c126, ++ .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L3MISS", ++ .pme_code = 0x201e4, ++ .pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = { + .pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC", + .pme_code = 0x2d12e, +- .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load", +- .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load.", ++ .pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load.", + }, + [ POWER8_PME_PM_MRK_DATA_FROM_L3_CYC ] = { + .pme_name = "PM_MRK_DATA_FROM_L3_CYC", +@@ -873,6 +5582,30 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load", + .pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x3d142, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", ++ .pme_code = 0x2c122, ++ .pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L3_MEPF", ++ .pme_code = 0x2d142, ++ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC", ++ .pme_code = 0x4d122, ++ .pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = { + .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT", + .pme_code = 0x1d144, +@@ -909,6 +5642,12 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load", + .pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_MEM ] = { ++ .pme_name = "PM_MRK_DATA_FROM_MEM", ++ .pme_code = 0x201e0, ++ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.", ++}, + [ POWER8_PME_PM_MRK_DATA_FROM_MEMORY ] = { + .pme_name = "PM_MRK_DATA_FROM_MEMORY", + .pme_code = 0x2d14c, +@@ -921,42 +5660,750 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", + .pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load.", + }, ++[ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4d14a, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", ++ .pme_code = 0x2d12a, ++ .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x1d148, ++ .pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", ++ .pme_code = 0x4c128, ++ .pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", ++ .pme_code = 0x2d146, ++ .pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", ++ .pme_code = 0x4d126, ++ .pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", ++ .pme_code = 0x1d14a, ++ .pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", ++ .pme_code = 0x4c12a, ++ .pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL4 ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL4", ++ .pme_code = 0x2d14a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RL4_CYC", ++ .pme_code = 0x4d12a, ++ .pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RMEM ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RMEM", ++ .pme_code = 0x3d14a, ++ .pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", ++ .pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { ++ .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", ++ .pme_code = 0x2c12a, ++ .pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", ++ .pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load.", ++}, ++[ POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV ] = { ++ .pme_name = "PM_MRK_DCACHE_RELOAD_INTV", ++ .pme_code = 0x40118, ++ .pme_short_desc = "Combined Intervention event", ++ .pme_long_desc = "Combined Intervention event.", ++}, ++[ POWER8_PME_PM_MRK_DERAT_MISS ] = { ++ .pme_name = "PM_MRK_DERAT_MISS", ++ .pme_code = 0x301e6, ++ .pme_short_desc = "Erat Miss (TLB Access) All page sizes", ++ .pme_long_desc = "Erat Miss (TLB Access) All page sizes.", ++}, ++[ POWER8_PME_PM_MRK_DERAT_MISS_16G ] = { ++ .pme_name = "PM_MRK_DERAT_MISS_16G", ++ .pme_code = 0x4d154, ++ .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G", ++ .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G.", ++}, ++[ POWER8_PME_PM_MRK_DERAT_MISS_16M ] = { ++ .pme_name = "PM_MRK_DERAT_MISS_16M", ++ .pme_code = 0x3d154, ++ .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M", ++ .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M.", ++}, ++[ POWER8_PME_PM_MRK_DERAT_MISS_4K ] = { ++ .pme_name = "PM_MRK_DERAT_MISS_4K", ++ .pme_code = 0x1d156, ++ .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K", ++ .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K.", ++}, ++[ POWER8_PME_PM_MRK_DERAT_MISS_64K ] = { ++ .pme_name = "PM_MRK_DERAT_MISS_64K", ++ .pme_code = 0x2d154, ++ .pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K", ++ .pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K.", ++}, ++[ POWER8_PME_PM_MRK_DFU_FIN ] = { ++ .pme_name = "PM_MRK_DFU_FIN", ++ .pme_code = 0x20132, ++ .pme_short_desc = "Decimal Unit marked Instruction Finish", ++ .pme_long_desc = "Decimal Unit marked Instruction Finish.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD", ++ .pme_code = 0x4f148, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR", ++ .pme_code = 0x3f148, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_DL4 ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_DL4", ++ .pme_code = 0x3f14c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_DMEM ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_DMEM", ++ .pme_code = 0x4f14c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2 ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2", ++ .pme_code = 0x1f142, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L21_MOD", ++ .pme_code = 0x4f146, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L21_SHR", ++ .pme_code = 0x3f146, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2MISS", ++ .pme_code = 0x1f14e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST", ++ .pme_code = 0x3f140, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER", ++ .pme_code = 0x4f140, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF", ++ .pme_code = 0x2f140, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT", ++ .pme_code = 0x1f140, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L3 ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L3", ++ .pme_code = 0x4f142, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_MOD", ++ .pme_code = 0x4f144, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_SHR", ++ .pme_code = 0x3f144, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L31_MOD", ++ .pme_code = 0x2f144, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L31_SHR", ++ .pme_code = 0x1f146, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L3MISS", ++ .pme_code = 0x4f14e, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", ++ .pme_code = 0x3f142, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF", ++ .pme_code = 0x2f142, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT", ++ .pme_code = 0x1f144, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_LL4 ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_LL4", ++ .pme_code = 0x1f14c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_LMEM ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_LMEM", ++ .pme_code = 0x2f148, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_MEMORY", ++ .pme_code = 0x2f14c, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE", ++ .pme_code = 0x4f14a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", ++ .pme_code = 0x1f148, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD", ++ .pme_code = 0x2f146, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR", ++ .pme_code = 0x1f14a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_RL4 ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_RL4", ++ .pme_code = 0x2f14a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DPTEG_FROM_RMEM ] = { ++ .pme_name = "PM_MRK_DPTEG_FROM_RMEM", ++ .pme_code = 0x3f14a, ++ .pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request", ++ .pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request.", ++}, ++[ POWER8_PME_PM_MRK_DTLB_MISS ] = { ++ .pme_name = "PM_MRK_DTLB_MISS", ++ .pme_code = 0x401e4, ++ .pme_short_desc = "Marked dtlb miss", ++ .pme_long_desc = "Marked dtlb miss.", ++}, ++[ POWER8_PME_PM_MRK_DTLB_MISS_16G ] = { ++ .pme_name = "PM_MRK_DTLB_MISS_16G", ++ .pme_code = 0x1d158, ++ .pme_short_desc = "Marked Data TLB Miss page size 16G", ++ .pme_long_desc = "Marked Data TLB Miss page size 16G.", ++}, ++[ POWER8_PME_PM_MRK_DTLB_MISS_16M ] = { ++ .pme_name = "PM_MRK_DTLB_MISS_16M", ++ .pme_code = 0x4d156, ++ .pme_short_desc = "Marked Data TLB Miss page size 16M", ++ .pme_long_desc = "Marked Data TLB Miss page size 16M.", ++}, ++[ POWER8_PME_PM_MRK_DTLB_MISS_4K ] = { ++ .pme_name = "PM_MRK_DTLB_MISS_4K", ++ .pme_code = 0x2d156, ++ .pme_short_desc = "Marked Data TLB Miss page size 4k", ++ .pme_long_desc = "Marked Data TLB Miss page size 4k.", ++}, ++[ POWER8_PME_PM_MRK_DTLB_MISS_64K ] = { ++ .pme_name = "PM_MRK_DTLB_MISS_64K", ++ .pme_code = 0x3d156, ++ .pme_short_desc = "Marked Data TLB Miss page size 64K", ++ .pme_long_desc = "Marked Data TLB Miss page size 64K.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_BKILL ] = { ++ .pme_name = "PM_MRK_FAB_RSP_BKILL", ++ .pme_code = 0x40154, ++ .pme_short_desc = "Marked store had to do a bkill", ++ .pme_long_desc = "Marked store had to do a bkill.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = { ++ .pme_name = "PM_MRK_FAB_RSP_BKILL_CYC", ++ .pme_code = 0x2f150, ++ .pme_short_desc = "cycles L2 RC took for a bkill", ++ .pme_long_desc = "cycles L2 RC took for a bkill.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = { ++ .pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY", ++ .pme_code = 0x3015e, ++ .pme_short_desc = "Sampled store did a rwitm and got a rty", ++ .pme_long_desc = "Sampled store did a rwitm and got a rty.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM ] = { ++ .pme_name = "PM_MRK_FAB_RSP_DCLAIM", ++ .pme_code = 0x30154, ++ .pme_short_desc = "Marked store had to do a dclaim", ++ .pme_long_desc = "Marked store had to do a dclaim.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = { ++ .pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC", ++ .pme_code = 0x2f152, ++ .pme_short_desc = "cycles L2 RC took for a dclaim", ++ .pme_long_desc = "cycles L2 RC took for a dclaim.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_MATCH ] = { ++ .pme_name = "PM_MRK_FAB_RSP_MATCH", ++ .pme_code = 0x30156, ++ .pme_short_desc = "ttype and cresp matched as specified in MMCR1", ++ .pme_long_desc = "ttype and cresp matched as specified in MMCR1.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC ] = { ++ .pme_name = "PM_MRK_FAB_RSP_MATCH_CYC", ++ .pme_code = 0x4f152, ++ .pme_short_desc = "cresp/ttype match cycles", ++ .pme_long_desc = "cresp/ttype match cycles.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_RD_RTY ] = { ++ .pme_name = "PM_MRK_FAB_RSP_RD_RTY", ++ .pme_code = 0x4015e, ++ .pme_short_desc = "Sampled L2 reads retry count", ++ .pme_long_desc = "Sampled L2 reads retry count.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = { ++ .pme_name = "PM_MRK_FAB_RSP_RD_T_INTV", ++ .pme_code = 0x1015e, ++ .pme_short_desc = "Sampled Read got a T intervention", ++ .pme_long_desc = "Sampled Read got a T intervention.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = { ++ .pme_name = "PM_MRK_FAB_RSP_RWITM_CYC", ++ .pme_code = 0x4f150, ++ .pme_short_desc = "cycles L2 RC took for a rwitm", ++ .pme_long_desc = "cycles L2 RC took for a rwitm.", ++}, ++[ POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = { ++ .pme_name = "PM_MRK_FAB_RSP_RWITM_RTY", ++ .pme_code = 0x2015e, ++ .pme_short_desc = "Sampled store did a rwitm and got a rty", ++ .pme_long_desc = "Sampled store did a rwitm and got a rty.", ++}, ++[ POWER8_PME_PM_MRK_FILT_MATCH ] = { ++ .pme_name = "PM_MRK_FILT_MATCH", ++ .pme_code = 0x2013c, ++ .pme_short_desc = "Marked filter Match", ++ .pme_long_desc = "Marked filter Match.", ++}, ++[ POWER8_PME_PM_MRK_FIN_STALL_CYC ] = { ++ .pme_name = "PM_MRK_FIN_STALL_CYC", ++ .pme_code = 0x1013c, ++ .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count )", ++ .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #).", ++}, ++[ POWER8_PME_PM_MRK_FXU_FIN ] = { ++ .pme_name = "PM_MRK_FXU_FIN", ++ .pme_code = 0x20134, ++ .pme_short_desc = "fxu marked instr finish", ++ .pme_long_desc = "fxu marked instr finish.", ++}, + [ POWER8_PME_PM_MRK_GRP_CMPL ] = { + .pme_name = "PM_MRK_GRP_CMPL", + .pme_code = 0x40130, + .pme_short_desc = "marked instruction finished (completed)", + .pme_long_desc = "marked instruction finished (completed).", + }, ++[ POWER8_PME_PM_MRK_GRP_IC_MISS ] = { ++ .pme_name = "PM_MRK_GRP_IC_MISS", ++ .pme_code = 0x4013a, ++ .pme_short_desc = "Marked Group experienced I cache miss", ++ .pme_long_desc = "Marked Group experienced I cache miss.", ++}, ++[ POWER8_PME_PM_MRK_GRP_NTC ] = { ++ .pme_name = "PM_MRK_GRP_NTC", ++ .pme_code = 0x3013c, ++ .pme_short_desc = "Marked group ntc cycles.", ++ .pme_long_desc = "Marked group ntc cycles.", ++}, ++[ POWER8_PME_PM_MRK_INST_CMPL ] = { ++ .pme_name = "PM_MRK_INST_CMPL", ++ .pme_code = 0x401e0, ++ .pme_short_desc = "marked instruction completed", ++ .pme_long_desc = "marked instruction completed.", ++}, + [ POWER8_PME_PM_MRK_INST_DECODED ] = { + .pme_name = "PM_MRK_INST_DECODED", + .pme_code = 0x20130, + .pme_short_desc = "marked instruction decoded", + .pme_long_desc = "marked instruction decoded. Name from ISU?", + }, ++[ POWER8_PME_PM_MRK_INST_DISP ] = { ++ .pme_name = "PM_MRK_INST_DISP", ++ .pme_code = 0x101e0, ++ .pme_short_desc = "The thread has dispatched a randomly sampled marked instruction", ++ .pme_long_desc = "Marked Instruction dispatched.", ++}, ++[ POWER8_PME_PM_MRK_INST_FIN ] = { ++ .pme_name = "PM_MRK_INST_FIN", ++ .pme_code = 0x30130, ++ .pme_short_desc = "marked instruction finished", ++ .pme_long_desc = "marked instr finish any unit .", ++}, ++[ POWER8_PME_PM_MRK_INST_FROM_L3MISS ] = { ++ .pme_name = "PM_MRK_INST_FROM_L3MISS", ++ .pme_code = 0x401e6, ++ .pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet", ++ .pme_long_desc = "n/a", ++}, ++[ POWER8_PME_PM_MRK_INST_ISSUED ] = { ++ .pme_name = "PM_MRK_INST_ISSUED", ++ .pme_code = 0x10132, ++ .pme_short_desc = "Marked instruction issued", ++ .pme_long_desc = "Marked instruction issued.", ++}, ++[ POWER8_PME_PM_MRK_INST_TIMEO ] = { ++ .pme_name = "PM_MRK_INST_TIMEO", ++ .pme_code = 0x40134, ++ .pme_short_desc = "marked Instruction finish timeout (instruction lost)", ++ .pme_long_desc = "marked Instruction finish timeout (instruction lost).", ++}, ++[ POWER8_PME_PM_MRK_L1_ICACHE_MISS ] = { ++ .pme_name = "PM_MRK_L1_ICACHE_MISS", ++ .pme_code = 0x101e4, ++ .pme_short_desc = "sampled Instruction suffered an icache Miss", ++ .pme_long_desc = "Marked L1 Icache Miss.", ++}, ++[ POWER8_PME_PM_MRK_L1_RELOAD_VALID ] = { ++ .pme_name = "PM_MRK_L1_RELOAD_VALID", ++ .pme_code = 0x101ea, ++ .pme_short_desc = "Marked demand reload", ++ .pme_long_desc = "Marked demand reload.", ++}, + [ POWER8_PME_PM_MRK_L2_RC_DISP ] = { + .pme_name = "PM_MRK_L2_RC_DISP", + .pme_code = 0x20114, + .pme_short_desc = "Marked Instruction RC dispatched in L2", + .pme_long_desc = "Marked Instruction RC dispatched in L2.", + }, ++[ POWER8_PME_PM_MRK_L2_RC_DONE ] = { ++ .pme_name = "PM_MRK_L2_RC_DONE", ++ .pme_code = 0x3012a, ++ .pme_short_desc = "Marked RC done", ++ .pme_long_desc = "Marked RC done.", ++}, ++[ POWER8_PME_PM_MRK_LARX_FIN ] = { ++ .pme_name = "PM_MRK_LARX_FIN", ++ .pme_code = 0x40116, ++ .pme_short_desc = "Larx finished", ++ .pme_long_desc = "Larx finished .", ++}, ++[ POWER8_PME_PM_MRK_LD_MISS_EXPOSED ] = { ++ .pme_name = "PM_MRK_LD_MISS_EXPOSED", ++ .pme_code = 0x1013f, ++ .pme_short_desc = "Marked Load exposed Miss (exposed period ended)", ++ .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)", ++}, ++[ POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { ++ .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC", ++ .pme_code = 0x1013e, ++ .pme_short_desc = "Marked Load exposed Miss cycles", ++ .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #).", ++}, ++[ POWER8_PME_PM_MRK_LD_MISS_L1 ] = { ++ .pme_name = "PM_MRK_LD_MISS_L1", ++ .pme_code = 0x201e2, ++ .pme_short_desc = "Marked DL1 Demand Miss counted at exec time", ++ .pme_long_desc = "Marked DL1 Demand Miss counted at exec time.", ++}, + [ POWER8_PME_PM_MRK_LD_MISS_L1_CYC ] = { + .pme_name = "PM_MRK_LD_MISS_L1_CYC", + .pme_code = 0x4013e, + .pme_short_desc = "Marked ld latency", + .pme_long_desc = "Marked ld latency.", + }, ++[ POWER8_PME_PM_MRK_LSU_FIN ] = { ++ .pme_name = "PM_MRK_LSU_FIN", ++ .pme_code = 0x40132, ++ .pme_short_desc = "lsu marked instr finish", ++ .pme_long_desc = "lsu marked instr finish.", ++}, ++[ POWER8_PME_PM_MRK_LSU_FLUSH ] = { ++ .pme_name = "PM_MRK_LSU_FLUSH", ++ .pme_code = 0xd180, ++ .pme_short_desc = "Flush: (marked) : All Cases", ++ .pme_long_desc = "Flush: (marked) : All Cases42", ++}, ++[ POWER8_PME_PM_MRK_LSU_FLUSH_LRQ ] = { ++ .pme_name = "PM_MRK_LSU_FLUSH_LRQ", ++ .pme_code = 0xd188, ++ .pme_short_desc = "Flush: (marked) LRQ", ++ .pme_long_desc = "Flush: (marked) LRQMarked LRQ flushes", ++}, ++[ POWER8_PME_PM_MRK_LSU_FLUSH_SRQ ] = { ++ .pme_name = "PM_MRK_LSU_FLUSH_SRQ", ++ .pme_code = 0xd18a, ++ .pme_short_desc = "Flush: (marked) SRQ", ++ .pme_long_desc = "Flush: (marked) SRQMarked SRQ lhs flushes", ++}, ++[ POWER8_PME_PM_MRK_LSU_FLUSH_ULD ] = { ++ .pme_name = "PM_MRK_LSU_FLUSH_ULD", ++ .pme_code = 0xd184, ++ .pme_short_desc = "Flush: (marked) Unaligned Load", ++ .pme_long_desc = "Flush: (marked) Unaligned LoadMarked unaligned load flushes", ++}, ++[ POWER8_PME_PM_MRK_LSU_FLUSH_UST ] = { ++ .pme_name = "PM_MRK_LSU_FLUSH_UST", ++ .pme_code = 0xd186, ++ .pme_short_desc = "Flush: (marked) Unaligned Store", ++ .pme_long_desc = "Flush: (marked) Unaligned StoreMarked unaligned store flushes", ++}, ++[ POWER8_PME_PM_MRK_LSU_REJECT ] = { ++ .pme_name = "PM_MRK_LSU_REJECT", ++ .pme_code = 0x40164, ++ .pme_short_desc = "LSU marked reject (up to 2 per cycle)", ++ .pme_long_desc = "LSU marked reject (up to 2 per cycle).", ++}, ++[ POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { ++ .pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS", ++ .pme_code = 0x30164, ++ .pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", ++ .pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle).", ++}, ++[ POWER8_PME_PM_MRK_NTF_FIN ] = { ++ .pme_name = "PM_MRK_NTF_FIN", ++ .pme_code = 0x20112, ++ .pme_short_desc = "Marked next to finish instruction finished", ++ .pme_long_desc = "Marked next to finish instruction finished.", ++}, ++[ POWER8_PME_PM_MRK_RUN_CYC ] = { ++ .pme_name = "PM_MRK_RUN_CYC", ++ .pme_code = 0x1d15e, ++ .pme_short_desc = "Marked run cycles", ++ .pme_long_desc = "Marked run cycles.", ++}, ++[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF ] = { ++ .pme_name = "PM_MRK_SRC_PREF_TRACK_EFF", ++ .pme_code = 0x1d15a, ++ .pme_short_desc = "Marked src pref track was effective", ++ .pme_long_desc = "Marked src pref track was effective.", ++}, ++[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF ] = { ++ .pme_name = "PM_MRK_SRC_PREF_TRACK_INEFF", ++ .pme_code = 0x3d15a, ++ .pme_short_desc = "Prefetch tracked was ineffective for marked src", ++ .pme_long_desc = "Prefetch tracked was ineffective for marked src.", ++}, ++[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD ] = { ++ .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD", ++ .pme_code = 0x4d15c, ++ .pme_short_desc = "Prefetch tracked was moderate for marked src", ++ .pme_long_desc = "Prefetch tracked was moderate for marked src.", ++}, ++[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 ] = { ++ .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L2", ++ .pme_code = 0x1d15c, ++ .pme_short_desc = "Marked src Prefetch Tracked was moderate (source L2)", ++ .pme_long_desc = "Marked src Prefetch Tracked was moderate (source L2).", ++}, ++[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 ] = { ++ .pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L3", ++ .pme_code = 0x3d15c, ++ .pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked src", ++ .pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked src.", ++}, + [ POWER8_PME_PM_MRK_STALL_CMPLU_CYC ] = { + .pme_name = "PM_MRK_STALL_CMPLU_CYC", + .pme_code = 0x3013e, + .pme_short_desc = "Marked Group completion Stall", +- .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count).", ++ .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #).", ++}, ++[ POWER8_PME_PM_MRK_STCX_FAIL ] = { ++ .pme_name = "PM_MRK_STCX_FAIL", ++ .pme_code = 0x3e158, ++ .pme_short_desc = "marked stcx failed", ++ .pme_long_desc = "marked stcx failed.", ++}, ++[ POWER8_PME_PM_MRK_ST_CMPL ] = { ++ .pme_name = "PM_MRK_ST_CMPL", ++ .pme_code = 0x10134, ++ .pme_short_desc = "marked store completed and sent to nest", ++ .pme_long_desc = "Marked store completed.", ++}, ++[ POWER8_PME_PM_MRK_ST_CMPL_INT ] = { ++ .pme_name = "PM_MRK_ST_CMPL_INT", ++ .pme_code = 0x30134, ++ .pme_short_desc = "marked store finished with intervention", ++ .pme_long_desc = "marked store complete (data home) with intervention.", ++}, ++[ POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = { ++ .pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", ++ .pme_code = 0x3f150, ++ .pme_short_desc = "cycles to drain st from core to L2", ++ .pme_long_desc = "cycles to drain st from core to L2.", ++}, ++[ POWER8_PME_PM_MRK_ST_FWD ] = { ++ .pme_name = "PM_MRK_ST_FWD", ++ .pme_code = 0x3012c, ++ .pme_short_desc = "Marked st forwards", ++ .pme_long_desc = "Marked st forwards.", ++}, ++[ POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = { ++ .pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC", ++ .pme_code = 0x1f150, ++ .pme_short_desc = "cycles from L2 rc disp to l2 rc completion", ++ .pme_long_desc = "cycles from L2 rc disp to l2 rc completion.", ++}, ++[ POWER8_PME_PM_MRK_ST_NEST ] = { ++ .pme_name = "PM_MRK_ST_NEST", ++ .pme_code = 0x20138, ++ .pme_short_desc = "Marked store sent to nest", ++ .pme_long_desc = "Marked store sent to nest.", ++}, ++[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF ] = { ++ .pme_name = "PM_MRK_TGT_PREF_TRACK_EFF", ++ .pme_code = 0x1c15a, ++ .pme_short_desc = "Marked target pref track was effective", ++ .pme_long_desc = "Marked target pref track was effective.", ++}, ++[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF ] = { ++ .pme_name = "PM_MRK_TGT_PREF_TRACK_INEFF", ++ .pme_code = 0x3c15a, ++ .pme_short_desc = "Prefetch tracked was ineffective for marked target", ++ .pme_long_desc = "Prefetch tracked was ineffective for marked target.", ++}, ++[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD ] = { ++ .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD", ++ .pme_code = 0x4c15c, ++ .pme_short_desc = "Prefetch tracked was moderate for marked target", ++ .pme_long_desc = "Prefetch tracked was moderate for marked target.", ++}, ++[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 ] = { ++ .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L2", ++ .pme_code = 0x1c15c, ++ .pme_short_desc = "Marked target Prefetch Tracked was moderate (source L2)", ++ .pme_long_desc = "Marked target Prefetch Tracked was moderate (source L2).", ++}, ++[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 ] = { ++ .pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L3", ++ .pme_code = 0x3c15c, ++ .pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked target", ++ .pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked target.", ++}, ++[ POWER8_PME_PM_MRK_VSU_FIN ] = { ++ .pme_name = "PM_MRK_VSU_FIN", ++ .pme_code = 0x30132, ++ .pme_short_desc = "VSU marked instr finish", ++ .pme_long_desc = "vsu (fpu) marked instr finish.", ++}, ++[ POWER8_PME_PM_MULT_MRK ] = { ++ .pme_name = "PM_MULT_MRK", ++ .pme_code = 0x3d15e, ++ .pme_short_desc = "mult marked instr", ++ .pme_long_desc = "mult marked instr.", ++}, ++[ POWER8_PME_PM_NESTED_TEND ] = { ++ .pme_name = "PM_NESTED_TEND", ++ .pme_code = 0x20b0, ++ .pme_short_desc = "Completion time nested tend", ++ .pme_long_desc = "Completion time nested tend", + }, + [ POWER8_PME_PM_NEST_REF_CLK ] = { + .pme_name = "PM_NEST_REF_CLK", + .pme_code = 0x3006e, +- .pme_short_desc = "Nest reference clocks", ++ .pme_short_desc = "Multiply by 4 to obtain the number of PB cycles", + .pme_long_desc = "Nest reference clocks.", + }, ++[ POWER8_PME_PM_NON_FAV_TBEGIN ] = { ++ .pme_name = "PM_NON_FAV_TBEGIN", ++ .pme_code = 0x20b6, ++ .pme_short_desc = "Dispatch time non favored tbegin", ++ .pme_long_desc = "Dispatch time non favored tbegin", ++}, ++[ POWER8_PME_PM_NON_TM_RST_SC ] = { ++ .pme_name = "PM_NON_TM_RST_SC", ++ .pme_code = 0x328084, ++ .pme_short_desc = "non tm snp rst tm sc", ++ .pme_long_desc = "non tm snp rst tm sc", ++}, ++[ POWER8_PME_PM_NTCG_ALL_FIN ] = { ++ .pme_name = "PM_NTCG_ALL_FIN", ++ .pme_code = 0x2001a, ++ .pme_short_desc = "Cycles after all instructions have finished to group completed", ++ .pme_long_desc = "Ccycles after all instructions have finished to group completed.", ++}, ++[ POWER8_PME_PM_OUTER_TBEGIN ] = { ++ .pme_name = "PM_OUTER_TBEGIN", ++ .pme_code = 0x20ac, ++ .pme_short_desc = "Completion time outer tbegin", ++ .pme_long_desc = "Completion time outer tbegin", ++}, ++[ POWER8_PME_PM_OUTER_TEND ] = { ++ .pme_name = "PM_OUTER_TEND", ++ .pme_code = 0x20ae, ++ .pme_short_desc = "Completion time outer tend", ++ .pme_long_desc = "Completion time outer tend", ++}, + [ POWER8_PME_PM_PMC1_OVERFLOW ] = { + .pme_name = "PM_PMC1_OVERFLOW", + .pme_code = 0x20010, +@@ -969,6 +6416,18 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Overflow from counter 2", + .pme_long_desc = "Overflow from counter 2.", + }, ++[ POWER8_PME_PM_PMC2_REWIND ] = { ++ .pme_name = "PM_PMC2_REWIND", ++ .pme_code = 0x30020, ++ .pme_short_desc = "PMC2 Rewind Event (did not match condition)", ++ .pme_long_desc = "PMC2 Rewind Event (did not match condition).", ++}, ++[ POWER8_PME_PM_PMC2_SAVED ] = { ++ .pme_name = "PM_PMC2_SAVED", ++ .pme_code = 0x10022, ++ .pme_short_desc = "PMC2 Rewind Value saved", ++ .pme_long_desc = "PMC2 Rewind Value saved (matched condition).", ++}, + [ POWER8_PME_PM_PMC3_OVERFLOW ] = { + .pme_name = "PM_PMC3_OVERFLOW", + .pme_code = 0x40010, +@@ -981,17 +6440,443 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "Overflow from counter 4", + .pme_long_desc = "Overflow from counter 4.", + }, ++[ POWER8_PME_PM_PMC4_REWIND ] = { ++ .pme_name = "PM_PMC4_REWIND", ++ .pme_code = 0x10020, ++ .pme_short_desc = "PMC4 Rewind Event", ++ .pme_long_desc = "PMC4 Rewind Event (did not match condition).", ++}, ++[ POWER8_PME_PM_PMC4_SAVED ] = { ++ .pme_name = "PM_PMC4_SAVED", ++ .pme_code = 0x30022, ++ .pme_short_desc = "PMC4 Rewind Value saved (matched condition)", ++ .pme_long_desc = "PMC4 Rewind Value saved (matched condition).", ++}, ++[ POWER8_PME_PM_PMC5_OVERFLOW ] = { ++ .pme_name = "PM_PMC5_OVERFLOW", ++ .pme_code = 0x10024, ++ .pme_short_desc = "Overflow from counter 5", ++ .pme_long_desc = "Overflow from counter 5.", ++}, + [ POWER8_PME_PM_PMC6_OVERFLOW ] = { + .pme_name = "PM_PMC6_OVERFLOW", + .pme_code = 0x30024, + .pme_short_desc = "Overflow from counter 6", + .pme_long_desc = "Overflow from counter 6.", + }, +-[ POWER8_PME_PM_PPC_CMPL ] = { +- .pme_name = "PM_PPC_CMPL", +- .pme_code = 0x40002, +- .pme_short_desc = "PPC Instructions Finished (completed)", +- .pme_long_desc = "PPC Instructions Finished (completed).", ++[ POWER8_PME_PM_PREF_TRACKED ] = { ++ .pme_name = "PM_PREF_TRACKED", ++ .pme_code = 0x2005a, ++ .pme_short_desc = "Total number of Prefetch Operations that were tracked", ++ .pme_long_desc = "Total number of Prefetch Operations that were tracked.", ++}, ++[ POWER8_PME_PM_PREF_TRACK_EFF ] = { ++ .pme_name = "PM_PREF_TRACK_EFF", ++ .pme_code = 0x1005a, ++ .pme_short_desc = "Prefetch Tracked was effective", ++ .pme_long_desc = "Prefetch Tracked was effective.", ++}, ++[ POWER8_PME_PM_PREF_TRACK_INEFF ] = { ++ .pme_name = "PM_PREF_TRACK_INEFF", ++ .pme_code = 0x3005a, ++ .pme_short_desc = "Prefetch tracked was ineffective", ++ .pme_long_desc = "Prefetch tracked was ineffective.", ++}, ++[ POWER8_PME_PM_PREF_TRACK_MOD ] = { ++ .pme_name = "PM_PREF_TRACK_MOD", ++ .pme_code = 0x4005a, ++ .pme_short_desc = "Prefetch tracked was moderate", ++ .pme_long_desc = "Prefetch tracked was moderate.", ++}, ++[ POWER8_PME_PM_PREF_TRACK_MOD_L2 ] = { ++ .pme_name = "PM_PREF_TRACK_MOD_L2", ++ .pme_code = 0x1005c, ++ .pme_short_desc = "Prefetch Tracked was moderate (source L2)", ++ .pme_long_desc = "Prefetch Tracked was moderate (source L2).", ++}, ++[ POWER8_PME_PM_PREF_TRACK_MOD_L3 ] = { ++ .pme_name = "PM_PREF_TRACK_MOD_L3", ++ .pme_code = 0x3005c, ++ .pme_short_desc = "Prefetch tracked was moderate (L3)", ++ .pme_long_desc = "Prefetch tracked was moderate (L3).", ++}, ++[ POWER8_PME_PM_PROBE_NOP_DISP ] = { ++ .pme_name = "PM_PROBE_NOP_DISP", ++ .pme_code = 0x40014, ++ .pme_short_desc = "ProbeNops dispatched", ++ .pme_long_desc = "ProbeNops dispatched.", ++}, ++[ POWER8_PME_PM_PTE_PREFETCH ] = { ++ .pme_name = "PM_PTE_PREFETCH", ++ .pme_code = 0xe084, ++ .pme_short_desc = "PTE prefetches", ++ .pme_long_desc = "PTE prefetches42", ++}, ++[ POWER8_PME_PM_PUMP_CPRED ] = { ++ .pme_name = "PM_PUMP_CPRED", ++ .pme_code = 0x10054, ++ .pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_PUMP_MPRED ] = { ++ .pme_name = "PM_PUMP_MPRED", ++ .pme_code = 0x40052, ++ .pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_RC0_ALLOC ] = { ++ .pme_name = "PM_RC0_ALLOC", ++ .pme_code = 0x16081, ++ .pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_RC0_BUSY ] = { ++ .pme_name = "PM_RC0_BUSY", ++ .pme_code = 0x16080, ++ .pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++}, ++[ POWER8_PME_PM_RC_LIFETIME_EXC_1024 ] = { ++ .pme_name = "PM_RC_LIFETIME_EXC_1024", ++ .pme_code = 0x200301ea, ++ .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 1024 cycles", ++ .pme_long_desc = "Reload latency exceeded 1024 cyc", ++}, ++[ POWER8_PME_PM_RC_LIFETIME_EXC_2048 ] = { ++ .pme_name = "PM_RC_LIFETIME_EXC_2048", ++ .pme_code = 0x200401ec, ++ .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 2048 cycles", ++ .pme_long_desc = "Threshold counter exceeded a value of 2048", ++}, ++[ POWER8_PME_PM_RC_LIFETIME_EXC_256 ] = { ++ .pme_name = "PM_RC_LIFETIME_EXC_256", ++ .pme_code = 0x200101e8, ++ .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 256 cycles", ++ .pme_long_desc = "Threshold counter exceed a count of 256", ++}, ++[ POWER8_PME_PM_RC_LIFETIME_EXC_32 ] = { ++ .pme_name = "PM_RC_LIFETIME_EXC_32", ++ .pme_code = 0x200201e6, ++ .pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 32 cycles", ++ .pme_long_desc = "Reload latency exceeded 32 cyc", ++}, ++[ POWER8_PME_PM_RC_USAGE ] = { ++ .pme_name = "PM_RC_USAGE", ++ .pme_code = 0x36088, ++ .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++ .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++}, ++[ POWER8_PME_PM_RD_CLEARING_SC ] = { ++ .pme_name = "PM_RD_CLEARING_SC", ++ .pme_code = 0x34808e, ++ .pme_short_desc = "rd clearing sc", ++ .pme_long_desc = "rd clearing sc", ++}, ++[ POWER8_PME_PM_RD_FORMING_SC ] = { ++ .pme_name = "PM_RD_FORMING_SC", ++ .pme_code = 0x34808c, ++ .pme_short_desc = "rd forming sc", ++ .pme_long_desc = "rd forming sc", ++}, ++[ POWER8_PME_PM_RD_HIT_PF ] = { ++ .pme_name = "PM_RD_HIT_PF", ++ .pme_code = 0x428086, ++ .pme_short_desc = "rd machine hit l3 pf machine", ++ .pme_long_desc = "rd machine hit l3 pf machine", ++}, ++[ POWER8_PME_PM_REAL_SRQ_FULL ] = { ++ .pme_name = "PM_REAL_SRQ_FULL", ++ .pme_code = 0x20004, ++ .pme_short_desc = "Out of real srq entries", ++ .pme_long_desc = "Out of real srq entries.", ++}, ++[ POWER8_PME_PM_RUN_CYC ] = { ++ .pme_name = "PM_RUN_CYC", ++ .pme_code = 0x600f4, ++ .pme_short_desc = "Run_cycles", ++ .pme_long_desc = "Run_cycles.", ++}, ++[ POWER8_PME_PM_RUN_CYC_SMT2_MODE ] = { ++ .pme_name = "PM_RUN_CYC_SMT2_MODE", ++ .pme_code = 0x3006c, ++ .pme_short_desc = "Cycles run latch is set and core is in SMT2 mode", ++ .pme_long_desc = "Cycles run latch is set and core is in SMT2 mode.", ++}, ++[ POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE ] = { ++ .pme_name = "PM_RUN_CYC_SMT2_SHRD_MODE", ++ .pme_code = 0x2006a, ++ .pme_short_desc = "cycles this threads run latch is set and the core is in SMT2 shared mode", ++ .pme_long_desc = "Cycles run latch is set and core is in SMT2-shared mode.", ++}, ++[ POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE ] = { ++ .pme_name = "PM_RUN_CYC_SMT2_SPLIT_MODE", ++ .pme_code = 0x1006a, ++ .pme_short_desc = "Cycles run latch is set and core is in SMT2-split mode", ++ .pme_long_desc = "Cycles run latch is set and core is in SMT2-split mode.", ++}, ++[ POWER8_PME_PM_RUN_CYC_SMT4_MODE ] = { ++ .pme_name = "PM_RUN_CYC_SMT4_MODE", ++ .pme_code = 0x2006c, ++ .pme_short_desc = "cycles this threads run latch is set and the core is in SMT4 mode", ++ .pme_long_desc = "Cycles run latch is set and core is in SMT4 mode.", ++}, ++[ POWER8_PME_PM_RUN_CYC_SMT8_MODE ] = { ++ .pme_name = "PM_RUN_CYC_SMT8_MODE", ++ .pme_code = 0x4006c, ++ .pme_short_desc = "Cycles run latch is set and core is in SMT8 mode", ++ .pme_long_desc = "Cycles run latch is set and core is in SMT8 mode.", ++}, ++[ POWER8_PME_PM_RUN_CYC_ST_MODE ] = { ++ .pme_name = "PM_RUN_CYC_ST_MODE", ++ .pme_code = 0x1006c, ++ .pme_short_desc = "Cycles run latch is set and core is in ST mode", ++ .pme_long_desc = "Cycles run latch is set and core is in ST mode.", ++}, ++[ POWER8_PME_PM_RUN_INST_CMPL ] = { ++ .pme_name = "PM_RUN_INST_CMPL", ++ .pme_code = 0x500fa, ++ .pme_short_desc = "Run_Instructions", ++ .pme_long_desc = "Run_Instructions.", ++}, ++[ POWER8_PME_PM_RUN_PURR ] = { ++ .pme_name = "PM_RUN_PURR", ++ .pme_code = 0x400f4, ++ .pme_short_desc = "Run_PURR", ++ .pme_long_desc = "Run_PURR.", ++}, ++[ POWER8_PME_PM_RUN_SPURR ] = { ++ .pme_name = "PM_RUN_SPURR", ++ .pme_code = 0x10008, ++ .pme_short_desc = "Run SPURR", ++ .pme_long_desc = "Run SPURR.", ++}, ++[ POWER8_PME_PM_SEC_ERAT_HIT ] = { ++ .pme_name = "PM_SEC_ERAT_HIT", ++ .pme_code = 0xf082, ++ .pme_short_desc = "secondary ERAT Hit", ++ .pme_long_desc = "secondary ERAT Hit42", ++}, ++[ POWER8_PME_PM_SHL_CREATED ] = { ++ .pme_name = "PM_SHL_CREATED", ++ .pme_code = 0x508c, ++ .pme_short_desc = "Store-Hit-Load Table Entry Created", ++ .pme_long_desc = "Store-Hit-Load Table Entry Created", ++}, ++[ POWER8_PME_PM_SHL_ST_CONVERT ] = { ++ .pme_name = "PM_SHL_ST_CONVERT", ++ .pme_code = 0x508e, ++ .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled", ++ .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled", ++}, ++[ POWER8_PME_PM_SHL_ST_DISABLE ] = { ++ .pme_name = "PM_SHL_ST_DISABLE", ++ .pme_code = 0x5090, ++ .pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", ++ .pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)", ++}, ++[ POWER8_PME_PM_SN0_ALLOC ] = { ++ .pme_name = "PM_SN0_ALLOC", ++ .pme_code = 0x26085, ++ .pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "0.0", ++}, ++[ POWER8_PME_PM_SN0_BUSY ] = { ++ .pme_name = "PM_SN0_BUSY", ++ .pme_code = 0x26084, ++ .pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++ .pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)", ++}, ++[ POWER8_PME_PM_SNOOP_TLBIE ] = { ++ .pme_name = "PM_SNOOP_TLBIE", ++ .pme_code = 0xd0b2, ++ .pme_short_desc = "TLBIE snoop", ++ .pme_long_desc = "TLBIE snoopSnoop TLBIE", ++}, ++[ POWER8_PME_PM_SNP_TM_HIT_M ] = { ++ .pme_name = "PM_SNP_TM_HIT_M", ++ .pme_code = 0x338088, ++ .pme_short_desc = "snp tm st hit m mu", ++ .pme_long_desc = "snp tm st hit m mu", ++}, ++[ POWER8_PME_PM_SNP_TM_HIT_T ] = { ++ .pme_name = "PM_SNP_TM_HIT_T", ++ .pme_code = 0x33808a, ++ .pme_short_desc = "snp tm_st_hit t tn te", ++ .pme_long_desc = "snp tm_st_hit t tn te", ++}, ++[ POWER8_PME_PM_SN_USAGE ] = { ++ .pme_name = "PM_SN_USAGE", ++ .pme_code = 0x4608c, ++ .pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++ .pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running", ++}, ++[ POWER8_PME_PM_STALL_END_GCT_EMPTY ] = { ++ .pme_name = "PM_STALL_END_GCT_EMPTY", ++ .pme_code = 0x10028, ++ .pme_short_desc = "Count ended because GCT went empty", ++ .pme_long_desc = "Count ended because GCT went empty.", ++}, ++[ POWER8_PME_PM_STCX_FAIL ] = { ++ .pme_name = "PM_STCX_FAIL", ++ .pme_code = 0x1e058, ++ .pme_short_desc = "stcx failed", ++ .pme_long_desc = "stcx failed .", ++}, ++[ POWER8_PME_PM_STCX_LSU ] = { ++ .pme_name = "PM_STCX_LSU", ++ .pme_code = 0xc090, ++ .pme_short_desc = "STCX executed reported at sent to nest", ++ .pme_long_desc = "STCX executed reported at sent to nest42", ++}, ++[ POWER8_PME_PM_ST_CAUSED_FAIL ] = { ++ .pme_name = "PM_ST_CAUSED_FAIL", ++ .pme_code = 0x717080, ++ .pme_short_desc = "Non TM St caused any thread to fail", ++ .pme_long_desc = "Non TM St caused any thread to fail", ++}, ++[ POWER8_PME_PM_ST_CMPL ] = { ++ .pme_name = "PM_ST_CMPL", ++ .pme_code = 0x20016, ++ .pme_short_desc = "Store completion count", ++ .pme_long_desc = "Store completion count.", ++}, ++[ POWER8_PME_PM_ST_FIN ] = { ++ .pme_name = "PM_ST_FIN", ++ .pme_code = 0x200f0, ++ .pme_short_desc = "Store Instructions Finished", ++ .pme_long_desc = "Store Instructions Finished (store sent to nest).", ++}, ++[ POWER8_PME_PM_ST_FWD ] = { ++ .pme_name = "PM_ST_FWD", ++ .pme_code = 0x20018, ++ .pme_short_desc = "Store forwards that finished", ++ .pme_long_desc = "Store forwards that finished.", ++}, ++[ POWER8_PME_PM_ST_MISS_L1 ] = { ++ .pme_name = "PM_ST_MISS_L1", ++ .pme_code = 0x300f0, ++ .pme_short_desc = "Store Missed L1", ++ .pme_long_desc = "Store Missed L1.", ++}, ++[ POWER8_PME_PM_SUSPENDED ] = { ++ .pme_name = "PM_SUSPENDED", ++ .pme_code = 0x0, ++ .pme_short_desc = "Counter OFF", ++ .pme_long_desc = "Counter OFF.", ++}, ++[ POWER8_PME_PM_SWAP_CANCEL ] = { ++ .pme_name = "PM_SWAP_CANCEL", ++ .pme_code = 0x3090, ++ .pme_short_desc = "SWAP cancel , rtag not available", ++ .pme_long_desc = "SWAP cancel , rtag not available", ++}, ++[ POWER8_PME_PM_SWAP_CANCEL_GPR ] = { ++ .pme_name = "PM_SWAP_CANCEL_GPR", ++ .pme_code = 0x3092, ++ .pme_short_desc = "SWAP cancel , rtag not available for gpr", ++ .pme_long_desc = "SWAP cancel , rtag not available for gpr", ++}, ++[ POWER8_PME_PM_SWAP_COMPLETE ] = { ++ .pme_name = "PM_SWAP_COMPLETE", ++ .pme_code = 0x308c, ++ .pme_short_desc = "swap cast in completed", ++ .pme_long_desc = "swap cast in completed", ++}, ++[ POWER8_PME_PM_SWAP_COMPLETE_GPR ] = { ++ .pme_name = "PM_SWAP_COMPLETE_GPR", ++ .pme_code = 0x308e, ++ .pme_short_desc = "swap cast in completed fpr gpr", ++ .pme_long_desc = "swap cast in completed fpr gpr", ++}, ++[ POWER8_PME_PM_SYNC_MRK_BR_LINK ] = { ++ .pme_name = "PM_SYNC_MRK_BR_LINK", ++ .pme_code = 0x15152, ++ .pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt", ++ .pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_BR_MPRED ] = { ++ .pme_name = "PM_SYNC_MRK_BR_MPRED", ++ .pme_code = 0x1515c, ++ .pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt", ++ .pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_FX_DIVIDE ] = { ++ .pme_name = "PM_SYNC_MRK_FX_DIVIDE", ++ .pme_code = 0x15156, ++ .pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt", ++ .pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_L2HIT ] = { ++ .pme_name = "PM_SYNC_MRK_L2HIT", ++ .pme_code = 0x15158, ++ .pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt", ++ .pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_L2MISS ] = { ++ .pme_name = "PM_SYNC_MRK_L2MISS", ++ .pme_code = 0x1515a, ++ .pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt", ++ .pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_L3MISS ] = { ++ .pme_name = "PM_SYNC_MRK_L3MISS", ++ .pme_code = 0x15154, ++ .pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt", ++ .pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt.", ++}, ++[ POWER8_PME_PM_SYNC_MRK_PROBE_NOP ] = { ++ .pme_name = "PM_SYNC_MRK_PROBE_NOP", ++ .pme_code = 0x15150, ++ .pme_short_desc = "Marked probeNops which can cause synchronous interrupts", ++ .pme_long_desc = "Marked probeNops which can cause synchronous interrupts.", ++}, ++[ POWER8_PME_PM_SYS_PUMP_CPRED ] = { ++ .pme_name = "PM_SYS_PUMP_CPRED", ++ .pme_code = 0x30050, ++ .pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_SYS_PUMP_MPRED ] = { ++ .pme_name = "PM_SYS_PUMP_MPRED", ++ .pme_code = 0x30052, ++ .pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or", ++}, ++[ POWER8_PME_PM_SYS_PUMP_MPRED_RTY ] = { ++ .pme_name = "PM_SYS_PUMP_MPRED_RTY", ++ .pme_code = 0x40050, ++ .pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", ++ .pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).", ++}, ++[ POWER8_PME_PM_TABLEWALK_CYC ] = { ++ .pme_name = "PM_TABLEWALK_CYC", ++ .pme_code = 0x10026, ++ .pme_short_desc = "Cycles when a tablewalk (I or D) is active", ++ .pme_long_desc = "Tablewalk Active.", ++}, ++[ POWER8_PME_PM_TABLEWALK_CYC_PREF ] = { ++ .pme_name = "PM_TABLEWALK_CYC_PREF", ++ .pme_code = 0xe086, ++ .pme_short_desc = "tablewalk qualified for pte prefetches", ++ .pme_long_desc = "tablewalk qualified for pte prefetches42", ++}, ++[ POWER8_PME_PM_TABORT_TRECLAIM ] = { ++ .pme_name = "PM_TABORT_TRECLAIM", ++ .pme_code = 0x20b2, ++ .pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim", ++ .pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim", ++}, ++[ POWER8_PME_PM_TB_BIT_TRANS ] = { ++ .pme_name = "PM_TB_BIT_TRANS", ++ .pme_code = 0x300f8, ++ .pme_short_desc = "timebase event", ++ .pme_long_desc = "timebase event.", ++}, ++[ POWER8_PME_PM_TEND_PEND_CYC ] = { ++ .pme_name = "PM_TEND_PEND_CYC", ++ .pme_code = 0xe0ba, ++ .pme_short_desc = "TEND latency per thread", ++ .pme_long_desc = "TEND latency per thread42", + }, + [ POWER8_PME_PM_THRD_ALL_RUN_CYC ] = { + .pme_name = "PM_THRD_ALL_RUN_CYC", +@@ -999,11 +6884,587 @@ static const pme_power_entry_t power8_pe[] = { + .pme_short_desc = "All Threads in Run_cycles (was both threads in run_cycles)", + .pme_long_desc = "All Threads in Run_cycles (was both threads in run_cycles).", + }, ++[ POWER8_PME_PM_THRD_CONC_RUN_INST ] = { ++ .pme_name = "PM_THRD_CONC_RUN_INST", ++ .pme_code = 0x300f4, ++ .pme_short_desc = "PPC Instructions Finished when both threads in run_cycles", ++ .pme_long_desc = "Concurrent Run Instructions.", ++}, ++[ POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { ++ .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", ++ .pme_code = 0x10012, ++ .pme_short_desc = "Cycles group completed on both completion slots by any thread", ++ .pme_long_desc = "Two threads finished same cycle (gated by run latch).", ++}, ++[ POWER8_PME_PM_THRD_PRIO_0_1_CYC ] = { ++ .pme_name = "PM_THRD_PRIO_0_1_CYC", ++ .pme_code = 0x40bc, ++ .pme_short_desc = "Cycles thread running at priority level 0 or 1", ++ .pme_long_desc = "Cycles thread running at priority level 0 or 1", ++}, ++[ POWER8_PME_PM_THRD_PRIO_2_3_CYC ] = { ++ .pme_name = "PM_THRD_PRIO_2_3_CYC", ++ .pme_code = 0x40be, ++ .pme_short_desc = "Cycles thread running at priority level 2 or 3", ++ .pme_long_desc = "Cycles thread running at priority level 2 or 3", ++}, ++[ POWER8_PME_PM_THRD_PRIO_4_5_CYC ] = { ++ .pme_name = "PM_THRD_PRIO_4_5_CYC", ++ .pme_code = 0x5080, ++ .pme_short_desc = "Cycles thread running at priority level 4 or 5", ++ .pme_long_desc = "Cycles thread running at priority level 4 or 5", ++}, ++[ POWER8_PME_PM_THRD_PRIO_6_7_CYC ] = { ++ .pme_name = "PM_THRD_PRIO_6_7_CYC", ++ .pme_code = 0x5082, ++ .pme_short_desc = "Cycles thread running at priority level 6 or 7", ++ .pme_long_desc = "Cycles thread running at priority level 6 or 7", ++}, ++[ POWER8_PME_PM_THRD_REBAL_CYC ] = { ++ .pme_name = "PM_THRD_REBAL_CYC", ++ .pme_code = 0x3098, ++ .pme_short_desc = "cycles rebalance was active", ++ .pme_long_desc = "cycles rebalance was active", ++}, ++[ POWER8_PME_PM_THRESH_EXC_1024 ] = { ++ .pme_name = "PM_THRESH_EXC_1024", ++ .pme_code = 0x301ea, ++ .pme_short_desc = "Threshold counter exceeded a value of 1024", ++ .pme_long_desc = "Threshold counter exceeded a value of 1024.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_128 ] = { ++ .pme_name = "PM_THRESH_EXC_128", ++ .pme_code = 0x401ea, ++ .pme_short_desc = "Threshold counter exceeded a value of 128", ++ .pme_long_desc = "Threshold counter exceeded a value of 128.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_2048 ] = { ++ .pme_name = "PM_THRESH_EXC_2048", ++ .pme_code = 0x401ec, ++ .pme_short_desc = "Threshold counter exceeded a value of 2048", ++ .pme_long_desc = "Threshold counter exceeded a value of 2048.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_256 ] = { ++ .pme_name = "PM_THRESH_EXC_256", ++ .pme_code = 0x101e8, ++ .pme_short_desc = "Threshold counter exceed a count of 256", ++ .pme_long_desc = "Threshold counter exceed a count of 256.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_32 ] = { ++ .pme_name = "PM_THRESH_EXC_32", ++ .pme_code = 0x201e6, ++ .pme_short_desc = "Threshold counter exceeded a value of 32", ++ .pme_long_desc = "Threshold counter exceeded a value of 32.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_4096 ] = { ++ .pme_name = "PM_THRESH_EXC_4096", ++ .pme_code = 0x101e6, ++ .pme_short_desc = "Threshold counter exceed a count of 4096", ++ .pme_long_desc = "Threshold counter exceed a count of 4096.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_512 ] = { ++ .pme_name = "PM_THRESH_EXC_512", ++ .pme_code = 0x201e8, ++ .pme_short_desc = "Threshold counter exceeded a value of 512", ++ .pme_long_desc = "Threshold counter exceeded a value of 512.", ++}, ++[ POWER8_PME_PM_THRESH_EXC_64 ] = { ++ .pme_name = "PM_THRESH_EXC_64", ++ .pme_code = 0x301e8, ++ .pme_short_desc = "IFU non-branch finished", ++ .pme_long_desc = "Threshold counter exceeded a value of 64.", ++}, ++[ POWER8_PME_PM_THRESH_MET ] = { ++ .pme_name = "PM_THRESH_MET", ++ .pme_code = 0x101ec, ++ .pme_short_desc = "threshold exceeded", ++ .pme_long_desc = "threshold exceeded.", ++}, + [ POWER8_PME_PM_THRESH_NOT_MET ] = { + .pme_name = "PM_THRESH_NOT_MET", + .pme_code = 0x4016e, + .pme_short_desc = "Threshold counter did not meet threshold", + .pme_long_desc = "Threshold counter did not meet threshold.", + }, ++[ POWER8_PME_PM_TLBIE_FIN ] = { ++ .pme_name = "PM_TLBIE_FIN", ++ .pme_code = 0x30058, ++ .pme_short_desc = "tlbie finished", ++ .pme_long_desc = "tlbie finished.", ++}, ++[ POWER8_PME_PM_TLB_MISS ] = { ++ .pme_name = "PM_TLB_MISS", ++ .pme_code = 0x20066, ++ .pme_short_desc = "TLB Miss (I + D)", ++ .pme_long_desc = "TLB Miss (I + D).", ++}, ++[ POWER8_PME_PM_TM_BEGIN_ALL ] = { ++ .pme_name = "PM_TM_BEGIN_ALL", ++ .pme_code = 0x20b8, ++ .pme_short_desc = "Tm any tbegin", ++ .pme_long_desc = "Tm any tbegin", ++}, ++[ POWER8_PME_PM_TM_CAM_OVERFLOW ] = { ++ .pme_name = "PM_TM_CAM_OVERFLOW", ++ .pme_code = 0x318082, ++ .pme_short_desc = "l3 tm cam overflow during L2 co of SC", ++ .pme_long_desc = "l3 tm cam overflow during L2 co of SC", ++}, ++[ POWER8_PME_PM_TM_CAP_OVERFLOW ] = { ++ .pme_name = "PM_TM_CAP_OVERFLOW", ++ .pme_code = 0x74708c, ++ .pme_short_desc = "TM Footprint Capactiy Overflow", ++ .pme_long_desc = "TM Footprint Capactiy Overflow", ++}, ++[ POWER8_PME_PM_TM_END_ALL ] = { ++ .pme_name = "PM_TM_END_ALL", ++ .pme_code = 0x20ba, ++ .pme_short_desc = "Tm any tend", ++ .pme_long_desc = "Tm any tend", ++}, ++[ POWER8_PME_PM_TM_FAIL_CONF_NON_TM ] = { ++ .pme_name = "PM_TM_FAIL_CONF_NON_TM", ++ .pme_code = 0x3086, ++ .pme_short_desc = "TEXAS fail reason @ completion", ++ .pme_long_desc = "TEXAS fail reason @ completion", ++}, ++[ POWER8_PME_PM_TM_FAIL_CON_TM ] = { ++ .pme_name = "PM_TM_FAIL_CON_TM", ++ .pme_code = 0x3088, ++ .pme_short_desc = "TEXAS fail reason @ completion", ++ .pme_long_desc = "TEXAS fail reason @ completion", ++}, ++[ POWER8_PME_PM_TM_FAIL_DISALLOW ] = { ++ .pme_name = "PM_TM_FAIL_DISALLOW", ++ .pme_code = 0xe0b2, ++ .pme_short_desc = "TM fail disallow", ++ .pme_long_desc = "TM fail disallow42", ++}, ++[ POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = { ++ .pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW", ++ .pme_code = 0x3084, ++ .pme_short_desc = "TEXAS fail reason @ completion", ++ .pme_long_desc = "TEXAS fail reason @ completion", ++}, ++[ POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = { ++ .pme_name = "PM_TM_FAIL_NON_TX_CONFLICT", ++ .pme_code = 0xe0b8, ++ .pme_short_desc = "Non transactional conflict from LSU whtver gets repoted to texas", ++ .pme_long_desc = "Non transactional conflict from LSU whtver gets repoted to texas42", ++}, ++[ POWER8_PME_PM_TM_FAIL_SELF ] = { ++ .pme_name = "PM_TM_FAIL_SELF", ++ .pme_code = 0x308a, ++ .pme_short_desc = "TEXAS fail reason @ completion", ++ .pme_long_desc = "TEXAS fail reason @ completion", ++}, ++[ POWER8_PME_PM_TM_FAIL_TLBIE ] = { ++ .pme_name = "PM_TM_FAIL_TLBIE", ++ .pme_code = 0xe0b4, ++ .pme_short_desc = "TLBIE hit bloom filter", ++ .pme_long_desc = "TLBIE hit bloom filter42", ++}, ++[ POWER8_PME_PM_TM_FAIL_TX_CONFLICT ] = { ++ .pme_name = "PM_TM_FAIL_TX_CONFLICT", ++ .pme_code = 0xe0b6, ++ .pme_short_desc = "Transactional conflict from LSU, whatever gets reported to texas", ++ .pme_long_desc = "Transactional conflict from LSU, whatever gets reported to texas 42", ++}, ++[ POWER8_PME_PM_TM_FAV_CAUSED_FAIL ] = { ++ .pme_name = "PM_TM_FAV_CAUSED_FAIL", ++ .pme_code = 0x727086, ++ .pme_short_desc = "TM Load (fav) caused another thread to fail", ++ .pme_long_desc = "TM Load (fav) caused another thread to fail", ++}, ++[ POWER8_PME_PM_TM_LD_CAUSED_FAIL ] = { ++ .pme_name = "PM_TM_LD_CAUSED_FAIL", ++ .pme_code = 0x717082, ++ .pme_short_desc = "Non TM Ld caused any thread to fail", ++ .pme_long_desc = "Non TM Ld caused any thread to fail", ++}, ++[ POWER8_PME_PM_TM_LD_CONF ] = { ++ .pme_name = "PM_TM_LD_CONF", ++ .pme_code = 0x727084, ++ .pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)", ++ .pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)", ++}, ++[ POWER8_PME_PM_TM_RST_SC ] = { ++ .pme_name = "PM_TM_RST_SC", ++ .pme_code = 0x328086, ++ .pme_short_desc = "tm snp rst tm sc", ++ .pme_long_desc = "tm snp rst tm sc", ++}, ++[ POWER8_PME_PM_TM_SC_CO ] = { ++ .pme_name = "PM_TM_SC_CO", ++ .pme_code = 0x318080, ++ .pme_short_desc = "l3 castout tm Sc line", ++ .pme_long_desc = "l3 castout tm Sc line", ++}, ++[ POWER8_PME_PM_TM_ST_CAUSED_FAIL ] = { ++ .pme_name = "PM_TM_ST_CAUSED_FAIL", ++ .pme_code = 0x73708a, ++ .pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail", ++ .pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail", ++}, ++[ POWER8_PME_PM_TM_ST_CONF ] = { ++ .pme_name = "PM_TM_ST_CONF", ++ .pme_code = 0x737088, ++ .pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)", ++ .pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)", ++}, ++[ POWER8_PME_PM_TM_TBEGIN ] = { ++ .pme_name = "PM_TM_TBEGIN", ++ .pme_code = 0x20bc, ++ .pme_short_desc = "Tm nested tbegin", ++ .pme_long_desc = "Tm nested tbegin", ++}, ++[ POWER8_PME_PM_TM_TRANS_RUN_CYC ] = { ++ .pme_name = "PM_TM_TRANS_RUN_CYC", ++ .pme_code = 0x10060, ++ .pme_short_desc = "run cycles in transactional state", ++ .pme_long_desc = "run cycles in transactional state.", ++}, ++[ POWER8_PME_PM_TM_TRANS_RUN_INST ] = { ++ .pme_name = "PM_TM_TRANS_RUN_INST", ++ .pme_code = 0x30060, ++ .pme_short_desc = "Instructions completed in transactional state", ++ .pme_long_desc = "Instructions completed in transactional state.", ++}, ++[ POWER8_PME_PM_TM_TRESUME ] = { ++ .pme_name = "PM_TM_TRESUME", ++ .pme_code = 0x3080, ++ .pme_short_desc = "Tm resume", ++ .pme_long_desc = "Tm resume", ++}, ++[ POWER8_PME_PM_TM_TSUSPEND ] = { ++ .pme_name = "PM_TM_TSUSPEND", ++ .pme_code = 0x20be, ++ .pme_short_desc = "Tm suspend", ++ .pme_long_desc = "Tm suspend", ++}, ++[ POWER8_PME_PM_TM_TX_PASS_RUN_CYC ] = { ++ .pme_name = "PM_TM_TX_PASS_RUN_CYC", ++ .pme_code = 0x2e012, ++ .pme_short_desc = "cycles spent in successful transactions", ++ .pme_long_desc = "run cycles spent in successful transactions.", ++}, ++[ POWER8_PME_PM_TM_TX_PASS_RUN_INST ] = { ++ .pme_name = "PM_TM_TX_PASS_RUN_INST", ++ .pme_code = 0x4e014, ++ .pme_short_desc = "run instructions spent in successful transactions.", ++ .pme_long_desc = "run instructions spent in successful transactions.", ++}, ++[ POWER8_PME_PM_UP_PREF_L3 ] = { ++ .pme_name = "PM_UP_PREF_L3", ++ .pme_code = 0xe08c, ++ .pme_short_desc = "Micropartition prefetch", ++ .pme_long_desc = "Micropartition prefetch42", ++}, ++[ POWER8_PME_PM_UP_PREF_POINTER ] = { ++ .pme_name = "PM_UP_PREF_POINTER", ++ .pme_code = 0xe08e, ++ .pme_short_desc = "Micrpartition pointer prefetches", ++ .pme_long_desc = "Micrpartition pointer prefetches42", ++}, ++[ POWER8_PME_PM_VSU0_16FLOP ] = { ++ .pme_name = "PM_VSU0_16FLOP", ++ .pme_code = 0xa0a4, ++ .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", ++ .pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", ++}, ++[ POWER8_PME_PM_VSU0_1FLOP ] = { ++ .pme_name = "PM_VSU0_1FLOP", ++ .pme_code = 0xa080, ++ .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", ++ .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU", ++}, ++[ POWER8_PME_PM_VSU0_2FLOP ] = { ++ .pme_name = "PM_VSU0_2FLOP", ++ .pme_code = 0xa098, ++ .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", ++ .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", ++}, ++[ POWER8_PME_PM_VSU0_4FLOP ] = { ++ .pme_name = "PM_VSU0_4FLOP", ++ .pme_code = 0xa09c, ++ .pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", ++ .pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", ++}, ++[ POWER8_PME_PM_VSU0_8FLOP ] = { ++ .pme_name = "PM_VSU0_8FLOP", ++ .pme_code = 0xa0a0, ++ .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", ++ .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", ++}, ++[ POWER8_PME_PM_VSU0_COMPLEX_ISSUED ] = { ++ .pme_name = "PM_VSU0_COMPLEX_ISSUED", ++ .pme_code = 0xb0a4, ++ .pme_short_desc = "Complex VMX instruction issued", ++ .pme_long_desc = "Complex VMX instruction issued", ++}, ++[ POWER8_PME_PM_VSU0_CY_ISSUED ] = { ++ .pme_name = "PM_VSU0_CY_ISSUED", ++ .pme_code = 0xb0b4, ++ .pme_short_desc = "Cryptographic instruction RFC02196 Issued", ++ .pme_long_desc = "Cryptographic instruction RFC02196 Issued", ++}, ++[ POWER8_PME_PM_VSU0_DD_ISSUED ] = { ++ .pme_name = "PM_VSU0_DD_ISSUED", ++ .pme_code = 0xb0a8, ++ .pme_short_desc = "64BIT Decimal Issued", ++ .pme_long_desc = "64BIT Decimal Issued", ++}, ++[ POWER8_PME_PM_VSU0_DP_2FLOP ] = { ++ .pme_name = "PM_VSU0_DP_2FLOP", ++ .pme_code = 0xa08c, ++ .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", ++ .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", ++}, ++[ POWER8_PME_PM_VSU0_DP_FMA ] = { ++ .pme_name = "PM_VSU0_DP_FMA", ++ .pme_code = 0xa090, ++ .pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", ++ .pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", ++}, ++[ POWER8_PME_PM_VSU0_DP_FSQRT_FDIV ] = { ++ .pme_name = "PM_VSU0_DP_FSQRT_FDIV", ++ .pme_code = 0xa094, ++ .pme_short_desc = "DP vector versions of fdiv,fsqrt", ++ .pme_long_desc = "DP vector versions of fdiv,fsqrt", ++}, ++[ POWER8_PME_PM_VSU0_DQ_ISSUED ] = { ++ .pme_name = "PM_VSU0_DQ_ISSUED", ++ .pme_code = 0xb0ac, ++ .pme_short_desc = "128BIT Decimal Issued", ++ .pme_long_desc = "128BIT Decimal Issued", ++}, ++[ POWER8_PME_PM_VSU0_EX_ISSUED ] = { ++ .pme_name = "PM_VSU0_EX_ISSUED", ++ .pme_code = 0xb0b0, ++ .pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", ++ .pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", ++}, ++[ POWER8_PME_PM_VSU0_FIN ] = { ++ .pme_name = "PM_VSU0_FIN", ++ .pme_code = 0xa0bc, ++ .pme_short_desc = "VSU0 Finished an instruction", ++ .pme_long_desc = "VSU0 Finished an instruction", ++}, ++[ POWER8_PME_PM_VSU0_FMA ] = { ++ .pme_name = "PM_VSU0_FMA", ++ .pme_code = 0xa084, ++ .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", ++ .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", ++}, ++[ POWER8_PME_PM_VSU0_FPSCR ] = { ++ .pme_name = "PM_VSU0_FPSCR", ++ .pme_code = 0xb098, ++ .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", ++ .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", ++}, ++[ POWER8_PME_PM_VSU0_FSQRT_FDIV ] = { ++ .pme_name = "PM_VSU0_FSQRT_FDIV", ++ .pme_code = 0xa088, ++ .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", ++ .pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", ++}, ++[ POWER8_PME_PM_VSU0_PERMUTE_ISSUED ] = { ++ .pme_name = "PM_VSU0_PERMUTE_ISSUED", ++ .pme_code = 0xb090, ++ .pme_short_desc = "Permute VMX Instruction Issued", ++ .pme_long_desc = "Permute VMX Instruction Issued", ++}, ++[ POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED ] = { ++ .pme_name = "PM_VSU0_SCALAR_DP_ISSUED", ++ .pme_code = 0xb088, ++ .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", ++ .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", ++}, ++[ POWER8_PME_PM_VSU0_SIMPLE_ISSUED ] = { ++ .pme_name = "PM_VSU0_SIMPLE_ISSUED", ++ .pme_code = 0xb094, ++ .pme_short_desc = "Simple VMX instruction issued", ++ .pme_long_desc = "Simple VMX instruction issued", ++}, ++[ POWER8_PME_PM_VSU0_SINGLE ] = { ++ .pme_name = "PM_VSU0_SINGLE", ++ .pme_code = 0xa0a8, ++ .pme_short_desc = "FPU single precision", ++ .pme_long_desc = "FPU single precision", ++}, ++[ POWER8_PME_PM_VSU0_SQ ] = { ++ .pme_name = "PM_VSU0_SQ", ++ .pme_code = 0xb09c, ++ .pme_short_desc = "Store Vector Issued", ++ .pme_long_desc = "Store Vector Issued", ++}, ++[ POWER8_PME_PM_VSU0_STF ] = { ++ .pme_name = "PM_VSU0_STF", ++ .pme_code = 0xb08c, ++ .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", ++ .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", ++}, ++[ POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED ] = { ++ .pme_name = "PM_VSU0_VECTOR_DP_ISSUED", ++ .pme_code = 0xb080, ++ .pme_short_desc = "Double Precision vector instruction issued on Pipe0", ++ .pme_long_desc = "Double Precision vector instruction issued on Pipe0", ++}, ++[ POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { ++ .pme_name = "PM_VSU0_VECTOR_SP_ISSUED", ++ .pme_code = 0xb084, ++ .pme_short_desc = "Single Precision vector instruction issued (executed)", ++ .pme_long_desc = "Single Precision vector instruction issued (executed)", ++}, ++[ POWER8_PME_PM_VSU1_16FLOP ] = { ++ .pme_name = "PM_VSU1_16FLOP", ++ .pme_code = 0xa0a6, ++ .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", ++ .pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)", ++}, ++[ POWER8_PME_PM_VSU1_1FLOP ] = { ++ .pme_name = "PM_VSU1_1FLOP", ++ .pme_code = 0xa082, ++ .pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", ++ .pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished", ++}, ++[ POWER8_PME_PM_VSU1_2FLOP ] = { ++ .pme_name = "PM_VSU1_2FLOP", ++ .pme_code = 0xa09a, ++ .pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", ++ .pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)", ++}, ++[ POWER8_PME_PM_VSU1_4FLOP ] = { ++ .pme_name = "PM_VSU1_4FLOP", ++ .pme_code = 0xa09e, ++ .pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", ++ .pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)", ++}, ++[ POWER8_PME_PM_VSU1_8FLOP ] = { ++ .pme_name = "PM_VSU1_8FLOP", ++ .pme_code = 0xa0a2, ++ .pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", ++ .pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)", ++}, ++[ POWER8_PME_PM_VSU1_COMPLEX_ISSUED ] = { ++ .pme_name = "PM_VSU1_COMPLEX_ISSUED", ++ .pme_code = 0xb0a6, ++ .pme_short_desc = "Complex VMX instruction issued", ++ .pme_long_desc = "Complex VMX instruction issued", ++}, ++[ POWER8_PME_PM_VSU1_CY_ISSUED ] = { ++ .pme_name = "PM_VSU1_CY_ISSUED", ++ .pme_code = 0xb0b6, ++ .pme_short_desc = "Cryptographic instruction RFC02196 Issued", ++ .pme_long_desc = "Cryptographic instruction RFC02196 Issued", ++}, ++[ POWER8_PME_PM_VSU1_DD_ISSUED ] = { ++ .pme_name = "PM_VSU1_DD_ISSUED", ++ .pme_code = 0xb0aa, ++ .pme_short_desc = "64BIT Decimal Issued", ++ .pme_long_desc = "64BIT Decimal Issued", ++}, ++[ POWER8_PME_PM_VSU1_DP_2FLOP ] = { ++ .pme_name = "PM_VSU1_DP_2FLOP", ++ .pme_code = 0xa08e, ++ .pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", ++ .pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg", ++}, ++[ POWER8_PME_PM_VSU1_DP_FMA ] = { ++ .pme_name = "PM_VSU1_DP_FMA", ++ .pme_code = 0xa092, ++ .pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", ++ .pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub", ++}, ++[ POWER8_PME_PM_VSU1_DP_FSQRT_FDIV ] = { ++ .pme_name = "PM_VSU1_DP_FSQRT_FDIV", ++ .pme_code = 0xa096, ++ .pme_short_desc = "DP vector versions of fdiv,fsqrt", ++ .pme_long_desc = "DP vector versions of fdiv,fsqrt", ++}, ++[ POWER8_PME_PM_VSU1_DQ_ISSUED ] = { ++ .pme_name = "PM_VSU1_DQ_ISSUED", ++ .pme_code = 0xb0ae, ++ .pme_short_desc = "128BIT Decimal Issued", ++ .pme_long_desc = "128BIT Decimal Issued", ++}, ++[ POWER8_PME_PM_VSU1_EX_ISSUED ] = { ++ .pme_name = "PM_VSU1_EX_ISSUED", ++ .pme_code = 0xb0b2, ++ .pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", ++ .pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued", ++}, ++[ POWER8_PME_PM_VSU1_FIN ] = { ++ .pme_name = "PM_VSU1_FIN", ++ .pme_code = 0xa0be, ++ .pme_short_desc = "VSU1 Finished an instruction", ++ .pme_long_desc = "VSU1 Finished an instruction", ++}, ++[ POWER8_PME_PM_VSU1_FMA ] = { ++ .pme_name = "PM_VSU1_FMA", ++ .pme_code = 0xa086, ++ .pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", ++ .pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!", ++}, ++[ POWER8_PME_PM_VSU1_FPSCR ] = { ++ .pme_name = "PM_VSU1_FPSCR", ++ .pme_code = 0xb09a, ++ .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", ++ .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", ++}, ++[ POWER8_PME_PM_VSU1_FSQRT_FDIV ] = { ++ .pme_name = "PM_VSU1_FSQRT_FDIV", ++ .pme_code = 0xa08a, ++ .pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", ++ .pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!", ++}, ++[ POWER8_PME_PM_VSU1_PERMUTE_ISSUED ] = { ++ .pme_name = "PM_VSU1_PERMUTE_ISSUED", ++ .pme_code = 0xb092, ++ .pme_short_desc = "Permute VMX Instruction Issued", ++ .pme_long_desc = "Permute VMX Instruction Issued", ++}, ++[ POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED ] = { ++ .pme_name = "PM_VSU1_SCALAR_DP_ISSUED", ++ .pme_code = 0xb08a, ++ .pme_short_desc = "Double Precision scalar instruction issued on Pipe1", ++ .pme_long_desc = "Double Precision scalar instruction issued on Pipe1", ++}, ++[ POWER8_PME_PM_VSU1_SIMPLE_ISSUED ] = { ++ .pme_name = "PM_VSU1_SIMPLE_ISSUED", ++ .pme_code = 0xb096, ++ .pme_short_desc = "Simple VMX instruction issued", ++ .pme_long_desc = "Simple VMX instruction issued", ++}, ++[ POWER8_PME_PM_VSU1_SINGLE ] = { ++ .pme_name = "PM_VSU1_SINGLE", ++ .pme_code = 0xa0aa, ++ .pme_short_desc = "FPU single precision", ++ .pme_long_desc = "FPU single precision", ++}, ++[ POWER8_PME_PM_VSU1_SQ ] = { ++ .pme_name = "PM_VSU1_SQ", ++ .pme_code = 0xb09e, ++ .pme_short_desc = "Store Vector Issued", ++ .pme_long_desc = "Store Vector Issued", ++}, ++[ POWER8_PME_PM_VSU1_STF ] = { ++ .pme_name = "PM_VSU1_STF", ++ .pme_code = 0xb08e, ++ .pme_short_desc = "FPU store (SP or DP) issued on Pipe1", ++ .pme_long_desc = "FPU store (SP or DP) issued on Pipe1", ++}, ++[ POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED ] = { ++ .pme_name = "PM_VSU1_VECTOR_DP_ISSUED", ++ .pme_code = 0xb082, ++ .pme_short_desc = "Double Precision vector instruction issued on Pipe1", ++ .pme_long_desc = "Double Precision vector instruction issued on Pipe1", ++}, ++[ POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED ] = { ++ .pme_name = "PM_VSU1_VECTOR_SP_ISSUED", ++ .pme_code = 0xb086, ++ .pme_short_desc = "Single Precision vector instruction issued (executed)", ++ .pme_long_desc = "Single Precision vector instruction issued (executed)", ++}, + }; + #endif diff --git a/SPECS/libpfm.spec b/SPECS/libpfm.spec index 7552556..d15596d 100644 --- a/SPECS/libpfm.spec +++ b/SPECS/libpfm.spec @@ -10,7 +10,7 @@ Name: libpfm Version: 4.4.0 -Release: 6%{?dist} +Release: 9%{?dist} Summary: Library to encode performance events for use by perf tool @@ -19,8 +19,8 @@ License: MIT URL: http://perfmon2.sourceforge.net/ Source0: http://sourceforge.net/projects/perfmon2/files/libpfm4/%{name}-%{version}.tar.gz Patch1: libpfm-power8.patch -Patch10: libpfm-haswell.patch Patch11: libpfm-events.patch +Patch200: libpfm-aarch64.patch %if %{with python} BuildRequires: python-devel @@ -66,8 +66,8 @@ Python bindings for libpfm4 and perf_event_open system call. %setup -q %patch1 -p1 -%patch10 -p1 %patch11 -p1 +%patch200 -p1 %build %if %{with python} @@ -115,6 +115,15 @@ make \ %endif %changelog +* Thu Oct 16 2014 William Cohen - 4.4.0-9 +- Bump and rebuid for chained build. rhbz1126091 + +* Fri Sep 26 2014 William Cohen - 4.4.0-8 +- Update Intel processor support. rhbz1126091 + +* Wed Sep 3 2014 William Cohen - 4.4.0-7 +- Add aarch64 and power8 support for rhbz963457 and rhbz1088557 + * Fri Jan 24 2014 Daniel Mach - 4.4.0-6 - Mass rebuild 2014-01-24