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commit 9b38b5435de72ae4253bd8a6d6558e50fff618e7
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Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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Date: Fri Feb 17 15:50:14 2017 +0100
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s390/cpumf: add support for IBM z13/z13s counters
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This commit adds the counter definitions for the IBM z13/z13s
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specific counters. These counters are available in the extended
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and the new MT-diagnostic counter sets.
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Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
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index e00b088..be9d7d9 100644
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--- a/lib/events/s390x_cpumf_events.h
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+++ b/lib/events/s390x_cpumf_events.h
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@@ -11,6 +11,7 @@
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#define CPUMF_CTRSET_PROBLEM_STATE 4
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#define CPUMF_CTRSET_CRYPTO 8
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#define CPUMF_CTRSET_EXTENDED 1
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+#define CPUMF_CTRSET_MT_DIAG 32
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static const pme_cpumf_ctr_t cpumcf_generic_counters[] = {
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@@ -840,6 +841,458 @@ static const pme_cpumf_ctr_t cpumcf_zec12_counters[] = {
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},
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};
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+static const pme_cpumf_ctr_t cpumcf_z13_counters[] = {
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+ {
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+ .ctrnum = 128,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_WRITES_RO_EXCL",
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+ .desc = "Counter:128 Name:L1D_WRITES_RO_EXCL A directory"
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+ " write to the Level-1 Data cache where the line was"
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+ " originally in a Read-Only state in the cache but"
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+ " has been updated to be in the Exclusive state that"
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+ " allows stores to the cache line.",
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+ },
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+ {
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+ .ctrnum = 129,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "DTLB1_WRITES",
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+ .desc = "A translation entry has been written to the Level-1"
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+ " Data Translation Lookaside Buffer",
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+ },
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+ {
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+ .ctrnum = 130,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "DTLB1_MISSES",
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+ .desc = "Level-1 Data TLB miss in progress. Incremented by"
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+ " one for every cycle a DTLB1 miss is in progress.",
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+ },
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+ {
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+ .ctrnum = 131,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "DTLB1_HPAGE_WRITES",
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+ .desc = "A translation entry has been written to the Level-1"
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+ " Data Translation Lookaside Buffer for a one-"
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+ " megabyte page",
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+ },
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+ {
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+ .ctrnum = 132,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "DTLB1_GPAGE_WRITES",
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+ .desc = "Counter:132 Name:DTLB1_GPAGE_WRITES A translation"
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+ " entry has been written to the Level-1 Data"
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+ " Translation Lookaside Buffer for a two-gigabyte"
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+ " page.",
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+ },
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+ {
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+ .ctrnum = 133,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_L2D_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from the Level-2 Data cache",
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+ },
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+ {
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+ .ctrnum = 134,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "ITLB1_WRITES",
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+ .desc = "A translation entry has been written to the Level-1"
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+ " Instruction Translation Lookaside Buffer",
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+ },
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+ {
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+ .ctrnum = 135,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "ITLB1_MISSES",
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+ .desc = "Level-1 Instruction TLB miss in progress."
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+ " Incremented by one for every cycle an ITLB1 miss is"
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+ " in progress",
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+ },
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+ {
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+ .ctrnum = 136,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1I_L2I_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Instruction cache"
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+ " directory where the returned cache line was sourced"
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+ " from the Level-2 Instruction cache",
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+ },
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+ {
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+ .ctrnum = 137,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "TLB2_PTE_WRITES",
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+ .desc = "A translation entry has been written to the Level-2"
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+ " TLB Page Table Entry arrays",
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+ },
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+ {
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+ .ctrnum = 138,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "TLB2_CRSTE_HPAGE_WRITES",
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+ .desc = "A translation entry has been written to the Level-2"
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+ " TLB Combined Region Segment Table Entry arrays for"
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+ " a one-megabyte large page translation",
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+ },
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+ {
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+ .ctrnum = 139,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "TLB2_CRSTE_WRITES",
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+ .desc = "A translation entry has been written to the Level-2"
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+ " TLB Combined Region Segment Table Entry arrays",
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+ },
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+ {
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+ .ctrnum = 140,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "TX_C_TEND",
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+ .desc = "A TEND instruction has completed in a constrained"
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+ " transactional-execution mode",
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+ },
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+ {
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+ .ctrnum = 141,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "TX_NC_TEND",
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+ .desc = "A TEND instruction has completed in a non-"
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+ " constrained transactional-execution mode",
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+ },
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+ {
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+ .ctrnum = 143,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1C_TLB1_MISSES",
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+ .desc = "Increments by one for any cycle where a Level-1"
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+ " cache or Level-1 TLB miss is in progress.",
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+ },
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+ {
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+ .ctrnum = 144,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Chip Level-3 cache without intervention",
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+ },
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+ {
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+ .ctrnum = 145,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Chip Level-3 cache with intervention",
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+ },
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+ {
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+ .ctrnum = 146,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONNODE_L4_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Node Level-4 cache",
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+ },
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+ {
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+ .ctrnum = 147,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONNODE_L3_SOURCED_WRITES_IV",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Node Level-3 cache with intervention",
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+ },
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+ {
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+ .ctrnum = 148,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONNODE_L3_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Node Level-3 cache without intervention",
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+ },
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+ {
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+ .ctrnum = 149,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONDRAWER_L4_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Drawer Level-4 cache",
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+ },
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+ {
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+ .ctrnum = 150,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Drawer Level-3 cache with intervention",
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+ },
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+ {
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+ .ctrnum = 151,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONDRAWER_L3_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an On-Drawer Level-3 cache without"
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+ " intervention",
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+ },
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+ {
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+ .ctrnum = 152,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Same-Column Level-4 cache",
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+ },
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+ {
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+ .ctrnum = 153,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Same-Column Level-3 cache with"
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+ " intervention",
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+ },
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+ {
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+ .ctrnum = 154,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Same-Column Level-3 cache"
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+ " without intervention",
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+ },
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+ {
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+ .ctrnum = 155,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Far-Column Level-4 cache",
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+ },
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+ {
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+ .ctrnum = 156,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Far-Column Level-3 cache with"
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+ " intervention",
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+ },
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+ {
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+ .ctrnum = 157,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from an Off-Drawer Far-Column Level-3 cache without"
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+ " intervention",
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+ },
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+ {
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+ .ctrnum = 158,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONNODE_MEM_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from On-Node memory",
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+ },
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+ {
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+ .ctrnum = 159,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_ONDRAWER_MEM_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from On-Drawer memory",
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+ },
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+ {
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+ .ctrnum = 160,
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+ .ctrset = CPUMF_CTRSET_EXTENDED,
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+ .name = "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
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+ .desc = "A directory write to the Level-1 Data cache"
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+ " directory where the returned cache line was sourced"
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+ " from On-Drawer memory",
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+ },
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+ {
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+ .ctrnum = 161,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCHIP_MEM_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Chip memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 162,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Chip Level-3 cache without intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 163,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On Chip Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 164,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONNODE_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Node Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 165,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONNODE_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Node Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 166,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONNODE_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Node Level-3 cache without intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 167,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONDRAWER_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Drawer Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 168,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Drawer Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 169,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONDRAWER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Drawer Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 170,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Same-Column Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 171,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Same-Column Level-3 cache with"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 172,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Same-Column Level-3 cache"
|
|
|
23ec99 |
+ " without intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 173,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Far-Column Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 174,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Far-Column Level-3 cache with"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 175,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Far-Column Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 176,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONNODE_MEM_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Node memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 177,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONDRAWER_MEM_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Drawer memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 178,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Drawer memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 179,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_MEM_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Chip memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 218,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_NC_TABORT",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a non-"
|
|
|
23ec99 |
+ " constrained transactional-execution mode",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 219,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_C_TABORT_NO_SPECIAL",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a constrained"
|
|
|
23ec99 |
+ " transactional-execution mode and the CPU is not"
|
|
|
23ec99 |
+ " using any special logic to allow the transaction to"
|
|
|
23ec99 |
+ " complete",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 220,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_C_TABORT_SPECIAL",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a constrained"
|
|
|
23ec99 |
+ " transactional-execution mode and the CPU is using"
|
|
|
23ec99 |
+ " special logic to allow the transaction to complete",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 448,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_MT_DIAG,
|
|
|
23ec99 |
+ .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
|
|
23ec99 |
+ .desc = "Cycle count with one thread active",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 449,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_MT_DIAG,
|
|
|
23ec99 |
+ .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
|
|
23ec99 |
+ .desc = "Cycle count with two threads active",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+};
|
|
|
23ec99 |
+
|
|
|
23ec99 |
static const pme_cpumf_ctr_t cpumsf_counters[] = {
|
|
|
23ec99 |
{
|
|
|
23ec99 |
.ctrnum = 720896,
|
|
|
23ec99 |
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
index b5444ef..7273962 100644
|
|
|
23ec99 |
--- a/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
+++ b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
@@ -128,6 +128,11 @@ static int pfm_cpumcf_init(void *this)
|
|
|
23ec99 |
ext_set = cpumcf_zec12_counters;
|
|
|
23ec99 |
ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_zec12_counters);
|
|
|
23ec99 |
break;
|
|
|
23ec99 |
+ case 2964: /* IBM z13 */
|
|
|
23ec99 |
+ case 2965: /* IBM z13s */
|
|
|
23ec99 |
+ ext_set = cpumcf_z13_counters;
|
|
|
23ec99 |
+ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z13_counters);
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
default:
|
|
|
23ec99 |
/* No extended counter set for this machine type or there
|
|
|
23ec99 |
* was an error retrieving the machine type */
|
|
|
23ec99 |
commit 8f2653b8e2e18bad44ba1acc7f92c825f226ef71
|
|
|
23ec99 |
Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
|
|
|
23ec99 |
Date: Fri Oct 13 16:57:32 2017 +0200
|
|
|
23ec99 |
|
|
|
23ec99 |
s390/cpumf: add support for IBM z14 counters
|
|
|
23ec99 |
|
|
|
23ec99 |
Add counter definitions for the IBM z14 hardware model. With z14,
|
|
|
23ec99 |
the counters in the problem-state set are reduced and the counter
|
|
|
23ec99 |
first number version is increased accordingly. Now, the counters
|
|
|
23ec99 |
are processed depending on the counter facility versions.
|
|
|
23ec99 |
|
|
|
23ec99 |
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
|
|
|
23ec99 |
|
|
|
23ec99 |
diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h
|
|
|
23ec99 |
index be9d7d9..c843bc3 100644
|
|
|
23ec99 |
--- a/lib/events/s390x_cpumf_events.h
|
|
|
23ec99 |
+++ b/lib/events/s390x_cpumf_events.h
|
|
|
23ec99 |
@@ -14,7 +14,7 @@
|
|
|
23ec99 |
#define CPUMF_CTRSET_MT_DIAG 32
|
|
|
23ec99 |
|
|
|
23ec99 |
|
|
|
23ec99 |
-static const pme_cpumf_ctr_t cpumcf_generic_counters[] = {
|
|
|
23ec99 |
+static const pme_cpumf_ctr_t cpumcf_fvn1_counters[] = {
|
|
|
23ec99 |
{
|
|
|
23ec99 |
.ctrnum = 0,
|
|
|
23ec99 |
.ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
@@ -87,6 +87,60 @@ static const pme_cpumf_ctr_t cpumcf_generic_counters[] = {
|
|
|
23ec99 |
.name = "PROBLEM_STATE_L1D_PENALTY_CYCLES",
|
|
|
23ec99 |
.desc = "Problem-State Level-1 D-Cache Penalty Cycle Count",
|
|
|
23ec99 |
},
|
|
|
23ec99 |
+};
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+static const pme_cpumf_ctr_t cpumcf_fvn3_counters[] = {
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 0,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "CPU_CYCLES",
|
|
|
23ec99 |
+ .desc = "Cycle Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 1,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "INSTRUCTIONS",
|
|
|
23ec99 |
+ .desc = "Instruction Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 2,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "L1I_DIR_WRITES",
|
|
|
23ec99 |
+ .desc = "Level-1 I-Cache Directory Write Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 3,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "L1I_PENALTY_CYCLES",
|
|
|
23ec99 |
+ .desc = "Level-1 I-Cache Penalty Cycle Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 4,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "L1D_DIR_WRITES",
|
|
|
23ec99 |
+ .desc = "Level-1 D-Cache Directory Write Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 5,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_BASIC,
|
|
|
23ec99 |
+ .name = "L1D_PENALTY_CYCLES",
|
|
|
23ec99 |
+ .desc = "Level-1 D-Cache Penalty Cycle Count",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 32,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_PROBLEM_STATE,
|
|
|
23ec99 |
+ .name = "PROBLEM_STATE_CPU_CYCLES",
|
|
|
23ec99 |
+ .desc = "Problem-State Cycle Count",
|
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23ec99 |
+ },
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23ec99 |
+ {
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23ec99 |
+ .ctrnum = 33,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_PROBLEM_STATE,
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23ec99 |
+ .name = "PROBLEM_STATE_INSTRUCTIONS",
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23ec99 |
+ .desc = "Problem-State Instruction Count",
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23ec99 |
+ },
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23ec99 |
+};
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23ec99 |
+
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23ec99 |
+static const pme_cpumf_ctr_t cpumcf_svn_generic_counters[] = {
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23ec99 |
{
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23ec99 |
.ctrnum = 64,
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23ec99 |
.ctrset = CPUMF_CTRSET_CRYPTO,
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23ec99 |
@@ -1293,6 +1347,434 @@ static const pme_cpumf_ctr_t cpumcf_z13_counters[] = {
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23ec99 |
},
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23ec99 |
};
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23ec99 |
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23ec99 |
+static const pme_cpumf_ctr_t cpumcf_z14_counters[] = {
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23ec99 |
+ {
|
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23ec99 |
+ .ctrnum = 128,
|
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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23ec99 |
+ .name = "L1D_WRITES_RO_EXCL",
|
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23ec99 |
+ .desc = "Counter:128 Name:L1D_WRITES_RO_EXCL A directory"
|
|
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23ec99 |
+ " write to the Level-1 Data cache where the line was"
|
|
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23ec99 |
+ " originally in a Read-Only state in the cache but"
|
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23ec99 |
+ " has been updated to be in the Exclusive state that"
|
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23ec99 |
+ " allows stores to the cache line",
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23ec99 |
+ },
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23ec99 |
+ {
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23ec99 |
+ .ctrnum = 129,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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23ec99 |
+ .name = "DTLB2_WRITES",
|
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23ec99 |
+ .desc = "A translation has been written into The Translation"
|
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23ec99 |
+ " Lookaside Buffer 2 (TLB2) and the request was made"
|
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23ec99 |
+ " by the data cache",
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23ec99 |
+ },
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23ec99 |
+ {
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23ec99 |
+ .ctrnum = 130,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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23ec99 |
+ .name = "DTLB2_MISSES",
|
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23ec99 |
+ .desc = "A TLB2 miss is in progress for a request made by"
|
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23ec99 |
+ " the data cache. Incremented by one for every TLB2"
|
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23ec99 |
+ " miss in progress for the Level-1 Data cache on this"
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23ec99 |
+ " cycle",
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23ec99 |
+ },
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23ec99 |
+ {
|
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23ec99 |
+ .ctrnum = 131,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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23ec99 |
+ .name = "DTLB2_HPAGE_WRITES",
|
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|
23ec99 |
+ .desc = "A translation entry was written into the Combined"
|
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23ec99 |
+ " Region and Segment Table Entry array in the Level-2"
|
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23ec99 |
+ " TLB for a one-megabyte page or a Last Host"
|
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23ec99 |
+ " Translation was done",
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23ec99 |
+ },
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23ec99 |
+ {
|
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23ec99 |
+ .ctrnum = 132,
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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23ec99 |
+ .name = "DTLB2_GPAGE_WRITES",
|
|
|
23ec99 |
+ .desc = "A translation entry for a two-gigabyte page was"
|
|
|
23ec99 |
+ " written into the Level-2 TLB",
|
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|
23ec99 |
+ },
|
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23ec99 |
+ {
|
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23ec99 |
+ .ctrnum = 133,
|
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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|
23ec99 |
+ .name = "L1D_L2D_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from the Level-2 Data cache",
|
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|
23ec99 |
+ },
|
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23ec99 |
+ {
|
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|
23ec99 |
+ .ctrnum = 134,
|
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23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
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|
23ec99 |
+ .name = "ITLB2_WRITES",
|
|
|
23ec99 |
+ .desc = "A translation entry has been written into the"
|
|
|
23ec99 |
+ " Translation Lookaside Buffer 2 (TLB2) and the"
|
|
|
23ec99 |
+ " request was made by the instruction cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 135,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "ITLB2_MISSES",
|
|
|
23ec99 |
+ .desc = "A TLB2 miss is in progress for a request made by"
|
|
|
23ec99 |
+ " the instruction cache. Incremented by one for every"
|
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|
23ec99 |
+ " TLB2 miss in progress for the Level-1 Instruction"
|
|
|
23ec99 |
+ " cache in a cycle",
|
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23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 136,
|
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|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_L2I_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from the Level-2 Instruction cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 137,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TLB2_PTE_WRITES",
|
|
|
23ec99 |
+ .desc = "A translation entry was written into the Page Table"
|
|
|
23ec99 |
+ " Entry array in the Level-2 TLB",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 138,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TLB2_CRSTE_WRITES",
|
|
|
23ec99 |
+ .desc = "Translation entries were written into the Combined"
|
|
|
23ec99 |
+ " Region and Segment Table Entry array and the Page"
|
|
|
23ec99 |
+ " Table Entry array in the Level-2 TLB",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 139,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TLB2_ENGINES_BUSY",
|
|
|
23ec99 |
+ .desc = "The number of Level-2 TLB translation engines busy"
|
|
|
23ec99 |
+ " in a cycle",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 140,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_C_TEND",
|
|
|
23ec99 |
+ .desc = "A TEND instruction has completed in a constrained"
|
|
|
23ec99 |
+ " transactional-execution mode",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 141,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_NC_TEND",
|
|
|
23ec99 |
+ .desc = "A TEND instruction has completed in a non-"
|
|
|
23ec99 |
+ " constrained transactional-execution mode",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 143,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1C_TLB2_MISSES",
|
|
|
23ec99 |
+ .desc = "Increments by one for any cycle where a level-1"
|
|
|
23ec99 |
+ " cache or level-2 TLB miss is in progress",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 144,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Chip Level-3 cache without intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 145,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Chip memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 146,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Chip Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 147,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Cluster Level-3 cache withountervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 148,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Cluster memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 149,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Cluster Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 150,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Cluster Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 151,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Cluster memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 152,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Cluster Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 153,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 154,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Drawer memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 155,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 156,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONDRAWER_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Drawer Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 157,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_OFFDRAWER_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Drawer Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 158,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Data cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Chip L3 but a read-only invalidate was done"
|
|
|
23ec99 |
+ " to remove other copies of the cache line",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 162,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache ine was sourced"
|
|
|
23ec99 |
+ " from an On-Chip Level-3 cache without intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 163,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache ine was sourced"
|
|
|
23ec99 |
+ " from On-Chip memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 164,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache ine was sourced"
|
|
|
23ec99 |
+ " from an On-Chip Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 165,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Cluster Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 166,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an On-Cluster memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 167,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Cluster Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 168,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Cluster Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 169,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Cluster memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 170,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Cluster Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 171,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Level-3 cache without"
|
|
|
23ec99 |
+ " intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 172,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Drawer memory",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 173,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from an Off-Drawer Level-3 cache with intervention",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 174,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_ONDRAWER_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from On-Drawer Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 175,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "L1I_OFFDRAWER_L4_SOURCED_WRITES",
|
|
|
23ec99 |
+ .desc = "A directory write to the Level-1 Instruction cache"
|
|
|
23ec99 |
+ " directory where the returned cache line was sourced"
|
|
|
23ec99 |
+ " from Off-Drawer Level-4 cache",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 224,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "BCD_DFP_EXECUTION_SLOTS",
|
|
|
23ec99 |
+ .desc = "Count of floating point execution slots used for"
|
|
|
23ec99 |
+ " finished Binary Coded Decimal to Decimal Floating"
|
|
|
23ec99 |
+ " Point conversions. Instructions: CDZT, CXZT, CZDT,"
|
|
|
23ec99 |
+ " CZXT",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 225,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "VX_BCD_EXECUTION_SLOTS",
|
|
|
23ec99 |
+ .desc = "Count of floating point execution slots used for"
|
|
|
23ec99 |
+ " finished vector arithmetic Binary Coded Decimal"
|
|
|
23ec99 |
+ " instructions. Instructions: VAP, VSP, VMPVMSP, VDP,"
|
|
|
23ec99 |
+ " VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ,"
|
|
|
23ec99 |
+ " VCVB, VCVBG, VCVDVCVDG",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 226,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "DECIMAL_INSTRUCTIONS",
|
|
|
23ec99 |
+ .desc = "Decimal instructions dispatched. Instructions: CVB,"
|
|
|
23ec99 |
+ " CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 232,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "LAST_HOST_TRANSLATIONS",
|
|
|
23ec99 |
+ .desc = "Last Host Translation done",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 243,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_NC_TABORT",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a non-"
|
|
|
23ec99 |
+ " constrained transactional-execution mode",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 244,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_C_TABORT_NO_SPECIAL",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a constrained"
|
|
|
23ec99 |
+ " transactional-execution mode and the CPU is not"
|
|
|
23ec99 |
+ " using any special logic to allow the transaction to"
|
|
|
23ec99 |
+ " complete",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 245,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_EXTENDED,
|
|
|
23ec99 |
+ .name = "TX_C_TABORT_SPECIAL",
|
|
|
23ec99 |
+ .desc = "A transaction abort has occurred in a constrained"
|
|
|
23ec99 |
+ " transactional-execution mode and the CPU is using"
|
|
|
23ec99 |
+ " special logic to allow the transaction to complete",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 448,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_MT_DIAG,
|
|
|
23ec99 |
+ .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
|
|
23ec99 |
+ .desc = "Cycle count with one thread active",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ .ctrnum = 449,
|
|
|
23ec99 |
+ .ctrset = CPUMF_CTRSET_MT_DIAG,
|
|
|
23ec99 |
+ .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
|
|
23ec99 |
+ .desc = "Cycle count with two threads active",
|
|
|
23ec99 |
+ },
|
|
|
23ec99 |
+};
|
|
|
23ec99 |
+
|
|
|
23ec99 |
static const pme_cpumf_ctr_t cpumsf_counters[] = {
|
|
|
23ec99 |
{
|
|
|
23ec99 |
.ctrnum = 720896,
|
|
|
23ec99 |
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
index 7273962..62b1457 100644
|
|
|
23ec99 |
--- a/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
+++ b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
@@ -37,6 +37,8 @@
|
|
|
23ec99 |
#define CPUM_CF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_cf"
|
|
|
23ec99 |
#define CPUM_SF_DEVICE_DIR "/sys/bus/event_source/devices/cpum_sf"
|
|
|
23ec99 |
#define SYS_INFO "/proc/sysinfo"
|
|
|
23ec99 |
+#define SERVICE_LEVEL "/proc/service_levels"
|
|
|
23ec99 |
+#define CF_VERSION_STR "CPU-MF: Counter facility: version="
|
|
|
23ec99 |
|
|
|
23ec99 |
|
|
|
23ec99 |
/* CPU-measurement counter list (pmu events) */
|
|
|
23ec99 |
@@ -99,6 +101,37 @@ out:
|
|
|
23ec99 |
return machine_type;
|
|
|
23ec99 |
}
|
|
|
23ec99 |
|
|
|
23ec99 |
+static void get_cf_version(unsigned int *cfvn, unsigned int *csvn)
|
|
|
23ec99 |
+{
|
|
|
23ec99 |
+ int rc;
|
|
|
23ec99 |
+ FILE *fp;
|
|
|
23ec99 |
+ char *buffer;
|
|
|
23ec99 |
+ size_t buflen;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ *cfvn = *csvn = 0;
|
|
|
23ec99 |
+ fp = fopen(SERVICE_LEVEL, "r");
|
|
|
23ec99 |
+ if (fp == NULL)
|
|
|
23ec99 |
+ return;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ buffer = NULL;
|
|
|
23ec99 |
+ while (pfmlib_getl(&buffer, &buflen, fp) != -1) {
|
|
|
23ec99 |
+ /* skip empty lines */
|
|
|
23ec99 |
+ if (*buffer == '\n')
|
|
|
23ec99 |
+ continue;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ /* look for 'CPU-MF: Counter facility: version=' entry */
|
|
|
23ec99 |
+ if (!strncmp(CF_VERSION_STR, buffer, strlen(CF_VERSION_STR))) {
|
|
|
23ec99 |
+ rc = sscanf(buffer + strlen(CF_VERSION_STR), "%u.%u",
|
|
|
23ec99 |
+ cfvn, csvn);
|
|
|
23ec99 |
+ if (rc != 2)
|
|
|
23ec99 |
+ *cfvn = *csvn = 0;
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
+ }
|
|
|
23ec99 |
+ }
|
|
|
23ec99 |
+ fclose(fp);
|
|
|
23ec99 |
+ free(buffer);
|
|
|
23ec99 |
+}
|
|
|
23ec99 |
+
|
|
|
23ec99 |
/* Initialize the PMU representation for CPUMF.
|
|
|
23ec99 |
*
|
|
|
23ec99 |
* Set up the PMU events array based on
|
|
|
23ec99 |
@@ -108,8 +141,33 @@ out:
|
|
|
23ec99 |
static int pfm_cpumcf_init(void *this)
|
|
|
23ec99 |
{
|
|
|
23ec99 |
pfmlib_pmu_t *pmu = this;
|
|
|
23ec99 |
- const pme_cpumf_ctr_t *ext_set;
|
|
|
23ec99 |
- size_t generic_count, ext_set_count;
|
|
|
23ec99 |
+ unsigned int cfvn, csvn;
|
|
|
23ec99 |
+ const pme_cpumf_ctr_t *cfvn_set, *csvn_set, *ext_set;
|
|
|
23ec99 |
+ size_t cfvn_set_count, csvn_set_count, ext_set_count, pme_count;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ /* obtain counter first/second version number */
|
|
|
23ec99 |
+ get_cf_version(&cfvn, &csvn);
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ /* counters based on first version number */
|
|
|
23ec99 |
+ switch (cfvn)
|
|
|
23ec99 |
+ {
|
|
|
23ec99 |
+ case 1:
|
|
|
23ec99 |
+ cfvn_set = cpumcf_fvn1_counters;
|
|
|
23ec99 |
+ cfvn_set_count = LIBPFM_ARRAY_SIZE(cpumcf_fvn1_counters);
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
+ case 3:
|
|
|
23ec99 |
+ cfvn_set = cpumcf_fvn3_counters;
|
|
|
23ec99 |
+ cfvn_set_count = LIBPFM_ARRAY_SIZE(cpumcf_fvn3_counters);
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
+ default:
|
|
|
23ec99 |
+ cfvn_set = NULL;
|
|
|
23ec99 |
+ cfvn_set_count = 0;
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
+ }
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ /* counters based on second version number */
|
|
|
23ec99 |
+ csvn_set = cpumcf_svn_generic_counters;
|
|
|
23ec99 |
+ csvn_set_count = LIBPFM_ARRAY_SIZE(cpumcf_svn_generic_counters);
|
|
|
23ec99 |
|
|
|
23ec99 |
/* check and assign a machine-specific extended counter set */
|
|
|
23ec99 |
switch (get_machine_type()) {
|
|
|
23ec99 |
@@ -133,6 +191,10 @@ static int pfm_cpumcf_init(void *this)
|
|
|
23ec99 |
ext_set = cpumcf_z13_counters;
|
|
|
23ec99 |
ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z13_counters);
|
|
|
23ec99 |
break;
|
|
|
23ec99 |
+ case 3906: /* IBM z14 */
|
|
|
23ec99 |
+ ext_set = cpumcf_z14_counters;
|
|
|
23ec99 |
+ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z14_counters);
|
|
|
23ec99 |
+ break;
|
|
|
23ec99 |
default:
|
|
|
23ec99 |
/* No extended counter set for this machine type or there
|
|
|
23ec99 |
* was an error retrieving the machine type */
|
|
|
23ec99 |
@@ -141,20 +203,30 @@ static int pfm_cpumcf_init(void *this)
|
|
|
23ec99 |
break;
|
|
|
23ec99 |
}
|
|
|
23ec99 |
|
|
|
23ec99 |
- generic_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters);
|
|
|
23ec99 |
-
|
|
|
23ec99 |
- cpumcf_pe = calloc(sizeof(*cpumcf_pe), generic_count + ext_set_count);
|
|
|
23ec99 |
+ cpumcf_pe = calloc(sizeof(*cpumcf_pe),
|
|
|
23ec99 |
+ cfvn_set_count + csvn_set_count + ext_set_count);
|
|
|
23ec99 |
if (cpumcf_pe == NULL)
|
|
|
23ec99 |
return PFM_ERR_NOMEM;
|
|
|
23ec99 |
|
|
|
23ec99 |
- memcpy(cpumcf_pe, cpumcf_generic_counters,
|
|
|
23ec99 |
- sizeof(*cpumcf_pe) * generic_count);
|
|
|
23ec99 |
+ pme_count = 0;
|
|
|
23ec99 |
+ memcpy(cpumcf_pe, cfvn_set, sizeof(*cpumcf_pe) * cfvn_set_count);
|
|
|
23ec99 |
+ pme_count += cfvn_set_count;
|
|
|
23ec99 |
+ memcpy((void *) (cpumcf_pe + pme_count), csvn_set,
|
|
|
23ec99 |
+ sizeof(*cpumcf_pe) * csvn_set_count);
|
|
|
23ec99 |
+ pme_count += csvn_set_count;
|
|
|
23ec99 |
if (ext_set_count)
|
|
|
23ec99 |
- memcpy((void *) (cpumcf_pe + generic_count),
|
|
|
23ec99 |
+ memcpy((void *) (cpumcf_pe + pme_count),
|
|
|
23ec99 |
ext_set, sizeof(*cpumcf_pe) * ext_set_count);
|
|
|
23ec99 |
+ pme_count += ext_set_count;
|
|
|
23ec99 |
|
|
|
23ec99 |
pmu->pe = cpumcf_pe;
|
|
|
23ec99 |
- pmu->pme_count = generic_count + ext_set_count;
|
|
|
23ec99 |
+ pmu->pme_count = pme_count;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ /* CPUM-CF provides fixed counters only. The number of installed
|
|
|
23ec99 |
+ * counters depends on the version and hardware model up to
|
|
|
23ec99 |
+ * CPUMF_COUNTER_MAX.
|
|
|
23ec99 |
+ */
|
|
|
23ec99 |
+ pmu->num_fixed_cntrs = pme_count;
|
|
|
23ec99 |
|
|
|
23ec99 |
return PFM_SUCCESS;
|
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|
23ec99 |
}
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23ec99 |
@@ -276,8 +348,8 @@ pfmlib_pmu_t s390x_cpum_cf_support = {
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|
23ec99 |
.num_fixed_cntrs = CPUMF_COUNTER_MAX, /* fixed counters only */
|
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|
23ec99 |
.max_encoding = 1,
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|
23ec99 |
|
|
|
23ec99 |
- .pe = cpumcf_generic_counters,
|
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|
23ec99 |
- .pme_count = LIBPFM_ARRAY_SIZE(cpumcf_generic_counters),
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23ec99 |
+ .pe = NULL,
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23ec99 |
+ .pme_count = 0,
|
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23ec99 |
|
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23ec99 |
.pmu_detect = pfm_cpumcf_detect,
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23ec99 |
.pmu_init = pfm_cpumcf_init,
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23ec99 |
diff --git a/lib/pfmlib_s390x_priv.h b/lib/pfmlib_s390x_priv.h
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23ec99 |
index 22c775a..48a96c3 100644
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|
23ec99 |
--- a/lib/pfmlib_s390x_priv.h
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|
23ec99 |
+++ b/lib/pfmlib_s390x_priv.h
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|
|
23ec99 |
@@ -1,7 +1,7 @@
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23ec99 |
#ifndef __PFMLIB_S390X_PRIV_H__
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23ec99 |
#define __PFMLIB_S390X_PRIV_H__
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23ec99 |
|
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23ec99 |
-#define CPUMF_COUNTER_MAX 256
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|
23ec99 |
+#define CPUMF_COUNTER_MAX 0xffff
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|
|
23ec99 |
typedef struct {
|
|
|
23ec99 |
uint64_t ctrnum; /* counter number */
|
|
|
23ec99 |
unsigned int ctrset; /* counter set */
|
|
|
23ec99 |
commit 31ab4b33773750fbd13a1824e485805b70fc0bff
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|
23ec99 |
Author: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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|
|
23ec99 |
Date: Fri Feb 9 09:42:07 2018 +0100
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|
|
23ec99 |
|
|
|
23ec99 |
s390/cpumf: check for counter facility availability
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|
23ec99 |
|
|
|
23ec99 |
If the counter facility is not available, counter information
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|
|
23ec99 |
are not being set up. Introduce checks to protect against
|
|
|
23ec99 |
access to counter information in that case.
|
|
|
23ec99 |
|
|
|
23ec99 |
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
|
|
|
23ec99 |
|
|
|
23ec99 |
diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
index 62b1457..4e03fc4 100644
|
|
|
23ec99 |
--- a/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
+++ b/lib/pfmlib_s390x_cpumf.c
|
|
|
23ec99 |
@@ -254,7 +254,9 @@ static int pfm_cpumf_get_encoding(void *this, pfmlib_event_desc_t *e)
|
|
|
23ec99 |
|
|
|
23ec99 |
static int pfm_cpumf_get_event_first(void *this)
|
|
|
23ec99 |
{
|
|
|
23ec99 |
- return 0;
|
|
|
23ec99 |
+ pfmlib_pmu_t *pmu = this;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
+ return !!pmu->pme_count ? 0 : -1;
|
|
|
23ec99 |
}
|
|
|
23ec99 |
|
|
|
23ec99 |
static int pfm_cpumf_get_event_next(void *this, int idx)
|
|
|
23ec99 |
@@ -317,6 +319,9 @@ static int pfm_cpumf_get_event_info(void *this, int idx,
|
|
|
23ec99 |
pfmlib_pmu_t *pmu = this;
|
|
|
23ec99 |
const pme_cpumf_ctr_t *pe = this_pe(this);
|
|
|
23ec99 |
|
|
|
23ec99 |
+ if (idx >= pmu->pme_count)
|
|
|
23ec99 |
+ return PFM_ERR_INVAL;
|
|
|
23ec99 |
+
|
|
|
23ec99 |
info->name = pe[idx].name;
|
|
|
23ec99 |
info->desc = pe[idx].desc;
|
|
|
23ec99 |
info->code = pe[idx].ctrnum;
|