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commit a637b532a405aa3c8c210f21f925e87c11bbeb3f
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Author: Carl Love <cel@us.ibm.com>
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Date: Mon Jun 17 22:11:44 2013 +0200
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Add IBM Power 8 support
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This patch adds support for the Power 8 CPU events to the
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libpfm4 library.
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Signed-off-by: Carl Love <cel@us.ibm.com>
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diff --git a/README b/README
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index 74cc89f..905b768 100644
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--- a/README
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+++ b/README
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@@ -67,6 +67,7 @@ The library supports many PMUs. The current version can handle:
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Power 5
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Power 6
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Power 7
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+ Power 8
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PPC970
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Torrent
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System z (s390x)
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diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
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index 709048c..89b9fd8 100644
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--- a/include/perfmon/pfmlib.h
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+++ b/include/perfmon/pfmlib.h
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@@ -190,6 +190,8 @@ typedef enum {
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PFM_PMU_INTEL_IVB_UNC_CB2, /* Intel IvyBridge C-box 2 uncore PMU */
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PFM_PMU_INTEL_IVB_UNC_CB3, /* Intel IvyBridge C-box 3 uncore PMU */
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+ PFM_PMU_POWER8, /* IBM POWER8 */
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+
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/* MUST ADD NEW PMU MODELS HERE */
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PFM_PMU_MAX /* end marker */
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diff --git a/lib/Makefile b/lib/Makefile
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index a103927..98411b8 100644
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--- a/lib/Makefile
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+++ b/lib/Makefile
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@@ -95,7 +95,7 @@ SRCS += pfmlib_powerpc_perf_event.c
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endif
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INCARCH = $(INC_POWERPC)
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-SRCS += pfmlib_powerpc.c pfmlib_power4.c pfmlib_ppc970.c pfmlib_power5.c pfmlib_power6.c pfmlib_power7.c pfmlib_torrent.c
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+SRCS += pfmlib_powerpc.c pfmlib_power4.c pfmlib_ppc970.c pfmlib_power5.c pfmlib_power6.c pfmlib_power7.c pfmlib_torrent.c pfmlib_power8.c
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CFLAGS += -DCONFIG_PFMLIB_ARCH_POWERPC
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endif
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@@ -227,6 +227,7 @@ INC_POWERPC=events/ppc970_events.h \
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events/power5+_events.h \
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events/power6_events.h \
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events/power7_events.h \
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+ events/power8_events.h \
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events/torrent_events.h
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INC_S390X=pfmlib_s390x_priv.h \
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diff --git a/lib/events/power8_events.h b/lib/events/power8_events.h
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new file mode 100644
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index 0000000..25945f3
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--- /dev/null
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+++ b/lib/events/power8_events.h
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@@ -0,0 +1,1009 @@
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+/****************************/
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+/* THIS IS OPEN SOURCE CODE */
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+/****************************/
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+
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+#ifndef __POWER8_EVENTS_H__
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+#define __POWER8_EVENTS_H__
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+
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+/*
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+* File: power8_events.h
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+* CVS:
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+Author: Carl Love
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+* carll.ibm.com
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+* Mods: <your name here>
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+* <your email address>
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+*
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+* (C) Copyright IBM Corporation, 2013. All Rights Reserved.
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+* Contributed by
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+*
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+* Note: This code was automatically generated and should not be modified by
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+* hand.
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+*
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+* Documentation on the PMU events will be published at:
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+* http://www.power.org/documentation
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+*/
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+
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+#define POWER8_PME_PM_1PLUS_PPC_CMPL 0
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+#define POWER8_PME_PM_1PLUS_PPC_DISP 1
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+#define POWER8_PME_PM_ANY_THRD_RUN_CYC 2
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+#define POWER8_PME_PM_BR_MPRED_CMPL 3
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+#define POWER8_PME_PM_BR_TAKEN_CMPL 4
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+#define POWER8_PME_PM_CYC 5
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+#define POWER8_PME_PM_DATA_FROM_L2MISS 6
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+#define POWER8_PME_PM_DATA_FROM_L3MISS 7
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+#define POWER8_PME_PM_DATA_FROM_MEM 8
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+#define POWER8_PME_PM_DTLB_MISS 9
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+#define POWER8_PME_PM_EXT_INT 10
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+#define POWER8_PME_PM_FLOP 11
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+#define POWER8_PME_PM_FLUSH 12
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+#define POWER8_PME_PM_GCT_NOSLOT_CYC 13
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+#define POWER8_PME_PM_IERAT_MISS 14
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+#define POWER8_PME_PM_INST_DISP 15
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+#define POWER8_PME_PM_INST_FROM_L3MISS 16
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+#define POWER8_PME_PM_ITLB_MISS 17
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+#define POWER8_PME_PM_L1_DCACHE_RELOAD_VALID 18
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+#define POWER8_PME_PM_L1_ICACHE_MISS 19
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+#define POWER8_PME_PM_LD_MISS_L1 20
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+#define POWER8_PME_PM_LSU_DERAT_MISS 21
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+#define POWER8_PME_PM_MRK_BR_MPRED_CMPL 22
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+#define POWER8_PME_PM_MRK_BR_TAKEN_CMPL 23
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS 24
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS 25
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+#define POWER8_PME_PM_MRK_DATA_FROM_MEM 26
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+#define POWER8_PME_PM_MRK_DERAT_MISS 27
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+#define POWER8_PME_PM_MRK_DTLB_MISS 28
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+#define POWER8_PME_PM_MRK_INST_CMPL 29
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+#define POWER8_PME_PM_MRK_INST_DISP 30
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+#define POWER8_PME_PM_MRK_INST_FROM_L3MISS 31
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+#define POWER8_PME_PM_MRK_L1_ICACHE_MISS 32
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+#define POWER8_PME_PM_MRK_L1_RELOAD_VALID 33
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+#define POWER8_PME_PM_MRK_LD_MISS_L1 34
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+#define POWER8_PME_PM_MRK_ST_CMPL 35
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+#define POWER8_PME_PM_RUN_CYC 36
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+#define POWER8_PME_PM_RUN_INST_CMPL 37
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+#define POWER8_PME_PM_RUN_PURR 38
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+#define POWER8_PME_PM_ST_FIN 39
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+#define POWER8_PME_PM_ST_MISS_L1 40
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+#define POWER8_PME_PM_TB_BIT_TRANS 41
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+#define POWER8_PME_PM_THRD_CONC_RUN_INST 42
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+#define POWER8_PME_PM_THRESH_EXC_1024 43
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+#define POWER8_PME_PM_THRESH_EXC_128 44
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+#define POWER8_PME_PM_THRESH_EXC_2048 45
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+#define POWER8_PME_PM_THRESH_EXC_256 46
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+#define POWER8_PME_PM_THRESH_EXC_32 47
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+#define POWER8_PME_PM_THRESH_EXC_4096 48
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+#define POWER8_PME_PM_THRESH_EXC_512 49
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+#define POWER8_PME_PM_THRESH_EXC_64 50
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+#define POWER8_PME_PM_THRESH_MET 51
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+#define POWER8_PME_PM_BR_2PATH 52
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+#define POWER8_PME_PM_BR_CMPL 53
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+#define POWER8_PME_PM_BR_MRK_2PATH 54
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+#define POWER8_PME_PM_CMPLU_STALL 55
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+#define POWER8_PME_PM_CMPLU_STALL_BRU 56
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+#define POWER8_PME_PM_CMPLU_STALL_BRU_CRU 57
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+#define POWER8_PME_PM_CMPLU_STALL_COQ_FULL 58
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+#define POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS 59
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 60
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 61
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 62
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS 63
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM 64
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+#define POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE 65
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+#define POWER8_PME_PM_CMPLU_STALL_ERAT_MISS 66
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+#define POWER8_PME_PM_CMPLU_STALL_FLUSH 67
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+#define POWER8_PME_PM_CMPLU_STALL_FXLONG 68
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+#define POWER8_PME_PM_CMPLU_STALL_FXU 69
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+#define POWER8_PME_PM_CMPLU_STALL_HWSYNC 70
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+#define POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH 71
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+#define POWER8_PME_PM_CMPLU_STALL_LSU 72
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+#define POWER8_PME_PM_CMPLU_STALL_LWSYNC 73
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+#define POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY 74
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+#define POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH 75
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+#define POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL 76
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+#define POWER8_PME_PM_CMPLU_STALL_REJECT 77
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+#define POWER8_PME_PM_CMPLU_STALL_REJECT_LHS 78
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+#define POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL 79
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+#define POWER8_PME_PM_CMPLU_STALL_SCALAR 80
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+#define POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG 81
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+#define POWER8_PME_PM_CMPLU_STALL_STORE 82
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+#define POWER8_PME_PM_CMPLU_STALL_ST_FWD 83
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+#define POWER8_PME_PM_CMPLU_STALL_THRD 84
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+#define POWER8_PME_PM_CMPLU_STALL_VECTOR 85
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+#define POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG 86
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+#define POWER8_PME_PM_CMPLU_STALL_VSU 87
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+#define POWER8_PME_PM_DATA_FROM_L2 88
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+#define POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT 89
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+#define POWER8_PME_PM_DATA_FROM_L3 90
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+#define POWER8_PME_PM_DATA_FROM_L3MISS_MOD 91
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+#define POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT 92
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+#define POWER8_PME_PM_DATA_FROM_LMEM 93
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+#define POWER8_PME_PM_DATA_FROM_MEMORY 94
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+#define POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF 95
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+#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED 96
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+#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS 97
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+#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ 98
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+#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER 99
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+#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ 100
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+#define POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS 101
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+#define POWER8_PME_PM_GCT_NOSLOT_IC_MISS 102
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+#define POWER8_PME_PM_GRP_DISP 103
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+#define POWER8_PME_PM_GRP_MRK 104
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+#define POWER8_PME_PM_HV_CYC 105
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+#define POWER8_PME_PM_INST_CMPL 106
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+#define POWER8_PME_PM_IOPS_CMPL 107
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+#define POWER8_PME_PM_LD_CMPL 108
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+#define POWER8_PME_PM_LD_L3MISS_PEND_CYC 109
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2 110
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC 111
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2_CYC 112
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 113
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+#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 114
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3 115
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC 116
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3_CYC 117
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 118
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+#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 119
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+#define POWER8_PME_PM_MRK_DATA_FROM_LL4 120
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+#define POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC 121
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+#define POWER8_PME_PM_MRK_DATA_FROM_LMEM 122
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+#define POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC 123
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+#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY 124
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+#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC 125
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+#define POWER8_PME_PM_MRK_GRP_CMPL 126
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+#define POWER8_PME_PM_MRK_INST_DECODED 127
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+#define POWER8_PME_PM_MRK_L2_RC_DISP 128
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+#define POWER8_PME_PM_MRK_LD_MISS_L1_CYC 129
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+#define POWER8_PME_PM_MRK_STALL_CMPLU_CYC 130
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f1d3e6 |
+#define POWER8_PME_PM_NEST_REF_CLK 131
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PMC1_OVERFLOW 132
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PMC2_OVERFLOW 133
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PMC3_OVERFLOW 134
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PMC4_OVERFLOW 135
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PMC6_OVERFLOW 136
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_PPC_CMPL 137
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_THRD_ALL_RUN_CYC 138
|
|
|
f1d3e6 |
+#define POWER8_PME_PM_THRESH_NOT_MET 139
|
|
|
f1d3e6 |
+
|
|
|
f1d3e6 |
+static const pme_power_entry_t power8_pe[] = {
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_1PLUS_PPC_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_1PLUS_PPC_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x100f2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "one or more ppc instructions completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "one or more ppc instructions finished",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_1PLUS_PPC_DISP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_1PLUS_PPC_DISP",
|
|
|
f1d3e6 |
+ .pme_code = 0x400f2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Cycles at least one Instr Dispatched",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Cycles at least one Instr Dispatched",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_ANY_THRD_RUN_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_ANY_THRD_RUN_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x100fa,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Any thread in run_cycles (was one thread in run_cycles)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "One of threads in run_cycles",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_BR_MPRED_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_BR_MPRED_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x400f6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Number of Branch Mispredicts",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Number of Branch Mispredicts",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_BR_TAKEN_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_BR_TAKEN_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x200fa,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Branch Taken",
|
|
|
f1d3e6 |
+ .pme_long_desc = "New event for Branch Taken",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x100f0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Cycles",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Cycles",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L2MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L2MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x200fe,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Demand LD - L2 Miss (not L2 hit)",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x300fe,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_MEM ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_MEM",
|
|
|
f1d3e6 |
+ .pme_code = 0x400fe,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Data cache reload from memory (including L4)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "data from Memory",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DTLB_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DTLB_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x300fc,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Data PTEG Reloaded (DTLB Miss)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Data PTEG reload",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_EXT_INT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_EXT_INT",
|
|
|
f1d3e6 |
+ .pme_code = 0x200f8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "external interrupt",
|
|
|
f1d3e6 |
+ .pme_long_desc = "external interrupt",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_FLOP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_FLOP",
|
|
|
f1d3e6 |
+ .pme_code = 0x100f4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Floating Point Operations Finished",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Floating Point Operations Finished",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_FLUSH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_FLUSH",
|
|
|
f1d3e6 |
+ .pme_code = 0x400f8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Flush (any type)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Flush (any type)",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x100f8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Pipeline empty (No itags assigned , no GCT slots used)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "No itags assigned",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_IERAT_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_IERAT_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x100f6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "IERAT Reloaded (Miss)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Cycles Instruction ERAT was reloaded",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_INST_DISP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_INST_DISP",
|
|
|
f1d3e6 |
+ .pme_code = 0x200f2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Number of PPC Dispatched",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Number of PPC Dispatched",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_INST_FROM_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_INST_FROM_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x300fa,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Inst from L3 miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "A Instruction cacheline request resolved from a location that was beyond the local L3 cache",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_ITLB_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_ITLB_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x400fc,
|
|
|
f1d3e6 |
+ .pme_short_desc = "ITLB Reloaded",
|
|
|
f1d3e6 |
+ .pme_long_desc = "ITLB Reloaded (always zero on POWER6)",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_L1_DCACHE_RELOAD_VALID",
|
|
|
f1d3e6 |
+ .pme_code = 0x300f6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "DL1 reloaded due to Demand Load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "DL1 reloaded due to Demand Load",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_L1_ICACHE_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_L1_ICACHE_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x200fc,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Demand iCache Miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Demand iCache Miss",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_LD_MISS_L1 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_LD_MISS_L1",
|
|
|
f1d3e6 |
+ .pme_code = 0x400f0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Load Missed L1",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Load Missed L1",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_LSU_DERAT_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_LSU_DERAT_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x200f6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "DERAT Reloaded (Miss)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "DERAT Reloaded due to a DERAT miss",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_BR_MPRED_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_BR_MPRED_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x300e4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked Branch Mispredicted",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked Branch Mispredicted",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_BR_TAKEN_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_BR_TAKEN_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x100e2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked Branch Taken",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked Branch Taken completed",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x400e8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Data cache reload L2 miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled load resolved beyond L2",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x200e4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled load resolved beyond L3",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_MEM ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_MEM",
|
|
|
f1d3e6 |
+ .pme_code = 0x200e0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled load resolved from memory",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DERAT_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DERAT_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x300e6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Erat Miss (TLB Access) All page sizes",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Erat Miss (TLB Access) All page sizes",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DTLB_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DTLB_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x400e4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked dtlb miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled Instruction dtlb miss",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_INST_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_INST_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x400e0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "marked instruction completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked group complete",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_INST_DISP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_INST_DISP",
|
|
|
f1d3e6 |
+ .pme_code = 0x100e0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked Instruction dispatched",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The thread has dispatched a randomly sampled marked instruction",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_INST_FROM_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_INST_FROM_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x400e6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_L1_ICACHE_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_L1_ICACHE_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x100e4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked L1 Icache Miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "sampled Instruction suffered an icache Miss",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_L1_RELOAD_VALID ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_L1_RELOAD_VALID",
|
|
|
f1d3e6 |
+ .pme_code = 0x100ea,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked demand reload",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Sampled Instruction had a data reload",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_LD_MISS_L1 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_LD_MISS_L1",
|
|
|
f1d3e6 |
+ .pme_code = 0x200e2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked DL1 Demand Miss counted at exec time",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked DL1 Demand Miss",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_ST_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_ST_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x300e2,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked store completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "marked store completed and sent to nest",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_RUN_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_RUN_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x600f4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Run_cycles",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Run_cycles",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_RUN_INST_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_RUN_INST_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x500fa,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Run_Instructions",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Run_Instructions",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_RUN_PURR ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_RUN_PURR",
|
|
|
f1d3e6 |
+ .pme_code = 0x400f4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Run_PURR",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Run_PURR",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_ST_FIN ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_ST_FIN",
|
|
|
f1d3e6 |
+ .pme_code = 0x200f0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Store Instructions Finished (store sent to nest)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Store Instructions Finished",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_ST_MISS_L1 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_ST_MISS_L1",
|
|
|
f1d3e6 |
+ .pme_code = 0x300f0,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Store Missed L1",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Store Missed L1",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_TB_BIT_TRANS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_TB_BIT_TRANS",
|
|
|
f1d3e6 |
+ .pme_code = 0x300f8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "timebase event",
|
|
|
f1d3e6 |
+ .pme_long_desc = "timebase event",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRD_CONC_RUN_INST ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRD_CONC_RUN_INST",
|
|
|
f1d3e6 |
+ .pme_code = 0x300f4,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Concurrent Run Instructions",
|
|
|
f1d3e6 |
+ .pme_long_desc = "PPC Instructions Finished when both threads in run_cycles",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_1024 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_1024",
|
|
|
f1d3e6 |
+ .pme_code = 0x300ea,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_128 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_128",
|
|
|
f1d3e6 |
+ .pme_code = 0x400ea,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 128",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_2048 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_2048",
|
|
|
f1d3e6 |
+ .pme_code = 0x400ec,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 2048",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_256 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_256",
|
|
|
f1d3e6 |
+ .pme_code = 0x100e8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceed a count of 256",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_32 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_32",
|
|
|
f1d3e6 |
+ .pme_code = 0x200e6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 32",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_4096 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_4096",
|
|
|
f1d3e6 |
+ .pme_code = 0x100e6,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceed a count of 4096",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_512 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_512",
|
|
|
f1d3e6 |
+ .pme_code = 0x200e8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_EXC_64 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_EXC_64",
|
|
|
f1d3e6 |
+ .pme_code = 0x300e8,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_MET ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_MET",
|
|
|
f1d3e6 |
+ .pme_code = 0x100ec,
|
|
|
f1d3e6 |
+ .pme_short_desc = "threshold exceeded",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Threshold exceeded",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_BR_2PATH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_BR_2PATH",
|
|
|
f1d3e6 |
+ .pme_code = 0x40036,
|
|
|
f1d3e6 |
+ .pme_short_desc = "two path branch",
|
|
|
f1d3e6 |
+ .pme_long_desc = "two path branch.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_BR_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_BR_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x40060,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Branch Instruction completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Branch Instruction completed.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_BR_MRK_2PATH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_BR_MRK_2PATH",
|
|
|
f1d3e6 |
+ .pme_code = 0x40138,
|
|
|
f1d3e6 |
+ .pme_short_desc = "marked two path branch",
|
|
|
f1d3e6 |
+ .pme_long_desc = "marked two path branch.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL",
|
|
|
f1d3e6 |
+ .pme_code = 0x1e054,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_BRU ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_BRU",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d018,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to a Branch Unit",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to a Branch Unit.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_BRU_CRU ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_BRU_CRU",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d018,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to IFU",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to IFU.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_COQ_FULL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_COQ_FULL",
|
|
|
f1d3e6 |
+ .pme_code = 0x30026,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to CO q full",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to CO q full.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c012,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by Dcache miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by Dcache miss.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_L21_L31",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c018,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_L2L3",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c016,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c016,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to cache miss due to L2 l3 conflict",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to cache miss resolving in core's L2/L3 with a conflict.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c01a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to cache miss resolving missed the L3",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to cache miss resolving missed the L3.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_LMEM",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c018,
|
|
|
f1d3e6 |
+ .pme_short_desc = "GCT empty by branch mispredict + IC miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to cache miss resolving in core's Local Memory.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_DMISS_REMOTE",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c01c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_ERAT_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c012,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to LSU reject ERAT miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to LSU reject ERAT miss.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_FLUSH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_FLUSH",
|
|
|
f1d3e6 |
+ .pme_code = 0x30038,
|
|
|
f1d3e6 |
+ .pme_short_desc = "completion stall due to flush by own thread",
|
|
|
f1d3e6 |
+ .pme_long_desc = "completion stall due to flush by own thread.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_FXLONG ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_FXLONG",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d016,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to a long latency fixed point instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to a long latency fixed point instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_FXU ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_FXU",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d016,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to FXU",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to FXU.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_HWSYNC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_HWSYNC",
|
|
|
f1d3e6 |
+ .pme_code = 0x30036,
|
|
|
f1d3e6 |
+ .pme_short_desc = "completion stall due to hwsync",
|
|
|
f1d3e6 |
+ .pme_long_desc = "completion stall due to hwsync.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_LOAD_FINISH",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d014,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to a Load finish",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to a Load finish.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_LSU ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_LSU",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by LSU instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by LSU instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_LWSYNC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_LWSYNC",
|
|
|
f1d3e6 |
+ .pme_code = 0x10036,
|
|
|
f1d3e6 |
+ .pme_short_desc = "completion stall due to isync/lwsync",
|
|
|
f1d3e6 |
+ .pme_long_desc = "completion stall due to isync/lwsync.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_MEM_ECC_DELAY",
|
|
|
f1d3e6 |
+ .pme_code = 0x30028,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to mem ECC delay",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to mem ECC delay.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_NTCG_FLUSH",
|
|
|
f1d3e6 |
+ .pme_code = 0x2e01e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to ntcg flush",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to reject (load hit store).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_OTHER_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x30006,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Instructions core completed while this thread was stalled.",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Instructions core completed while this thread was stalled.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_REJECT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_REJECT",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to LSU reject",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to LSU reject.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_REJECT_LHS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_REJECT_LHS",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c01a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to reject (load hit store)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to reject (load hit store).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_REJ_LMQ_FULL",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c014,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to LSU reject LMQ full",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to LSU reject LMQ full.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_SCALAR ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_SCALAR",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to VSU scalar instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to VSU scalar instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_SCALAR_LONG",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to VSU scalar long latency instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to VSU scalar long latency instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_STORE ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_STORE",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c014,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall by stores this includes store agent finishes in pipe LS0/LS1 and store data finishes in LS2/LS3",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall by stores.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_ST_FWD ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_ST_FWD",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c01c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to store forward",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to store forward.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_THRD ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_THRD",
|
|
|
f1d3e6 |
+ .pme_code = 0x1001c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to thread conflict.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_VECTOR ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_VECTOR",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d014,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to VSU vector instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to VSU vector instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_VECTOR_LONG",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d012,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to VSU vector long instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to VSU vector long instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_CMPLU_STALL_VSU ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_CMPLU_STALL_VSU",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d012,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Completion stall due to VSU instruction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Completion stall due to VSU instruction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L2 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L2",
|
|
|
f1d3e6 |
+ .pme_code = 0x1c042,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[16]",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[20].",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L2_NO_CONFLICT",
|
|
|
f1d3e6 |
+ .pme_code = 0x1c040,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16]",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20] .",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L3 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L3",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c042,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L3MISS_MOD ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L3MISS_MOD",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c04e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_L3_NO_CONFLICT",
|
|
|
f1d3e6 |
+ .pme_code = 0x1c044,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[16]",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20].",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_LMEM ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_LMEM",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c048,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DATA_FROM_MEMORY ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DATA_FROM_MEMORY",
|
|
|
f1d3e6 |
+ .pme_code = 0x2c04c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_DC_PREF_STREAM_STRIDED_CONF",
|
|
|
f1d3e6 |
+ .pme_code = 0x3e050,
|
|
|
f1d3e6 |
+ .pme_short_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.",
|
|
|
f1d3e6 |
+ .pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software..",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_BR_MPRED",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d01e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty fo this thread due to branch misprediction",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to branch misprediction.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_BR_MPRED_ICMISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d01a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to Icache Miss and branch mispred",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to Icache Miss and branch mispred.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_DISP_HELD_ISSQ",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d01e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_DISP_HELD_OTHER",
|
|
|
f1d3e6 |
+ .pme_code = 0x2e010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_DISP_HELD_SRQ",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d01c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_IC_L3MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x4e010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to icach l3 miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to icach l3 miss.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GCT_NOSLOT_IC_MISS ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GCT_NOSLOT_IC_MISS",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d01a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Gct empty for this thread due to Icache Miss",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Gct empty for this thread due to Icache Miss.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GRP_DISP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GRP_DISP",
|
|
|
f1d3e6 |
+ .pme_code = 0x3000a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "group dispatch",
|
|
|
f1d3e6 |
+ .pme_long_desc = "dispatch_success (Group Dispatched).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_GRP_MRK ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_GRP_MRK",
|
|
|
f1d3e6 |
+ .pme_code = 0x10130,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Instruction Marked",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Instruction marked in idu.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_HV_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_HV_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x2000a,
|
|
|
f1d3e6 |
+ .pme_short_desc = "cycles in hypervisor mode",
|
|
|
f1d3e6 |
+ .pme_long_desc = "cycles in hypervisor mode .",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_INST_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_INST_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x10002,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Number of PowerPC Instructions that completed.",
|
|
|
f1d3e6 |
+ .pme_long_desc = "PPC Instructions Finished (completed).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_IOPS_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_IOPS_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x10014,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Internal Operations completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "IOPS Completed.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_LD_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_LD_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x1002e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "count of Loads completed",
|
|
|
f1d3e6 |
+ .pme_long_desc = "count of Loads completed.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_LD_L3MISS_PEND_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_LD_L3MISS_PEND_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x10062,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Cycles L3 miss was pending for this thread",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Cycles L3 miss was pending for this thread.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2",
|
|
|
f1d3e6 |
+ .pme_code = 0x1d142,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c12e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c122,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
|
|
|
f1d3e6 |
+ .pme_code = 0x1d140,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c120,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d142,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d12e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d122,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
|
|
|
f1d3e6 |
+ .pme_code = 0x1d144,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c124,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_LL4 ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_LL4",
|
|
|
f1d3e6 |
+ .pme_code = 0x1d14c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_LL4_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4c12c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_LMEM ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_LMEM",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d148,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d128,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_MEMORY ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_MEMORY",
|
|
|
f1d3e6 |
+ .pme_code = 0x2d14c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4d12c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_GRP_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_GRP_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x40130,
|
|
|
f1d3e6 |
+ .pme_short_desc = "marked instruction finished (completed)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "marked instruction finished (completed).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_INST_DECODED ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_INST_DECODED",
|
|
|
f1d3e6 |
+ .pme_code = 0x20130,
|
|
|
f1d3e6 |
+ .pme_short_desc = "marked instruction decoded",
|
|
|
f1d3e6 |
+ .pme_long_desc = "marked instruction decoded. Name from ISU?",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_L2_RC_DISP ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_L2_RC_DISP",
|
|
|
f1d3e6 |
+ .pme_code = 0x20114,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked Instruction RC dispatched in L2",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked Instruction RC dispatched in L2.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_LD_MISS_L1_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_LD_MISS_L1_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x4013e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked ld latency",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked ld latency.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_MRK_STALL_CMPLU_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_MRK_STALL_CMPLU_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x3013e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Marked Group completion Stall",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_NEST_REF_CLK ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_NEST_REF_CLK",
|
|
|
f1d3e6 |
+ .pme_code = 0x3006e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Nest reference clocks",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Nest reference clocks.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PMC1_OVERFLOW ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PMC1_OVERFLOW",
|
|
|
f1d3e6 |
+ .pme_code = 0x20010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Overflow from counter 1",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Overflow from counter 1.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PMC2_OVERFLOW ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PMC2_OVERFLOW",
|
|
|
f1d3e6 |
+ .pme_code = 0x30010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Overflow from counter 2",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Overflow from counter 2.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PMC3_OVERFLOW ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PMC3_OVERFLOW",
|
|
|
f1d3e6 |
+ .pme_code = 0x40010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Overflow from counter 3",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Overflow from counter 3.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PMC4_OVERFLOW ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PMC4_OVERFLOW",
|
|
|
f1d3e6 |
+ .pme_code = 0x10010,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Overflow from counter 4",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Overflow from counter 4.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PMC6_OVERFLOW ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PMC6_OVERFLOW",
|
|
|
f1d3e6 |
+ .pme_code = 0x30024,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Overflow from counter 6",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Overflow from counter 6.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_PPC_CMPL ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_PPC_CMPL",
|
|
|
f1d3e6 |
+ .pme_code = 0x40002,
|
|
|
f1d3e6 |
+ .pme_short_desc = "PPC Instructions Finished (completed)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "PPC Instructions Finished (completed).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRD_ALL_RUN_CYC ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRD_ALL_RUN_CYC",
|
|
|
f1d3e6 |
+ .pme_code = 0x2000c,
|
|
|
f1d3e6 |
+ .pme_short_desc = "All Threads in Run_cycles (was both threads in run_cycles)",
|
|
|
f1d3e6 |
+ .pme_long_desc = "All Threads in Run_cycles (was both threads in run_cycles).",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+[ POWER8_PME_PM_THRESH_NOT_MET ] = {
|
|
|
f1d3e6 |
+ .pme_name = "PM_THRESH_NOT_MET",
|
|
|
f1d3e6 |
+ .pme_code = 0x4016e,
|
|
|
f1d3e6 |
+ .pme_short_desc = "Threshold counter did not meet threshold",
|
|
|
f1d3e6 |
+ .pme_long_desc = "Threshold counter did not meet threshold.",
|
|
|
f1d3e6 |
+},
|
|
|
f1d3e6 |
+};
|
|
|
f1d3e6 |
+#endif
|
|
|
f1d3e6 |
diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c
|
|
|
f1d3e6 |
index 7b11b46..71bddd9 100644
|
|
|
f1d3e6 |
--- a/lib/pfmlib_common.c
|
|
|
f1d3e6 |
+++ b/lib/pfmlib_common.c
|
|
|
f1d3e6 |
@@ -137,6 +137,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]=
|
|
|
f1d3e6 |
&power5p_support,
|
|
|
f1d3e6 |
&power6_support,
|
|
|
f1d3e6 |
&power7_support,
|
|
|
f1d3e6 |
+ &power8_support,
|
|
|
f1d3e6 |
&torrent_support,
|
|
|
f1d3e6 |
#endif
|
|
|
f1d3e6 |
|
|
|
f1d3e6 |
diff --git a/lib/pfmlib_power8.c b/lib/pfmlib_power8.c
|
|
|
f1d3e6 |
new file mode 100644
|
|
|
f1d3e6 |
index 0000000..d274b59
|
|
|
f1d3e6 |
--- /dev/null
|
|
|
f1d3e6 |
+++ b/lib/pfmlib_power8.c
|
|
|
f1d3e6 |
@@ -0,0 +1,57 @@
|
|
|
f1d3e6 |
+/*
|
|
|
f1d3e6 |
+ * pfmlib_power8.c : IBM Power8 support
|
|
|
f1d3e6 |
+ *
|
|
|
f1d3e6 |
+ * Copyright (C) IBM Corporation, 2013. All rights reserved.
|
|
|
f1d3e6 |
+ * Contributed by Carl Love (carll@us.ibm.com)
|
|
|
f1d3e6 |
+ *
|
|
|
f1d3e6 |
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
f1d3e6 |
+ * of this software and associated documentation files (the "Software"), to deal
|
|
|
f1d3e6 |
+ * in the Software without restriction, including without limitation the rights
|
|
|
f1d3e6 |
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
|
|
|
f1d3e6 |
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
|
|
|
f1d3e6 |
+ * subject to the following conditions:
|
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|
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+ *
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+ * The above copyright notice and this permission notice shall be included in all
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+ * copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+/* private headers */
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+#include "pfmlib_priv.h"
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+#include "pfmlib_power_priv.h"
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+#include "events/power8_events.h"
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+
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+static int
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+pfm_power8_detect(void* this)
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+{
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+ if (__is_processor(PV_POWER8))
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+ return PFM_SUCCESS;
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+ return PFM_ERR_NOTSUPP;
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+}
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+
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+pfmlib_pmu_t power8_support={
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+ .desc = "POWER8",
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+ .name = "power8",
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+ .pmu = PFM_PMU_POWER8,
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+ .pme_count = LIBPFM_ARRAY_SIZE(power8_pe),
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+ .type = PFM_PMU_TYPE_CORE,
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+ .num_cntrs = 4,
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+ .num_fixed_cntrs = 2,
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+ .max_encoding = 1,
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+ .pe = power8_pe,
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+ .pmu_detect = pfm_power8_detect,
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+ .get_event_encoding[PFM_OS_NONE] = pfm_gen_powerpc_get_encoding,
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+ PFMLIB_ENCODE_PERF(pfm_gen_powerpc_get_perf_encoding),
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+ PFMLIB_VALID_PERF_PATTRS(pfm_gen_powerpc_perf_validate_pattrs),
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+ .get_event_first = pfm_gen_powerpc_get_event_first,
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+ .get_event_next = pfm_gen_powerpc_get_event_next,
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+ .event_is_valid = pfm_gen_powerpc_event_is_valid,
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+ .validate_table = pfm_gen_powerpc_validate_table,
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+ .get_event_info = pfm_gen_powerpc_get_event_info,
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+ .get_event_attr_info = pfm_gen_powerpc_get_event_attr_info,
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+};
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diff --git a/lib/pfmlib_power_priv.h b/lib/pfmlib_power_priv.h
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index 2f66c22..2721771 100644
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--- a/lib/pfmlib_power_priv.h
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+++ b/lib/pfmlib_power_priv.h
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@@ -93,6 +93,7 @@ typedef struct {
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#define PV_POWER7p 0x004a
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#define PV_970MP 0x0044
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#define PV_970GX 0x0045
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+#define PV_POWER8 0x004b
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extern int pfm_gen_powerpc_get_event_info(void *this, int pidx, pfm_event_info_t *info);
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extern int pfm_gen_powerpc_get_event_attr_info(void *this, int pidx, int umask_idx, pfm_event_attr_info_t *info);
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diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h
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index d90f015..8e203d4 100644
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f1d3e6 |
--- a/lib/pfmlib_priv.h
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f1d3e6 |
+++ b/lib/pfmlib_priv.h
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f1d3e6 |
@@ -264,6 +264,7 @@ extern pfmlib_pmu_t power5_support;
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extern pfmlib_pmu_t power5p_support;
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f1d3e6 |
extern pfmlib_pmu_t power6_support;
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f1d3e6 |
extern pfmlib_pmu_t power7_support;
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+extern pfmlib_pmu_t power8_support;
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extern pfmlib_pmu_t torrent_support;
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extern pfmlib_pmu_t sparc_support;
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extern pfmlib_pmu_t sparc_ultra12_support;
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