diff --git a/.gitignore b/.gitignore
index 286aa88..6105b37 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1 @@
-SOURCES/libdrm-2.4.91.tar.bz2
+SOURCES/libdrm-2.4.97.tar.bz2
diff --git a/.libdrm.metadata b/.libdrm.metadata
index 70ffdd2..6bca21d 100644
--- a/.libdrm.metadata
+++ b/.libdrm.metadata
@@ -1 +1 @@
-44e42ce3cd41666e343ba393c73f6f1ad9fe1e74 SOURCES/libdrm-2.4.91.tar.bz2
+7635bec769a17edd140282fa2c46838c4a44bc91 SOURCES/libdrm-2.4.97.tar.bz2
diff --git a/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch b/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch
deleted file mode 100644
index d07e93f..0000000
--- a/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 50426f3e177c383a2de1c22534171c12461164a3 Mon Sep 17 00:00:00 2001
-From: Matt Atwood <matthew.s.atwood@intel.com>
-Date: Tue, 24 Apr 2018 12:42:39 -0700
-Subject: [PATCH libdrm] Intel: Add a Kaby Lake PCI ID
-
-Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")'
-
-v2: name change M -> ULX, add enumeration in KBL ULX
-v3: add entry to IS_KABYLAKE
-
-Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
-Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
----
- intel/intel_chipset.h | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
-index 01d250e8..ba2e3ac1 100644
---- a/intel/intel_chipset.h
-+++ b/intel/intel_chipset.h
-@@ -200,7 +200,8 @@
- #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
- #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
- #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
--#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E
-+#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
-+#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
- #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
- #define PCI_CHIP_KABYLAKE_M_GT2 0x5917
- #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
-@@ -455,7 +456,8 @@
-
- #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
-- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \
-+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
-+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
- (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
---
-2.17.1
-
diff --git a/SOURCES/0001-amdgpu-add-some-raven-marketing-names.patch b/SOURCES/0001-amdgpu-add-some-raven-marketing-names.patch
new file mode 100644
index 0000000..804fc43
--- /dev/null
+++ b/SOURCES/0001-amdgpu-add-some-raven-marketing-names.patch
@@ -0,0 +1,32 @@
+From 6415bd3ced9d80137e30cb90837eb01932607882 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Jan 2019 11:32:03 -0500
+Subject: [PATCH libdrm] amdgpu: add some raven marketing names
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ data/amdgpu.ids | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/data/amdgpu.ids b/data/amdgpu.ids
+index d9ed5660..d24c7ee6 100644
+--- a/data/amdgpu.ids
++++ b/data/amdgpu.ids
+@@ -4,6 +4,10 @@
+ # device_id, revision_id, product_name <-- single tab after comma
+
+ 1.0.0
++15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
++15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
++15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
++15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
+ 6600, 0, AMD Radeon HD 8600/8700M
+ 6600, 81, AMD Radeon (TM) R7 M370
+ 6601, 0, AMD Radeon (TM) HD 8500M/8700M
+--
+2.20.1
+
diff --git a/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch b/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch
deleted file mode 100644
index 8d3d731..0000000
--- a/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 7164abebecfbf450cdc55133eb3162f8c1501ff3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
-Date: Tue, 19 Jun 2018 16:45:21 -0700
-Subject: [PATCH libdrm] intel: Introducing Amber Lake platform
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Amber Lake uses the same gen graphics as Kaby Lake, including a id
-that were previously marked as reserved on Kaby Lake, but that now is
-moved to AML page.
-
-So, let's just move it to AML macro that will feed into KBL macro
-just to keep it better organized to make easier future code review
-but it will be handled as a KBL.
-
-This is a copy of merged i915's
-commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
-
-Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
-Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
----
- intel/intel_chipset.h | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
-index 44e65f9e..583d6447 100644
---- a/intel/intel_chipset.h
-+++ b/intel/intel_chipset.h
-@@ -201,7 +201,6 @@
- #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
- #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
- #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
--#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
- #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
- #define PCI_CHIP_KABYLAKE_M_GT2 0x5917
- #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
-@@ -213,6 +212,9 @@
- #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
- #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
-
-+#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C
-+#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0
-+
- #define PCI_CHIP_BROXTON_0 0x0A84
- #define PCI_CHIP_BROXTON_1 0x1A84
- #define PCI_CHIP_BROXTON_2 0x5A84
-@@ -468,12 +470,13 @@
- #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
-- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
- (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
-- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
-+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
-+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \
-+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
-
- #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
---
-2.17.1
-
diff --git a/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch b/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch
deleted file mode 100644
index 4a7cd8d..0000000
--- a/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
-Date: Tue, 19 Jun 2018 16:45:20 -0700
-Subject: [PATCH libdrm] intel: Introducing Whiskey Lake platform
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Whiskey Lake uses the same gen graphics as Coffe Lake, including some
-ids that were previously marked as reserved on Coffe Lake, but that
-now are moved to WHL page.
-
-So, let's just move them to WHL macros that will feed into CFL macro
-just to keep it better organized to make easier future code review
-but it will be handled as a CFL.
-
-This is a copy of merged i915's
-commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
-
-Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
-Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
----
- intel/intel_chipset.h | 33 +++++++++++++++++----------------
- 1 file changed, 17 insertions(+), 16 deletions(-)
-
-diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
-index 32b2c48f..44e65f9e 100644
---- a/intel/intel_chipset.h
-+++ b/intel/intel_chipset.h
-@@ -231,16 +231,17 @@
- #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
- #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
- #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
--#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
--#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
--#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
--#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
--#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
--#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
--#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
--#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
--#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
--#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
-+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9
-+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
-+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
-+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
-+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
-+
-+#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1
-+#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0
-+#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2
-+#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
-+#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
-
- #define PCI_CHIP_CANNONLAKE_0 0x5A51
- #define PCI_CHIP_CANNONLAKE_1 0x5A59
-@@ -510,16 +511,16 @@
- #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
- (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
-
--#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
-- (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
-- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
-- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
-- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
-+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
-- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
-+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \
-+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \
-+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \
-+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \
-+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3)
-
- #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
- IS_CFL_H(devid) || \
---
-2.17.1
-
diff --git a/SOURCES/0001-intel-add-support-for-ICL-11.patch b/SOURCES/0001-intel-add-support-for-ICL-11.patch
deleted file mode 100644
index 6eb1fa0..0000000
--- a/SOURCES/0001-intel-add-support-for-ICL-11.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 1ac3ecde2f2c9afd7110389eccc6860daa6627ca Mon Sep 17 00:00:00 2001
-From: Paulo Zanoni <paulo.r.zanoni@intel.com>
-Date: Wed, 25 Apr 2018 17:09:37 -0700
-Subject: [PATCH libdrm] intel: add support for ICL 11
-
-Add the PCI IDs and the basic code to enable ICL. This is the current
-PCI ID list in our documentation.
-
-Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs")
-
-v2: Michel provided a fix to IS_9XX that was broken by rebase bot.
-v3: Fix double definition of PCI IDs, update IDs according to bspec
- and keep them in the same order and rebase (Lucas)
-
-Cc: Michel Thierry <michel.thierry@intel.com>
-Reviewed-by: Michel Thierry <michel.thierry@intel.com>
-Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
-Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
----
- intel/intel_bufmgr_gem.c | 2 ++
- intel/intel_chipset.h | 27 ++++++++++++++++++++++++++-
- intel/intel_decode.c | 4 +++-
- 3 files changed, 31 insertions(+), 2 deletions(-)
-
-diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
-index 5c47a46f..8c3a4b20 100644
---- a/intel/intel_bufmgr_gem.c
-+++ b/intel/intel_bufmgr_gem.c
-@@ -3660,6 +3660,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
- bufmgr_gem->gen = 9;
- else if (IS_GEN10(bufmgr_gem->pci_device))
- bufmgr_gem->gen = 10;
-+ else if (IS_GEN11(bufmgr_gem->pci_device))
-+ bufmgr_gem->gen = 11;
- else {
- free(bufmgr_gem);
- bufmgr_gem = NULL;
-diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
-index ba2e3ac1..32b2c48f 100644
---- a/intel/intel_chipset.h
-+++ b/intel/intel_chipset.h
-@@ -257,6 +257,16 @@
- #define PCI_CHIP_CANNONLAKE_12 0x5A44
- #define PCI_CHIP_CANNONLAKE_13 0x5A4C
-
-+#define PCI_CHIP_ICELAKE_11_0 0x8A50
-+#define PCI_CHIP_ICELAKE_11_1 0x8A51
-+#define PCI_CHIP_ICELAKE_11_2 0x8A5C
-+#define PCI_CHIP_ICELAKE_11_3 0x8A5D
-+#define PCI_CHIP_ICELAKE_11_4 0x8A52
-+#define PCI_CHIP_ICELAKE_11_5 0x8A5A
-+#define PCI_CHIP_ICELAKE_11_6 0x8A5B
-+#define PCI_CHIP_ICELAKE_11_7 0x8A71
-+#define PCI_CHIP_ICELAKE_11_8 0x8A70
-+
- #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I915_GM || \
- (devid) == PCI_CHIP_I945_GM || \
-@@ -538,6 +548,20 @@
-
- #define IS_GEN10(devid) (IS_CANNONLAKE(devid))
-
-+#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_1 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_2 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_3 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_4 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_5 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_6 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_7 || \
-+ (devid) == PCI_CHIP_ICELAKE_11_8)
-+
-+#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid))
-+
-+#define IS_GEN11(devid) (IS_ICELAKE_11(devid))
-+
- #define IS_9XX(dev) (IS_GEN3(dev) || \
- IS_GEN4(dev) || \
- IS_GEN5(dev) || \
-@@ -545,6 +569,7 @@
- IS_GEN7(dev) || \
- IS_GEN8(dev) || \
- IS_GEN9(dev) || \
-- IS_GEN10(dev))
-+ IS_GEN10(dev) || \
-+ IS_GEN11(dev))
-
- #endif /* _INTEL_CHIPSET_H */
-diff --git a/intel/intel_decode.c b/intel/intel_decode.c
-index bc7b04b8..b24861b1 100644
---- a/intel/intel_decode.c
-+++ b/intel/intel_decode.c
-@@ -3823,7 +3823,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
- ctx->devid = devid;
- ctx->out = stdout;
-
-- if (IS_GEN10(devid))
-+ if (IS_GEN11(devid))
-+ ctx->gen = 11;
-+ else if (IS_GEN10(devid))
- ctx->gen = 10;
- else if (IS_GEN9(devid))
- ctx->gen = 9;
---
-2.17.1
-
diff --git a/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch b/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch
deleted file mode 100644
index 6ad7e37..0000000
--- a/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From 7b12381723021fd5fbcf761e6832dd16a14f52d4 Mon Sep 17 00:00:00 2001
-From: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Date: Wed, 7 Feb 2018 22:46:43 -0800
-Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs.
-
-Let's sync CNL ids with Spec and kernel.
-
-Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
-Add Cannonlake PCI IDs for another SKU.")' and
-commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'
-
-Cc: James Ausmus <james.ausmus@intel.com>
-Cc: Lucas De Marchi <lucas.demarchi@intel.com>
-Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
-Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
----
- intel/intel_chipset.h | 52 +++++++++++++++++++++++--------------------
- 1 file changed, 28 insertions(+), 24 deletions(-)
-
-diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
-index 3818e71e..01d250e8 100644
---- a/intel/intel_chipset.h
-+++ b/intel/intel_chipset.h
-@@ -241,16 +241,20 @@
- #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
- #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
-
--#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
--#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
--#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
--#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
--#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
--#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
--#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
--#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
--#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
--#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
-+#define PCI_CHIP_CANNONLAKE_0 0x5A51
-+#define PCI_CHIP_CANNONLAKE_1 0x5A59
-+#define PCI_CHIP_CANNONLAKE_2 0x5A41
-+#define PCI_CHIP_CANNONLAKE_3 0x5A49
-+#define PCI_CHIP_CANNONLAKE_4 0x5A52
-+#define PCI_CHIP_CANNONLAKE_5 0x5A5A
-+#define PCI_CHIP_CANNONLAKE_6 0x5A42
-+#define PCI_CHIP_CANNONLAKE_7 0x5A4A
-+#define PCI_CHIP_CANNONLAKE_8 0x5A50
-+#define PCI_CHIP_CANNONLAKE_9 0x5A40
-+#define PCI_CHIP_CANNONLAKE_10 0x5A54
-+#define PCI_CHIP_CANNONLAKE_11 0x5A5C
-+#define PCI_CHIP_CANNONLAKE_12 0x5A44
-+#define PCI_CHIP_CANNONLAKE_13 0x5A4C
-
- #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I915_GM || \
-@@ -515,20 +519,20 @@
- IS_GEMINILAKE(devid) || \
- IS_COFFEELAKE(devid))
-
--#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
-- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
-- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
-- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
-- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
-- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
--
--#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
-- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
-- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
-- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
--
--#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
-- IS_CNL_Y(devid))
-+#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_1 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_2 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_3 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_4 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_5 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_6 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_7 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_8 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_9 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_10 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_11 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_12 || \
-+ (devid) == PCI_CHIP_CANNONLAKE_13)
-
- #define IS_GEN10(devid) (IS_CANNONLAKE(devid))
-
---
-2.17.1
-
diff --git a/SOURCES/0001-intel-sync-i915_pciids.h-with-kernel.patch b/SOURCES/0001-intel-sync-i915_pciids.h-with-kernel.patch
new file mode 100644
index 0000000..c89712e
--- /dev/null
+++ b/SOURCES/0001-intel-sync-i915_pciids.h-with-kernel.patch
@@ -0,0 +1,117 @@
+From 70a1ae89be6b9f9a535f1fbaff3e4b1c4bb46d4a Mon Sep 17 00:00:00 2001
+From: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Date: Fri, 1 Feb 2019 23:43:01 -0800
+Subject: [PATCH libdrm] intel: sync i915_pciids.h with kernel
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Straight copy from the kernel file.
+
+Add more PCI Device IDs for Coffee Lake, Ice Lake,
+and Amber Lake. It also include a reorg on Whiskey Lake IDs.
+
+Align with kernel commits:
+
+5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
+03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
+c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
+c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")
+
+Cc: José Roberto de Souza <jose.souza@intel.com>
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+---
+ intel/i915_pciids.h | 29 +++++++++++++++++++++--------
+ 1 file changed, 21 insertions(+), 8 deletions(-)
+
+diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
+index fd965ffb..d2fad7b0 100644
+--- a/intel/i915_pciids.h
++++ b/intel/i915_pciids.h
+@@ -365,16 +365,20 @@
+ INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
+
+ /* AML/KBL Y GT2 */
+-#define INTEL_AML_GT2_IDS(info) \
++#define INTEL_AML_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
+
++/* AML/CFL Y GT2 */
++#define INTEL_AML_CFL_GT2_IDS(info) \
++ INTEL_VGA_DEVICE(0x87CA, info)
++
+ #define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info), \
+- INTEL_AML_GT2_IDS(info)
++ INTEL_AML_KBL_GT2_IDS(info)
+
+ /* CFL S */
+ #define INTEL_CFL_S_GT1_IDS(info) \
+@@ -390,6 +394,9 @@
+ INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
+
+ /* CFL H */
++#define INTEL_CFL_H_GT1_IDS(info) \
++ INTEL_VGA_DEVICE(0x3E9C, info)
++
+ #define INTEL_CFL_H_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+@@ -407,27 +414,29 @@
+
+ /* WHL/CFL U GT1 */
+ #define INTEL_WHL_U_GT1_IDS(info) \
+- INTEL_VGA_DEVICE(0x3EA1, info)
++ INTEL_VGA_DEVICE(0x3EA1, info), \
++ INTEL_VGA_DEVICE(0x3EA4, info)
+
+ /* WHL/CFL U GT2 */
+ #define INTEL_WHL_U_GT2_IDS(info) \
+- INTEL_VGA_DEVICE(0x3EA0, info)
++ INTEL_VGA_DEVICE(0x3EA0, info), \
++ INTEL_VGA_DEVICE(0x3EA3, info)
+
+ /* WHL/CFL U GT3 */
+ #define INTEL_WHL_U_GT3_IDS(info) \
+- INTEL_VGA_DEVICE(0x3EA2, info), \
+- INTEL_VGA_DEVICE(0x3EA3, info), \
+- INTEL_VGA_DEVICE(0x3EA4, info)
++ INTEL_VGA_DEVICE(0x3EA2, info)
+
+ #define INTEL_CFL_IDS(info) \
+ INTEL_CFL_S_GT1_IDS(info), \
+ INTEL_CFL_S_GT2_IDS(info), \
++ INTEL_CFL_H_GT1_IDS(info), \
+ INTEL_CFL_H_GT2_IDS(info), \
+ INTEL_CFL_U_GT2_IDS(info), \
+ INTEL_CFL_U_GT3_IDS(info), \
+ INTEL_WHL_U_GT1_IDS(info), \
+ INTEL_WHL_U_GT2_IDS(info), \
+- INTEL_WHL_U_GT3_IDS(info)
++ INTEL_WHL_U_GT3_IDS(info), \
++ INTEL_AML_CFL_GT2_IDS(info)
+
+ /* CNL */
+ #define INTEL_CNL_IDS(info) \
+@@ -452,9 +461,13 @@
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
++ INTEL_VGA_DEVICE(0x8A59, info), \
++ INTEL_VGA_DEVICE(0x8A58, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
++ INTEL_VGA_DEVICE(0x8A57, info), \
++ INTEL_VGA_DEVICE(0x8A56, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
+
+--
+2.20.1
+
diff --git a/SOURCES/README.rst b/SOURCES/README.rst
new file mode 100644
index 0000000..e47cb24
--- /dev/null
+++ b/SOURCES/README.rst
@@ -0,0 +1,61 @@
+libdrm - userspace library for drm
+----------------------------------
+
+This is libdrm, a userspace library for accessing the DRM, direct rendering
+manager, on Linux, BSD and other operating systems that support the ioctl
+interface.
+The library provides wrapper functions for the ioctls to avoid exposing the
+kernel interface directly, and for chipsets with drm memory manager, support
+for tracking relocations and buffers.
+New functionality in the kernel DRM drivers typically requires a new libdrm,
+but a new libdrm will always work with an older kernel.
+
+libdrm is a low-level library, typically used by graphics drivers such as
+the Mesa drivers, the X drivers, libva and similar projects.
+
+
+Compiling
+---------
+
+libdrm has two build systems, a legacy autotools build system, and a newer
+meson build system. The meson build system is much faster, and offers a
+slightly different interface, but otherwise provides an equivalent feature set.
+
+To use it:
+
+ meson builddir/
+
+By default this will install into /usr/local, you can change your prefix
+with --prefix=/usr (or `meson configure builddir/ -Dprefix=/usr` after
+the initial meson setup).
+
+Then use ninja to build and install:
+
+ ninja -C builddir/ install
+
+If you are installing into a system location you will need to run install
+separately, and as root.
+
+
+Alternatively you can invoke autotools configure:
+
+ ./configure
+
+By default, libdrm will install into the /usr/local/ prefix. If you
+want to install this DRM to replace your system copy, pass
+--prefix=/usr and --exec-prefix=/ to configure. If you are building
+libdrm from a git checkout, you first need to run the autogen.sh
+script. You can pass any options to autogen.sh that you would other
+wise pass to configure, or you can just re-run configure with the
+options you need once autogen.sh finishes.
+
+Next step is to build libdrm:
+
+ make
+
+and once make finishes successfully, install the package using
+
+ make install
+
+If you are installing into a system location, you will need to be root
+to perform the install step.
diff --git a/SOURCES/libdrm-2.4.25-check-programs.patch b/SOURCES/libdrm-2.4.25-check-programs.patch
index 5debb03..8006516 100644
--- a/SOURCES/libdrm-2.4.25-check-programs.patch
+++ b/SOURCES/libdrm-2.4.25-check-programs.patch
@@ -1,10 +1,10 @@
-diff -up libdrm-2.4.82/tests/Makefile.am.check libdrm-2.4.82/tests/Makefile.am
---- libdrm-2.4.82/tests/Makefile.am.check 2017-08-10 09:44:12.380441220 +1000
-+++ libdrm-2.4.82/tests/Makefile.am 2017-08-10 09:45:13.349056689 +1000
-@@ -45,3 +45,6 @@ TESTS = \
- check_PROGRAMS = \
- $(TESTS) \
- drmdevice
+diff -up libdrm-2.4.97/tests/Makefile.am.check libdrm-2.4.97/tests/Makefile.am
+--- libdrm-2.4.97/tests/Makefile.am.check 2019-01-31 11:00:21.248243193 +1000
++++ libdrm-2.4.97/tests/Makefile.am 2019-01-31 11:05:28.380528292 +1000
+@@ -51,3 +51,6 @@ bin_PROGRAMS = drmdevice
+ else
+ check_PROGRAMS += drmdevice
+ endif
+
+check-programs:
+ @echo $(check_PROGRAMS)
diff --git a/SPECS/libdrm.spec b/SPECS/libdrm.spec
index 4d5ff6a..aaf8943 100644
--- a/SPECS/libdrm.spec
+++ b/SPECS/libdrm.spec
@@ -2,8 +2,8 @@
Summary: Direct Rendering Manager runtime library
Name: libdrm
-Version: 2.4.91
-Release: 3%{?dist}
+Version: 2.4.97
+Release: 2%{?dist}
License: MIT
Group: System Environment/Libraries
URL: http://dri.sourceforge.net
@@ -33,6 +33,7 @@ BuildRequires: valgrind-devel
BuildRequires: xorg-x11-util-macros
Source2: 91-drm-modeset.rules
+Source3: README.rst
# hardcode the 666 instead of 660 for device nodes
Patch3: libdrm-make-dri-perms-okay.patch
@@ -41,12 +42,10 @@ Patch4: libdrm-2.4.0-no-bc.patch
# make rule to print the list of test programs
Patch5: libdrm-2.4.25-check-programs.patch
-# backport new intel pci-ids
-Patch10: 0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch
-Patch11: 0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch
-Patch12: 0001-intel-add-support-for-ICL-11.patch
-Patch13: 0001-intel-Introducing-Whiskey-Lake-platform.patch
-Patch14: 0001-intel-Introducing-Amber-Lake-platform.patch
+# amdgpu names update
+Patch10: 0001-amdgpu-add-some-raven-marketing-names.patch
+# intel pciids update
+Patch11: 0001-intel-sync-i915_pciids.h-with-kernel.patch
%description
Direct Rendering Manager runtime library
@@ -74,12 +73,8 @@ Utility programs for the kernel DRM interface. Will void your warranty.
%patch3 -p1 -b .forceperms
%patch4 -p1 -b .no-bc
%patch5 -p1 -b .check
-
-%patch10 -p1
-%patch11 -p1
-%patch12 -p1
-%patch13 -p1
-%patch14 -p1
+%patch10 -p1 -b .amdnames
+%patch11 -p1 -b .intelid
%build
autoreconf -v --install || exit 1
@@ -95,6 +90,7 @@ make %{?_smp_mflags}
pushd tests
make %{?smp_mflags} `make check-programs`
popd
+cp %{SOURCE3} .
%install
make install DESTDIR=$RPM_BUILD_ROOT
@@ -104,6 +100,7 @@ for foo in $(make check-programs) ; do
libtool --mode=install install -m 0755 $foo %{buildroot}%{_bindir}
done
popd
+
# SUBDIRS=libdrm
mkdir -p $RPM_BUILD_ROOT/usr/lib/udev/rules.d/
install -m 0644 %{SOURCE2} $RPM_BUILD_ROOT/usr/lib/udev/rules.d/
@@ -120,7 +117,7 @@ done
%files
%defattr(-,root,root,-)
-%doc README
+%doc README.rst
%{_libdir}/libdrm.so.2
%{_libdir}/libdrm.so.2.4.0
%ifarch %{ix86} x86_64 ia64
@@ -243,6 +240,12 @@ done
%{_mandir}/man7/drm*.7*
%changelog
+* Wed Feb 20 2019 Dave Airlie <airlied@redhat.com> - 2.4.97-2
+- Add some new i915 pci ids, and amd marketing names
+
+* Thu Jan 31 2019 Dave Airlie <airlied@redhat.com> - 2.4.97-1
+- libdrm 2.4.97 (readd README)
+
* Wed Aug 22 2018 Rob Clark <rclark@redhat.com> - 2.4.91-3
- Add WHL, AML, etc PCI IDs